GB2251124A

GB2251124A - Conductivity modulation type mosfet

Info

Publication number: GB2251124A
Application number: GB9126379A
Authority: GB
Inventors: Yasukazu Seki
Original assignee: Fuji Electric Co Ltd
Current assignee: Fuji Electric Co Ltd
Priority date: 1990-12-17
Filing date: 1991-12-12
Publication date: 1992-06-24
Anticipated expiration: 2011-12-12
Also published as: JPH04216675A; GB2251124B; DE4141495A1; GB9126379D0

Abstract

A conductivity modulation type MOSFET including a highly doped buffer layer (2) whose impurity concentration is at least 1 x 10<17> atoms/cm<3> so that the buffer layer (2) can function to reduce the injection efficiency of carriers to an adjacent high resistivity layer (3). This will prevent the carrier transport efficiency of the high resistivity layer (3) from decreasing, which is caused by the effect of lifetime killers, and shortens a turn-off time of the device. Thickness of the buffer layer (2) is made equal to or less than 15 mu m so as to prevent increase in the ON-state voltage of the device. Tradeoff relationship between the turn-off time and ON-state voltage of the device can be further improved by diffusion of a certain amount of lifetime killers and irradiation of charged particles. <IMAGE>

Description

22311 4 1 CONDUCTIVITY MODULATION TYPE MOSFET The present invention

relates to a conductivity modulation type MOSFET which includes a bipolar transistor and a MOSFET as its integral parts, and in which a base current of the bipolar transistor is supplied by a channel current of the MOSFET.

A conductivity modulation type MOSFET is also called an IGBT (Insulated Gate Bipolar Transistor), and has attracted considerable attention recently, as a power switching device available instead of a power MOSFET. The conductivity modulation type MOSFET has a high input impedance of a MOSFET, and has a low ON-state resistance of a bipolar transistor.

Fig. I illustrates a basic structure of a conductivity modulation type MOSFET. This structure comprises a p+ substrate 1, a heavily doped n+ buffer layer 2 grown on the p+ substrate 1 by the epitaxial process or the like, a lightly doped n- layer 3 formed on the n+ buffer layer 2, p well layers 4 selectively formed in the surface of the n- layer 3 and n+ source layers 5 selectively formed in the surface of the p well layers 4. Channels 41 are to be formed in surface regions of the p well layer 4 between a top portion of the n- layer 3 and the n+ source layers 5. A gate electrode 7 is disposed on that surface regions via a gate insulating layer 6, - 2 and is connected to a gate terminal G. Further, a source electrode 8 which is connected to a source terminal S is disposed on both source layer 5 and P well layer 4, and a drain electrode 9 which is connected to a drain terminal D is formed on the bottom surface of the p+ substrate 1.

In such a conductivity type MOSFET, hole injection from p+ layer 1 to the n- layer 3 through the n+ buffer layer 2 occurs in response to an electron current injected from the source layers 5 to the n layer 3 through the channel regions 41, thereby turning on the conductivity type MOSFET. In this case, the conductivity modulation occurs in a part of the n layer 3 and the n+ buffer layer 2. Holes injected into the n- layer 3 pass immediately under the source layer 5 in the p well 4, thus reaching the source electrode 8. Since the source electrode 8 electrically short-circuits the p well layer 4 and the n+ source layer 5, a thyristor operation of the four layer structure, which comprises the p+ layer 1, the n+ buffer layer 2 and n- layer 3, the p well layer 4 and the n+ layer 5, is prevented so that the device can be turned off by applying zero voltage across the gate and source. In short, the conductivity modulation type MOSFET is different from a common vertical type power DMOSFET in that it includes the p+ layer 1, which is formed on the bottom surface of the drain region (the n+ buffer layer 2 and n- layer 3) and has the opposite 3 conductivity type to that of the drain region. so as to induce a conductivity modulation.

The conductivity modulation type MOSFET has a very low ON-state resistance because it induces conductivity modulation in the n- layer 3, which greatly increases carriers. Although the ON-state resistance of the device can be reduced by the conductivity modulation, it is not practical for the device if the turn-off or turn-on switching time lengthens. The switching time lengthens as the number of carriers increases, and therefore, the power dissipation during switching increases. Since the ON-state resistance and the switching time have a tradeoff relationship, the way to improve the tradeoff relationship is a key point to determine the characteristics of the device. In practice, the improvement is achieved by introducing lifetime killers that remarkably shorten the lifetime of carriers.

The degree of the conductivity modulation and that of introduction of lifetime killers include know-how that governs the characteristics of the device. The degree of the conductivity modulation not only depends on the electron current flowing through the channel regions 41, but also depends considerably on the hole injection into the n- layer 3. The hole injection is controlled by the n+ buffer layer 2: the resistivity of the n+ buffer layer 2 or the impurity concentration of the layer 2, and the thickness of the layer 2 control the degree of the conductivity modulation. The formation of the n+ buffer layer 2 is disclosed by U.S. Patent No. 4,364,073, Japanese Patent Application Laying-open No. 60-117673 (1985) which discloses the following technique: By increasing the ratio of the electron current to the hole current in the ON state drain current by the n+ buffer layer, a greater-current reduction is achieved when the electron current is broken by making the gate voltage zero. Thus, the turn-off time of this device can be shortened to half that of a conventional device. To accomplish this effect, the impurity concentration of the n+ buffer layer 2 must be at least 3 X 1014 atoms/cm3.

The most important point in the turn-off operation of the IGBT is to quicken the cutoff of the current. In the ON state, the n- layer 3 is filled with carriers because of the conductivity modulation taking place in the n- layer 3. When the gate is cut off in this state, the path of electrons supplied through the channel regions 41 is interrupted. The current of the device, however, tried to maintain itself even after the cutoff of the gate because a load of the IGBT device is usually a motor or the like that includes an inductance component. In the device, a depletion layer continuously grows so as to maintain this current which can be expressed by the following equation:

I = a X C X (dV/dt) - where a is a fixed value; and C is a depletion layer capacitance.

Fig. 2 illustrates movement of carriers inside the IGBT when turned off. As a depletion layer 31 grows in the n- layer 3 during the turn-off operation, holes 11 fall into the depletion layer 31. The holes 11 fallen into the depletion layer 31 are quickly accelerated by the electric field in the depletion layer 31 so as to get through to source side. Electrons 12, on the other hand, are pushed by the growth of the depletion layer 31 towards the p+ layer 1. Lifetime killers, when introduced, not only decrease transport factor of carriers but also shorten the lifetime of the carriers. Accordingly, the depletion layer 31 must further grow to maintain the device current. As a result of the depletion layer spreading, the remaining thickness of the n- layer 3 reduces, so that the current gain of a PNP transistor built inside the IGBT increases. Thus, hole reinjection during the turn-off operation is enhanced, thereby lengthening the turn-off time.

Another problem involved in introducing the lifetime killers is that the turn-off characteristic is degraded as the temperature rises. The reason for this is as follows: When introducing the lifetime killers, injection efficiency from the drain side is set at a considerably large amount in advance taking account of reduction in transport efficiency caused by recombination - 6 of carriers by lifetime killers inside the device. In this case, as temperature rises, the forward energy barrier of the pn junction at the drain side decreases, and hence the hole injection increases. In addition, the effect of lifetime killers declines as the temperature rises because of the following reason as stated in many papers: when the temperature rises, valence electrons constituting recombination centers are thermally activated; this hinders recombination of carriers through the intermediary of the recombination centers; and hence, the lifetime killers lose their effect.

Although efficiency of lifetime killers is different depending on their types because recombination energy levels built in silicon vary in accordance with the types, it still holds true that the efficiency of lifetime killers declines as the temperature elevates. Although it is generally recognized that employing lifetime killers and increasing injection efficiency to use the lifetime killers have adverse effects against temperature rise, it cannot have been avoided to use lifetime killers.

Accordingly, it is an object of the present invention to provide a conductivity modulation type MOSFET, which eliminates the above-described disadvantages associated with the conventional techniques to prevent adverse effects of lifetime killers so that - 7 turn-on time can be shortened without much increase in an ON-state resistance of a device, thereby improving the tradeoff relationship between a turn-on time and an ONstate voltage so as to reduce a total loss. 5 According to an aspect of the present invention, there is provided a conductivity modulation type MOSFET comprising: first layer of a first conductivity type; buffer layer of a second conductivity type formed on the first layer, the buffer layer being highly doped; a second layer of the second conductivity type formed on the buffer layer, the second layer being lightly doped; a well layer of the first conductivity type selectively formed in a surface of the second layer; a source layer of the second conductivity type selectively formed in a surface of the well layer; the source layer being heavily doped; a channel region in the surface of the well layer between the source layer and the second layer; a gate electrode disposed on the channel region via an insulating layer; a source electrode making common contact with surfaces of the source layer and the well layer; and a drain electrode making contact with the first layer, wherein impurity concentration of the buffer layer is at least 1 X 1017 atoms/CM3 and thickness of the buffer layer is equal to or less than 15 gm.

Here, at least the second layer and the buffer layer may comprise heavy metal elements distributed therein as lifetime killers.

At least the second layer and the buffer layer may be irradiated by a charged particle beam.

The buffer layer may have an impurity concentration of 0.8 1.2 X 1018 atoms/CM3 and a thickness of 8 - 12 9m - According to the present invention, the buffer layer has an impurity concentration of at least 1 X 1017 atoms/cm3 and a thickness equal to or less than 15 gm so that a carrier injection into the second layer (high resistivity layer) is restricted. This makes it possible to shorten the turn-off time without much increase in the ON-state voltage, thus improving the tradeoff relationship between the turn-off time and the ONstate voltage.

Moreover, when lifetime killers are diffused into the device, they are trapped in the highly doped buffer layer. As a result, the lifetime killers are located at an ideal position in the second layer. Thus, the diffusion of lifetime killers can be compatible with the succeeding process for generating the lifetime killers by rz irradiation of a charged particle beam so as to compensate the profile of distributed lifetime killers.

The switching time of the device can be shortened even when lifetime killers are not used. When lifetime killers are not used, adverse effects of the lifetime killers can be avoided. In other words, a conductivity modulation type MOSFET can be obtained that little changes its electric characteristics both at a high temperature and at an ordinary temperature. This will further improve reliability of the device. In addition, since no heavy metal element causing contamination is used and a step for diffusing lifetime killers is removed from the process, total cost of the device will be reduced.

The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of the embodiments thereof taken in conjunction with the accompanying drawings.

Fig. 1 is a cross sectional view illustrating a basic structure of a conductivity modulation type MOSFET of the present invention; Fig. 2 is a schematic cross sectional view illustrating movement of carriers inside the IGBT when turned off; - 10 Fig. 3 is a graph illustrating carrier density profile in the thickness direction across an n- layer 3 of Fig. 1 when the device undergoes conductivity modulation; Fig. 4 is a diagram illustrating waveforms of a turn-off current i and a turn-off voltage V associated with curves A and B of Fig. 3; Fig. 5 is a diagram illustrating tradeoff curves showing relationships between the ON-state voltage and the turn-off time of samples 21 - 25 when the diffusion temperature of gold is varied from 840C to HO'C; Fig. 6 is a diagram showing gold density profile in the thickness direction across the IGBT associated with the sample 22; Fig. 7 is a diagram illustrating tradeoff curves showing relationships between the ON-state voltage and the turn-off time of other samples of a first embodiment of the present invention; and Fig. 8 is a diagram illustrating a curve 82 showing a tradeoff relationship of a second embodiment of the present invention and a curve 81 showing that of a conventional device.

The invention will now be described with reference to the accompanying drawings.

First, let us consider the basic operation of a conductivity modulation type MOSFET as an IGBT including an n+ buffer layer which has impurity concentration of at least 5 X 1017 atoms/CM3, and thickness less than or equal to 15 gm.

Fig. 3 is a graph illustrating carrier density profiles across an n- layer 3 of Fig. 1 along its thickness direction when a device is conducted, that is, when the device undergoes conductivity modulation. In this figure, the left-hand side of the abscissa is a source side, and the right-hand side thereof is a drain side. A curve A represents a carrier density across the n- layer 3 when an n+ buffer layer has a conventional structure, whereas a curve B indicates a carrier density across the n- layer 3 when an n+ buffer layer has the impurity concentration and thickness specified in accordance with the present invention as mentioned above.

In Fig. 3, the carrier densities are high at both source side and drain side because of injection of electrons from the source side and that of holes from the drain side. The curves A and B suppose a similar ON- state voltage. In the conventional device corresponding to the curve A whose n+ buffer layer 2 has a high resistivity or low impurity concentration, injections from the drain side and the source side are large. The carrier density, however, sharply decreases at the center of the n- layer 3 as shown by the curve A of Fig. 3 because carriers eliminate there by recombination by lifetime killers. In contrast, in the device of the present invention corresponding to the curve B, the resistivity of the n+ buffer layer 2 is specified low, i.e., the impurity concentration is set high so as to restrict the hole injection. Therefore, it is necessary to decrease the carrier density difference in the nlayer 3 by limiting the effect of lifetime killers to obtain the same ON-state voltage as with the curve A. Next, a turn-off operation of the IGBT which has the same ON-state voltage but has different carrier distribution is considered.

Fig. 4 is a diagram illustrating waveforms of a turn-off current i and a turn-off voltage V with regard to the curves A and B of Fig. 3. In this figure, the abscissa represents time and the ordinate represents the turnoff currents and voltages corresponding to the curves A and B of Fig. 4. First, the difference between the curves A and B are considered in terms of voltage rising after the gate is cut off. With regard to the curve A, since the depletion layer must be grown to a large extent to maintain the current as described above, the device voltage quickly rises as indicated by the curve A(V) of Fig. 4. In contrast with this, with regard to the curve B, since the transport efficiency of carriers is high owing to the limitation of the effect of lifetime killers, the current can be readily maintained without widening the depletion layer. As a result, the voltage rises as B(V) of Fig. 4. Each of the curves A 13 and B tries to maintain its current by sharply rising the voltage when the depletion layer reaches the n+ buffer layer 2. The voltage, however, is usually clamped at a fixed voltage by an external circuit, and hence, the current sharply decreases as shown by the curves A(i) and B(i). Switching loss so far can be estimated by the product of the voltage multiplied by the current, and is smaller in curves B than in curves A as is clearly shown in Fig. 4.

Succeeding current waveforms of the turn-off operation can be considered as follows: Since the voltage is clamped at the fixed value after the depletion layer reaches the n+ buffer layer 2, the current cannot be maintained by further growing the depletion layer, resulting in a sharp decrease in the current. The behavior of the device until the depletion layer reaches the n+ layer associated with the curve B is different from that associated with the curve A in the following: As the depletion layer grows in the n- layer 3, the base region (the layers 2 and 3 of Fig. 1) of the major PNP transistor inside the IGBT is gradually narrowed, and the current gain hFE of the PNP transistor increases as the base is narrowed. With the curves A and B, however, the transport efficiency of carriers is greatly different: the difference depending on positions in the thickness direction of the base. With the curve A, since the transport efficiency is low originally, the current gain - 14 hFE sharply increases as the thickness of the base layer reduces. With the curve B, on the other hand, since the transport efficiency little varies with the position along the thickness direction, the current gain hFE scarcely changes even when the base layer is thinned. This means that the number of electrons pushed out of the base region to the drain region owing to the growth of the depletion layer is smaller in the curve B than that in the curve A, and hence, the number of holes reinjected into the base region from the drain region is also smaller in the curve B in comparison with that of the curve A. Thus, the reduction behavior of the current in the turn-off operation is different with the curves A and B as shown in Fig. 4. Since the tail (falling edge) current caused by the increase in the hFE as indicated by the curve B is smaller than in the curve A, the turn-off time of the device of the present invention is shorter than that of the conventional device. In addition, the curve B of the present invention has another advantage: the turn-off characteristic at a high temperature is scarcely different from that at a low temperature because the effect of lifetime killers is limited even though the injection efficiency is specified at a low value. Furthermore, the increase in the ON-state voltage is prevented by making the thickness of the n+ buffer layer less than or equal to 15 Rm.

Moreover, since heavy metal element particles distributed in semiconductor layers including a heavily doped buffer layer according to the present invention are selectively located close to the heavily doped buffer layer, the turn-off rate is increased without much increase in the ON- state voltage, thereby improving the tradeoff relationship between the ON- state voltage and the switching time. The effects described above can be achieved in a p-channel IGBT in which each layer has opposite conductivity type to that of the above IGBT.

EMBODIMENT 1 As shown in Table I, a several types of IGBTs were made by changing the n+ buffer layer 2 of the IGBT having the structure as shown in Fig. 1, and the tradeoff relationships between the ON-state voltage and the turnoff time were measured when the diffusion temperature of gold as lifetime killers was altered. Here, resistivity and thickness of the p+ layer 1 are 0.018 - 0.020 2-cm and 400 - 500 Rm, respectively, and those of the n- layer 3 are 100 - 200 Q- cm and 50 - 120 Rm, respectively. The resistivity and thickness of the n- layer 3 changes according to a withstanding voltage of a device.

TABLE I VARIABLES OF THE N+ BUFFER LAYER OF SAMPLE IGBTS SAMPLE NO. IMPURITY CONCENTRATION THICKNESS 21 3 X 1017 (atoms/CM3) 10 gm 22 5 X 1017 23 24 7 X 1016 5 X 1017 5 X 1017 10 20 7 Diffusion process of gold is carried out after the PSG (phospho-silicate glass) gate insulating layer 6 between the gate electrode 7 and the source layer 5 has been formed. First, water glass containing gold is coated on the bottom surface of a wafer and is dried.

Subsequently, the gold is diffused in an ordinary diffusion furnace, or is diffused by rising temperature to 700 - 900 C. The temperature and diffusion time vary depending on a device (whether a high-speed device or a low-speed device).

Fig. 5 is a graph illustrating tradeoff curves showing relationships between the ON-state voltage and the turn-off time of the samples 21 when the diffusion temperature of the gold is varied from 840 'C to 880 C. In this figure, the diffusion temperature increases as the curve proceeds toward the right-hand. The samples 23 and 24 have tradeoff relationships similar to that of a conventional device.

It is seen from this figure that the tradeoff relationships are greatly improved by making the impurity concentration of the n+ buffer layer 2 at least 1 X 1017 atoms/CM3, and the thickness thereof is equal to or less 5 than 15 gm.

Since the resistivity of the n+ buffer layer 2 of these samples is selected at a sufficiently low value, hole injection from the p+ layer 1 into the n+ buffer layer is very limited. As a result, an excessively thick n+ buffer layer 2 would increase the ON-state voltage, thereby degrading the tradeoff relationship. Judging from Fig. 5, thickness equal to or less than 15 gm is preferable. An excessively thin n+ buffer layer 2, on the other hand, cannot achieve another role of the n+ buffer layer: it cannot withstand a high voltage. Thus, the n+ buffer layer must be at least 3 gm thick.

Fig. 6 is a diagram showing gold density profile localized in the thickness direction across the IGBT associated with the sample 22. The gold density is measured in terms of spreading resistance. By making the resistivity of the n+ buffer layer low, the gold is placed at this portion C, and spreads into the n- layer 3 or a portion D. It is preferable that lifetime killers be localized at positions where the conductivity modulation is easiest to take place, that is, in the n+ and n- layers 2 and 3. Lifetime killers diffused in the whole device will only serve to increase ON-state 18 voltage. To effectively reduce the turn-off time of the device without increasing the ON-state voltage, it is necessary to localize lifetime killers at such position D as shown in Fig. 6 where the conductivity modulation occurs. Thus, improvement in the tradeoff relationship can be achieved.

Next, an IGBT whose n+ buffer layer 2 is identical to the sample 22 (that is, the impurity concentration is 5 X 1017 atoms/cm3 and the thickness is 10 gm) is formed by the succeeding gold diffusion and electron beam irradiation. The electron beam irradiation is carried out immediately before the drain electrode 9 is formed at the final stage of the device fabrication process. The diffusion temperature of gold is varied from 840 C to 880 C so that the tradeoff relationship is obtained as shown in Fig. 7. In Fig. 7, a curve 71 represents the tradeoff relationship of a conventional device, and a curve 22 represents that of the sample 22, and a curve 73 represents that of the above-described sample subjected to the gold diffusion and the electron beam irradiation. The tradeoff relationship of a sample 73 associated with the curve 73 is further improved by irradiating an electron beam to the IGBT corresponding to the sample 22 that contains lifetime killers in the position D near the n+ buffer layer 2 as shown in Fig. 6 so that lifetime killers are generated evenly in the thickness direction 19 of the n- layer 3 in such a manner that the shortage of the lifetime killers is compensated by the irradiation.

A device having opposite conductivity type layers to those of the device of Fig. 1 can achieve similar effects as the above examples by forming a p+ buffer layer between a p- layer and an n+ layer corresponding to the nlayer 3 and the p+ layer 1 of Fig. 1, respectively, as long as the p+ buffer layer has an impurity concentration of 1.5 X 1018 atoms/CM3 and a thickness equal to or less than 15 gm.

EMBODIMENT 2 Fig. 8 is a graph illustrating a curve 82 showing a tradeoff relationship of a second embodiment of the present invention and a curve 81 showing that of a conventional device. The second embodiment of an IGBT according to the present invention was fabricated by making the n+ buffer layer of the IGBT as shown in Fig. 1 such that the impurity concentration was 1 X 1018 atoms/CM3. and the thickness was 10 gm, without performing gold diffusion process. The curve 82 representing tradeoff relationship of the second embodiment in Fig. 8 was obtained by altering the resistivity and thickness of the n+ buffer layer 2 of the embodiment, whereas the curve 81 was obtained by modifying the introduction amount of lifetime killers in the conventional device.

The second embodiment aims at reducing the hole injection efficiency from the drain side by decreasing the resistance of the n+ buffer layer 2, that is, by increasing the impurity concentration of the n+ buffer layer 2. When the resistance of the n+ buffer layer 2 is reduced to an extreme, however, no hole injection comes to take place at last, and the device cannot conduct, or can conduct only with a high ON-state voltage. For this reason, it is preferable that the impurity concentration of the buffer layer be set between 0.8 - 1.2 X 1018 atoms/CM3, and it is further preferable that not only the resistivity but also the thickness of the buffer layer be limited between 8 - 12 gm. A thicker layer than that will restrict the hole injection or cause a high ON-state voltage.

The second embodiment attempts to limit the hole injection by controlling only the resistivity and thickness of the n+ buffer layer 2 so that the ON-state voltage is not inferior to that of a conventional device.

Accordingly, lifetime killers are not necessary. In other words, the second embodiment enables to maintain a low ON-state voltage, which is liable to increase owing to the reduction of the injection efficiency, by increasing transport factor without using lifetime killers. An IGBT according to the second embodiment has an advantage that its electric characteristics little change under a high temperature because it uses reduction 21 in the hole injection efficiency rather than lifetime killers.

The present invention has been described in detail with respect to various embodiments, and it will now be apparent from the foregoing to those skilled in the art that changes and modifications may be made without departing from the invention in its broader aspects, and it is the intention, therefore, in the appended claims to cover all such changes and modifications as fall within 10 the true spirit of the invention.

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Claims

Claims: 1. A conductivity modulation type MOSFET, characterized by comprising: first layer of a first conductivity type; buffer layer of a second conductivity type formed on said first layer, said buffer layer being high ly doped; a second layer of the second conductivity type formed on said buffer layer, said second layer being lightly doped; a well layer of the first conductivity type selectively formed in a surface of said second layer; a source layer of the second conductivity type selectively formed in a surface of said well layer; said source layer being heavily doped; a channel region in the surface of said well layer between said source layer and said second layer; a gate electrode disposed on said channel region via an insulating layer; a source electrode making common contact with surfaces of said source layer and said well layer; and a drain electrode making contact with said first layer, wherein impurity concentration of said buffer layer is at least 1 X 1017 atoms/CM3 and thickness of said buffer layer is equal to or less than 15 1m.

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2. A conductivity modulation type MOSFET as claimed in claim 1, characterized in that at least said second layer and said buffer layer comprise heavy metal particles distributed therein as lifetime killers.

3. A conductivity modulation type MOSFET as claimed in claim 2, characterized in that at least said second layer and said buffer layer is irradiated by a charged particle 10 beam.

4. A conductivity modulation type MOSFET as claimed in claim 1, characterized in that said buffer layer has an impurity concentration of 0.8 - 1.2 X 1018 atoms/CM3 and a thickness of 8 - 12 gm.

5. A semiconductor device providing a bipolar transistor structure and a field effect transistor structure such that the channel current of the field effect transistor provides the base current of the bipolar transistor, the bipolar structure comprising a buffer layer between the base region and the emitter region which buffer layer has the same conductivity type as the base region but a higher impurity concentration, the buffer layer having a thickness of up 17 3 to 15 micrometre and an impurity concentration of 10 cm6. A semiconductor device substantially as herein described with reference to the accompanying drawings as an embodiment of the invention.