JPH04216675A - Conductivity modulation type mosfet - Google Patents

Abstract

PURPOSE:To reduce the total loss by improving the trade-off relation between the turn-OFF time and the ON-voltage of a conductivity modulation type MOSFET. CONSTITUTION:Impurity concentration of a buffer layer 2 is increased to be higher than or equal to 1X10<17>cm<-3>, and the carrier injection efficiency to a high resistance layer is decreased. Thereby the effect of lifetime killer can be restrained. Hence the decrease of carrier transfer efficiency of the high resistance layer is prevented, and the turn-OFF time is shortened. The buffer layer 2 is set to thinner than or equal to 15mum, thereby preventing the increase of ON-voltage. Trade-off can be more improved by using the diffusion of lifetime killer together with the irradiation of charged particles.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a conductivity modulated MOSFET in which the base current of a bipolar transistor is supplied by the channel current of a MOSFET.

0002

[Prior Art] A conductivity modulated MOSFET is an insulated gate bipolar transistor (Insulated gate type bipolar transistor).
Gate Bipolar Transistor,I
GBT). In recent years, conductivity modulation type MOSFETs have been attracting attention as power switching elements that can replace power MOSFETs. This conductivity modulation type MOSFET has a high input impedance like a MOSFET, and can have a low on-resistance like a bipolar transistor. Figure 1 shows its basic structure. In this structure, p
+ A p-well layer 4 is selectively formed in the surface layer of a low impurity concentration n- layer 3 laminated on the substrate 1 via a high impurity concentration n+ buffer layer 2 by, for example, an epitaxial method, and further in the surface layer. An n+ source layer 5 is selectively formed thereon. A surface portion of the p-well layer 4 sandwiched between the exposed portion of the n- layer 3 and the n+ source layer 5 is a channel region 4.
1, a gate electrode 7 connected to a gate terminal G via a gate insulating film 6 is provided thereon. Then, on the source layer 5, there is a source electrode 8 which contacts the well layer 4 at the same time and is connected to the source terminal S, and also has a p+ substrate 1.
A drain electrode 9 connected to the drain terminal D is provided on the back surface of the drain electrode 9 . Such conductivity modulated MOSFET
Now, with respect to the electron current injected from the source layer 5 to the n- layer 3 through the channel region 41 by applying a voltage between the gate and the source, a positive current is injected from the p+ substrate 1 to the n- layer 3 via the n+ layer 2. Hole injection occurs and turns on. At this time, conductivity modulation occurs in part of the n- layer 3 and n+ layer 2. The holes injected into the n- layer 3 pass directly under the source layer 5 of the p-well layer 4 and escape to the source electrode 8. Since the source electrode 8 electrically shorts the p layer 4 and the n+ source layer 5, the p+ layer 1, the n+ layer 2, the n- layer 3,
The device can be turned off by blocking the operation of the thyristor of the four-layer structure consisting of the p layer 4 and the n+ layer 5, and reducing the gate-source voltage to zero. That is, this conductivity modulation type MOSFET differs from the conventional power vertical DMOSFET in that a p+ layer 1 of the opposite conductivity type is provided on the back surface of the drain region to cause conductivity modulation.

As mentioned above, in the conductivity modulation type MOSFET, conductivity modulation occurs in the n- layer 3, so that the resistance of the element is significantly lowered. This is due to the significant increase in carriers due to conductivity modulation. By causing conductivity modulation in this way, it is possible to lower the resistance of the element, but since this element is a switching element, even if the on-resistance is small, the switching time during turn-on and turn-off during switching can be reduced. It is not practical if it is too late. The more carriers there are, the longer this switching time will be, and as a result, the loss during switching will also be greater. Therefore, there is a trade-off relationship between the resistance value of the element and the switching time, and the key to the characteristics of the element is how this trade-off can be improved. In practice, this trade-off has been improved by introducing something called a lifetime killer, which significantly reduces the lifetime of the device.

However, in this case, the degree to which conductivity modulation is caused and the degree to which a lifetime killer is introduced depend on the know-how that truly influences the characteristics of the element. The extent to which conductivity modulation is caused depends, of course, on the injection of electron current at the element surface, and the injection of holes into the n- layer 3 also accounts for a large proportion. The n+ layer 2 regulates the injection of holes. The specific resistance of this n+ layer, that is, its impurity concentration and thickness, regulates hole injection, that is, the degree of conductivity modulation. The formation of this n+ layer 2 is described in US Pat.
This method is known from Japanese Patent No. 117673. Japanese Unexamined Patent Publication No. 1986-11
Publication No. 7673 discloses that by forming an n+ layer, the ratio of the electron current to the hole current in the drain current when on is increased, thereby increasing the current decrease when the gate voltage becomes zero and the electron current is cut off. However, it is stated that the turn-off time has been shortened to 1/2 of that of the conventional method, and that the effect can only be obtained by increasing the amount of impurities in the buffer layer 2 to 3.times.10@14 cm@-3 or more.

[0005]

The key point when turning off an IGBT is how quickly the current can be turned off. In the on state, conductivity modulation occurs inside the element and the n-layer is filled with carriers. In this state, when the gate is cut off, the path of the electrons that were being supplied through the channel is cut off. However, since the load of the IGBT is usually a motor or the like that includes inductance, the IGBT tries to maintain the current even after the gate is shut off. An attempt is made to continue supplying this current while expanding the depletion layer inside the element. This can be expressed by the following formula.

I=α×C×dV/dt [α: constant, C: depletion layer capacitance]

FIG. 2 shows the movement of carriers inside the IGBT at turn-off. n- at turn-off
As the depletion layer 31 spreads within the layer 3, the holes 11 fall into the depletion layer 31, and the fallen holes 11 are accelerated at once by the electric field in the depletion layer 31 and escape toward the source side. The electrons 12 are pushed out by the expansion of the depletion layer 31 and move to the p+ layer 1 side (drain side)
is being pushed out. By introducing a lifetime killer, carrier transportation efficiency is poor and carrier lifetime is shortened. For this reason, it is necessary to widen the depletion layer to continue to maintain the current. As the depletion layer expands, the remaining width of the n- layer decreases, improving the current amplification factor of the PNP transistor configured inside the IGBT. This promotes the re-injection of holes during turn-off, prolonging the turn-off time.

Furthermore, there is a problem in that the turn-off characteristics, which have been improved by introducing a lifetime killer, deteriorate as the temperature increases. This is due to the following reason. When introducing a lifetime killer, the injection efficiency from the drain side is set high. This is because a decrease in transport efficiency due to the disappearance of carriers due to recombination due to an internal lifetime killer is anticipated. In this case, as the temperature increases, the forward energy barrier of the pn junction on the drain side decreases and the injection increases. Additionally, lifetime killers lose their effectiveness as the temperature increases. The reason for this, as has already been made clear in many papers, is that the valence electrons at the recombination center are thermally excited, and as a result, it becomes difficult for carriers to recombine through this recombination center, resulting in a lifetime killer. This is because it would lose its effectiveness.

[0009] Depending on the type of lifetime killer, the recombination energy level formed inside the silicon differs, so the degree of effect of the lifetime killer on temperature also changes. However, the effect of the lifetime killer will continue to disappear as the temperature increases. Overall, it is clear that increasing injection efficiency and using a lifetime killer are unfavorable in response to temperature rise, but while recognizing this, it is important to Motoko had no choice but to create it using a time killer.

An object of the present invention is to solve the above-mentioned problems, prevent the adverse effects of lifetime killer, further shorten the turn-off time while suppressing the increase in on-voltage, and as a result, provide a turn-off system that can reduce the total loss. The object of the present invention is to provide an IGBT that can obtain a trade-off relationship between time and on-voltage.

[0011]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a structure in which a first conductivity type layer is formed between a first layer having a low impurity concentration of a first conductivity type and a second layer having a second conductivity type. A buffer layer with a high impurity concentration is interposed, a well layer of the second conductivity type is selectively formed in the surface layer of the first layer opposite to the buffer layer, and a well layer of the second conductivity type is selectively formed in the surface layer of the well layer. It has a semiconductor body in which a source layer of a first conductivity type with a high impurity concentration is formed, and a well layer sandwiched between the source layer and the first layer of the semiconductor body is used as a channel region. In an IGBT in which a gate electrode is provided on the surface of the buffer layer through an insulating film, the source electrode commonly contacts the surfaces of the source layer and the well layer, and the drain electrode contacts the second layer, the impurity concentration of the buffer layer is 1. ×1017cm-3 or more, thickness 15μ
m or less. It is also effective to diffuse heavy metal elements into the semiconductor element of such an IGBT or to irradiate it with charged particles. It is also effective that the buffer layer has an impurity concentration of 0.8 to 1.2×10 18 cm −3 and a thickness of 8 to 12 μm so that heavy metal elements are not diffused into the semiconductor body.

0012

[Operation] Here, the amount of impurities in the n+ buffer layer 10 is set to 5
The operation as an IGBT will be considered when the thickness is 1017 cm-3 or more and the thickness is 15 μm or less.

FIG. 3 shows the carrier concentration in the device on state, that is, conductivity modulation, in the cross-sectional direction of the n- layer 3 in FIG. On the horizontal axis, the left side is the source side and the right side is the drain side, where A is the conventional n+ buffer layer and B is the n+ buffer layer.
+ The impurity concentration and thickness of the buffer layer 2 are set to values based on the present invention. The reason why the carrier concentration is high on the source side and the drain side in FIG. 3 is that electrons and holes are injected, respectively. Further, it is assumed that A and B have approximately the same on-voltage. The specific resistance of buffer layer 2 is high (
In conventional devices, carriers are often injected from the drain and source sides, but carriers disappear in the center due to recombination due to the lifetime killer, so as shown in A in Figure 3, carriers are injected in the center. Significant decrease in carrier concentration. On the other hand, in the device of the present invention shown in B, the specific resistance of the n+ buffer layer 2 is lowered (the impurity concentration is increased to a predetermined value), and hole injection is suppressed, so that the on-state voltage is lower than in case A. In order to maintain the same value, it is necessary to suppress the effect of the lifetime killer and reduce the difference in carrier concentration between the inside and outside. Let us consider how IGBTs with different carrier distributions turn off even with the same on-voltage.

In FIG. 4, the horizontal axis represents time (t), and the vertical axis represents the current (i) and voltage (V) when the IGBT is turned off.
The waveforms of each are shown. A and B in FIG. 4 correspond to cases A and B in FIG. 3, respectively. The difference between A and B is considered from the rise of the voltage after the gate is turned off. In the case of A, as described above, it is necessary to widen the depletion layer to continue to maintain the current, so the voltage applied to the element rises quickly as shown in A (V) in FIG. On the other hand, in the case of B, the effect of the lifetime killer is suppressed and carrier transport efficiency is good, so a sufficient current can be maintained without expanding the depletion layer so much. Therefore, the voltage rises as shown in B (V) in FIG. 4. In both cases, the depletion layer is n
+ When it reaches the buffer layer 2, the voltage is suddenly raised to try to maintain the current, but in normal external circuits the voltage is clamped at a certain value, so the currents are A(i) and B( It rapidly attenuates as shown by the curve i). Switching losses up to this point can be estimated as the product of voltage and current. As for this switching loss, B is clearly small as shown in FIG.

Next, the subsequent turn-off current waveform will be considered as follows. After the depletion layer reaches n+ layer 2,
Since the voltage is clamped at a certain value, the depletion layer cannot be further expanded to maintain the current, and the current rapidly decreases as described above. The behavior until the depletion layer reaches the n+ layer also differs between case A and case B as follows. As described above, as the depletion layer expands through the n- layer, the base layer of the main internal PNP transistor of the IGBT gradually narrows. As a result, the current amplification factor (hFE) of this transistor increases as the base becomes thinner. However, carrier transport efficiency between A and B is significantly different. There are also differences depending on the position in the thickness direction. In the case of A, since the transport efficiency is originally poor, the hFE increases rapidly as the base layer becomes thinner. On the other hand, in case B, the transport efficiency does not change much depending on the position in the thickness direction, so even if the base layer becomes thinner, its hFE does not change much. This means that because fewer electrons are pushed out to the drain side than in case A due to the expansion of the depletion layer, compared to case A, there are also fewer holes to be re-injected accordingly. Therefore, the manner in which the current decreases during turn-off differs as shown in A and B in FIG. 4. That is, since the tail current flowing due to an increase in hFE as in A is small in B, the turn-off time of the element of the present invention is shorter. Furthermore, case B is superior because even if the injection efficiency is low, the action of the lifetime killer is suppressed.
There is little difference between the turn-off characteristics at high temperatures and the turn-off characteristics at room temperature. And the thickness of the buffer layer is 15
Make it less than μm to prevent an increase in on-voltage.

Furthermore, the heavy metal element diffused into the semiconductor element with increased impurity concentration in the buffer layer according to the present invention is
The high impurity concentration is selectively localized near the buffer layer, increasing the turn-off speed without increasing the on-voltage, which improves the trade-off between on-voltage and switching time. .

The above-mentioned effect is obtained when the conductivity type is reversed.
The same applies to channel IGBTs.

[0018]

[Example] The n+ buffer layer 2 of an IGBT having the structure shown in FIG. 1 was created with the changes shown in Table 1, and the on-voltage and turn-off time were further changed by changing the diffusion temperature of gold as a lifetime killer for each. We investigated the trade-off relationship.

[0019]

[Table 1]

FIG. 5 is a trade-off curve obtained by varying the gold diffusion temperature in the range of 840 to 880°C. The diffusion temperature is low on the left side of the diagram, and the diffusion temperature increases as it moves to the right. The trade-off relationship between sample 23 and sample 24 is almost the same as that of the conventional element. The impurity concentration of the n+ buffer layer is 1
It can be seen that the trade-off is significantly improved by setting the thickness to 1017 cm-3 or more and 15 μm or less.

Regarding the thickness of the n+ buffer layer, since the resistivity is set to a sufficiently low value, injection of holes is extremely limited. For this reason, if it is too thick, the on-state voltage will be increased, making the trade-off worse. Judging from Figure 5, 15
It is preferably less than μm. However, if it is made too thin,
The other role of the conventional n+ buffer layer, which is a stopper for withstanding voltage, is no longer fulfilled. Therefore, it has its own appropriate value.

FIG. 6 shows the concentration of gold localized in the cross-sectional direction of the IGBT of sample 22, confirmed by spreading resistance.
By making the + buffer layer 2 low in resistance, gold accumulates in this portion C and oozes out from there to the n- layer 3. In this way, the lifetime killer is not uniformly present in the n- layer 3, but can be localized at an ideal position as shown by D in the figure, so a significant trade-off improvement can be achieved.

Next, the amount of impurities in the buffer layer 2 is set to 5×10
IGB made with a size of 17cm-3 and a thickness of 10μm
Gold diffusion was applied to T. The temperature of gold diffusion is set to 840-8
The temperature was changed to 80°C, and electron beam irradiation was applied to confirm the trade-off. FIG. 7 shows a comparison of the trade-off of the conventional IGBT and the trade-off of the present invention. In the figure, a line 71 indicates a conventional product, a line 72 indicates a sample subjected to only gold diffusion, that is, a sample similar to 22, and a line 73 indicates a sample subjected to both gold diffusion and electron beam irradiation. As shown in Fig. 6, the IGBT in which the lifetime killer exists at the ideal position D near the n+ layer 2 is further irradiated with charged particles to compensate for the deficiency, and the thickness of the n- layer 3 is increased. By uniformly generating the lifetime killer in the direction, the trade-off can be further improved.

Even when the conductivity types of each layer are opposite to those shown in FIG. 1, there is a p+ layer between the p- layer and the n+ layer on the drain electrode side with an impurity amount of 1.5 x 1018 cm-3 or more and a thickness of 15 μm or less. By forming layers, the same effects as in the above embodiments can be obtained.

As another embodiment of the invention, I
GBT n+ buffer layer 2 with impurity amount of 1×1018
cm-3 with a thickness of 10 μm and without gold diffusion, the trade-off was obtained by changing the specific resistance and thickness of the buffer layer 2, and the amount of lifetime killer introduced was changed. Figure 8 shows the results of a comparison with the trade-off of the conventional product. Line 8 in the figure
1 is the conventional product, and line 82 is the IGBT of the embodiment.

The aim of this embodiment is first to reduce the resistance of the buffer layer 2 as much as possible (increase the impurity concentration) to lower the injection efficiency of holes from the drain side. However, if the resistance is reduced to an extremely low level, no injection will occur at all, and as a result, the device will not turn on. Also, although it turns on, the on-voltage is high. Therefore, the impurity concentration of the buffer layer is 0.8 to 1.
2×10 18 cm −3 , and in reality, it is better to limit not only the specific resistance but also the thickness to 8 to 12 μm. If it is thicker than this, the implantation will be restricted and the on-state voltage will become high. Furthermore, the present invention attempts to limit the injection of holes only by the specific resistance and thickness of the n+ buffer layer so that the on-voltage is comparable to that of the conventional one. Therefore, there is no need to use a lifetime killer. In other words, by lowering the injection efficiency and not using a lifetime killer, the on-voltage is maintained by increasing the transport efficiency. Since this IGBT lowers the injection efficiency and does not use a lifetime killer, the electrical characteristics hardly change even at high temperatures compared to at normal temperatures.

[0027]

[Effects of the Invention] According to the present invention, the impurity concentration of the buffer layer is made to be 1×10 17 cm -3 or more to lower the resistance, and the thickness is made to be 15 μm or less to suppress the injection of carriers into the high resistance layer. By increasing the turn-off speed by almost increasing the on-voltage, the trade-off relationship between the switching time and the on-voltage can be significantly improved. Furthermore, when the lifetime killer is diffused, the lifetime killer is trapped in the buffer layer with high impurity concentration, so the lifetime killer can be localized at an ideal position in the high resistance layer, and the lifetime It is possible to effectively achieve both the effects of diffusion of the killer and generation of the lifetime killer by irradiation with charged particles. On the other hand, since the switching time can be shortened without using a lifetime killer, IG has the great advantage that its electrical characteristics hardly change even at high temperatures compared to at room temperature.
BT is obtained. This is a great advantage including reliability as an element. In addition, from a process perspective, the process does not use heavy metals that can be a source of contamination, and there are no steps involved in life-time killers, leading to total cost reductions and an extremely large effect.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the structure of an IGBT in which the present invention is implemented.

[Figure 2] Cross-sectional view showing the movement of the carrier during turn-off of the IGBT

[Figure 3] Carrier concentration distribution diagram in the n- layer in the conductivity modulation state of IGBT

[Figure 4] Current and voltage waveform diagram at IGBT turn-off

FIG. 5 is a trade-off relationship diagram between on-voltage and turn-off time of IGBTs including embodiments of the present invention.

[Figure 6] Vertical gold concentration distribution diagram of IGBT with gold diffusion

FIG. 7 is a trade-off relationship diagram between on-voltage and turn-off time of IGBTs of another embodiment of the present invention and a comparative example.

[Figure 8]
Trade-off relationship diagram between on-voltage and turn-off time of still another embodiment of the present invention and conventional IGBT

[Explanation of symbols]

1 p+ layer 2 n+ buffer layer 3 n- layer 4 P well layer 5 n+ source layer 6 Gate oxide film 7 Gate electrode 8 Source electrode 9 Drain electrode 41 Channel area

Claims (4)

[Claims] Claim 1: A buffer layer of a first conductivity type with a high impurity concentration is interposed between a first layer of a first conductivity type with a low impurity concentration and a second layer of a second conductivity type, and the buffer layer of the first conductivity type has a high impurity concentration. A semiconductor in which a well layer of a second conductivity type is selectively formed in a surface layer opposite to the surface layer, and a source layer of a first conductivity type with a high impurity concentration is selectively formed in the surface layer of the well layer. The well layer sandwiched between the source layer and the first layer of the semiconductor element is used as a channel region, and a gate electrode is provided on the surface of the channel region via an insulating film. The buffer layer has an impurity concentration of 1 x 1017 cm-3 or more and a thickness of 15 μm or less, in which the source electrode is in common contact with the surface of the well layer and the drain electrode is in contact with the second layer. conductivity modulation type MOSFET. 2. The MOSFET according to claim 1, which is a conductivity-modulated MOS in which a heavy metal element is diffused in a semiconductor element.
FET. 3. The MOSFET according to claim 2, wherein the conductivity-modulated MOSFET is further irradiated with charged particles on the semiconductor element.
OSFET. 4. The MOSFET according to claim 1, wherein the buffer layer has an impurity concentration of 0.8 to 1.2×10 18 cm.
-3, the thickness is 8 to 12 μm, and a conductivity modulation type MOSFET in which heavy metal elements are not diffused into the semiconductor element.