GB2247778A - Bipolar transistors - Google Patents
Bipolar transistors Download PDFInfo
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- GB2247778A GB2247778A GB9027182A GB9027182A GB2247778A GB 2247778 A GB2247778 A GB 2247778A GB 9027182 A GB9027182 A GB 9027182A GB 9027182 A GB9027182 A GB 9027182A GB 2247778 A GB2247778 A GB 2247778A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 62
- 229920005591 polysilicon Polymers 0.000 claims abstract description 62
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 55
- 150000004767 nitrides Chemical class 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 17
- 238000001259 photo etching Methods 0.000 claims description 12
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 7
- 238000003892 spreading Methods 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 claims description 2
- 238000005334 plasma enhanced chemical vapour deposition Methods 0.000 claims 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims 2
- 230000008021 deposition Effects 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 239000000463 material Substances 0.000 description 11
- 150000002500 ions Chemical class 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- -1 boron ions Chemical class 0.000 description 4
- ZFBGKBGUMMBBMY-UHFFFAOYSA-N 1,1,2-trichlorobuta-1,3-diene Chemical compound ClC(Cl)=C(Cl)C=C ZFBGKBGUMMBBMY-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229960002050 hydrofluoric acid Drugs 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42304—Base electrodes for bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
- H01L29/7325—Vertical transistors having an emitter-base junction leaving at a main surface and a base-collector junction leaving at a peripheral surface of the body, e.g. mesa planar transistor
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
The transistor is constituted such that a polysilicon layer as a base electrode (19) is formed at least partly within an epitaxial layer (3). A thick oxide layer (17) is formed under the polysilicon base electrode so that the base region (24, 25) and a collector region (13) are separated, and an impurity is laterally diffused from the polysilicon base electrode to the extrinsic base region (25). The junction capacitance and the transit time between the extrinsic base region (25) and the collector region (13) are reduced, thereby improving the characteristics of the transistor. Further, reach-through due to the highly doped extrinsic base region is eliminated so that a high breakdown voltage of the transistor is obtained, and consequently, with no reduction in the breakdown voltage, the thickness of the epitaxial layer can be reduced, thereby improving the speed characteristics of the transistor. <IMAGE>
Description
BIPOLAR TRANSISTOR
The present invention relates to a bipolar transistor and a process for formation thereof, in which a base electrode in the form of a polysilicon layer is formed within an epitaxial layer, and a thick oxide layer is formed under the polysilicon base electrode, so that the collector region and the base region are separated from each other, and that the extrinsic base region is laterally diffused from the polysilicon base electrode.
Figure 1 is a sectional view of a conventional high speed bipolar transistor in which a buried layer 52 and an epitaxial layer 53 are formed on a silicon substrate 51, an extrinsic base region 55 and a collector region 56 are separated from each other by interposing a field oxide layer 57, and a channel stop region 58 is formed under the field oxide layer 57. Reference code 54 indicates an emitter region. Respective polysilicon electrodes 59 to 61 are formed on the substrate, and an insulating layer 65 is formed thereupon, while metal electrodes 62 to 64 are electrically connected to the polysilicon electrodes 59 to 61.
Generally, the cut-off frequency (fT) of a selfaligned NPN bipolar transistor is defined by the following formula:
1 kT f =~ [ TF + Rc - CJBC + ~ (CJEB + CJBC)-1 ]
2r ZIC where TF = TE + TEBD + TB + TCBD, Rc represents the
kT collector resistance, ------ a constant, IC the collector
q current, CJEB the junction capacitance between the emitter and the base, CJBC the junction capacitance between the base and the collector, TE the emitter transit time,rEBD the emitter base depletion layer delay,
TB the base transit time, and rCBD the base collector depletion delay.
In the above formula, generally, the critical factors which influence the characteristics of the high frequency performances of a self aligned NPN transistor are the junction capacitance CJBC between the base region and the collector region, and the collector-base depletion layer delay TCBD Generally, to reduce the base internal resistance rbb' in a bipolar transistor, the extrinsic base region has to be doped in high concentration. If the extrinsic base region is doped in high concentration, the junction capacitance between the base region and the collector region is increased, thereby influencing the high frequency performance of the transistor.
Furthermore, to improve the high frequency characteristics the series resistance of the collector has to be decreased by reducing the thickness of the epitaxial layer. If the thickness of the epitaxiai layer is reduced too much, a reach-through phenomenon occurs such that a depletion layer extends from the high concentration extrinsic base region to the buried layer, due to the reverse bias voltage. This results in the breakdown voltage (BVCEO) of the transistor being lowered.
An object of the present invention is to overcome at least some of the above-described disadvantages of conventional techniques.
A further object of the present invention is to provide a high speed bipolar transistor and a fabrication process thereof, in which the reach through phenomenon is eliminated, and the junction capacitance and the basecollector depletion delay are reduced, thereby improving the high frequency characteristics of the transistor.
In embodiments of the present invention, the reach-through phenomenon due to the high concentration extrinsic base region is removed by forming a base electrode in the form of a polysilicon layer within the epitaxial layer, and by forming a thick oxide layer under the polysilicon base electrode. Accordingly, it becomes possible to reduce the thickness of the epitaxial layer in a state with the breakdown voltage of the transistor kept in the same level, and therefore, the series resistance of the collector is reduced, with the result that the junction capacitance and the transit time between the extrinsic base region and the collector region are reduced.
According to the present invention there is provided a high speed bipolar transistor in which a buried layer and an epitaxial layer are formed on a silicon substrate; a channel stop region is formed under a field oxide layer which is for separating different components; and respective polysilicon electrodes are electrically connected to metal electrodes through contact devices, thereby forming a high speed bipolar transistor, and the transistor according to the present invention is further constituted such that: a polysilicon base electrode is formed within an epitaxial layer; a thick oxide layer is formed under the polysilicon base electrode so that the base region and the collector region are separated from each other; another oxide layer is formed upon the base electrode in the form of a polysilicon layer; a collector electrode and an emitter electrode made of polysilicon are contacted to a collector region and an emitter region in the longitudinal direction; and the polysilicon base electrode is contacted with the extrinsic base region in the lateral direction.
According to the present invention there is further provided a fabrication process for a high speed bipolar transistor comprising: the step of forming an buried layer and an N buried layer on a silicon substrate by applying an ordinary buried layer forming method; the step of exposing the portion for forming a field oxide layer by applying a photo-etching method after forming an oxide layer and a nitride layer, and forming a field oxide layer and a channel stop region by carrying out a thermal oxidizing process after carrying out an ion-implantation; the step of spreading an oxide layer, forming an opening by carrying out a photo-etching after spreading a photo-sensitive material, ionimplanting impurities into the opening using the photosensitive material as a mask, and forming a collector region by carrying out a heat treatment; the step of forming a thick oxide layer within the epitaxial layer; the step of forming a base electrode having a smooth and flat face by carrying out a polishing after spreading a polysilicon layer; the step of forming a base region; the step of forming an emitter region by ion-implanting an N type impurity, and by diffusing the ion-implanted impurity based on a thermal diffusion method; the step of forming an emitter electrode and a collector electrode by etching the polysilicon layer based on a photo-etching method; the step of depositing an oxide layer on the whole surface of the substrate by applying a plasma activated chemical vapour deposition method, and carrying out a photo-etching process in order to expose the portions where a collector electrode, a base electrode and an emitter electrode are to be formed; and the step of carrying out metallization to form an emitter electrode, a base electrode and a collector electrode.
The step of forming the thick oxide layer preferably comprises: the sub-step of forming a nitride layer on the oxide layer by applying a low pressure deposition method, and forming an oxide layer thereupon by applying a plasma activated chemical vapour deposition method; the sub-step of forming a pattern by sequentially etching the oxide layer, the nitride layer and the oxide layer; the sub-step of carrying out an a anisotropic etching on the portion of the N- epitaxial layer where a base electrode is to be formed; the sub-step of depositing a nitride layer on the whole surface of the substrate by applying a low pressure chemical vapour deposition method; the sub-step of forming a side wall nitride layer by anisotropically etching the nitride layer; and the sub-step of forming a thick oxide layer within the base region by applying the usual thermal oxidation.
The step of forming the base region preferably comprises: the sub-step of ion-implanting an impurity into the whole surface of the substrate after forming a polysilicon base electrode; the sub-step of removing the oxide layer by applying a wet etching process; the substep of growing an oxide layer on the polysilicon electrode; the sub-step of removing the nitride layer and the pad oxide layer; the sub-step of ion-implanting a P type impurity after growing a thin oxide layer again; the sub-step of forming a spacer on the side wall by carrying out an anisotropic etching after depositing an oxide layer; the sub-step of depositing a polysilicon layer on the whole surface of the substrate; and the sub-step of forming an intrinsic base region and an extrinsic base region by carrying out diffusions after ion-implanting a
P type impurity into the polysilicon layer.
Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings in which:
Figure 1 is a sectional view of a conventional high speed bipolar transistor;
Figure 2 is a sectional view of a high speed bipolar transistor according to the present invention; and
Figure 3 is a sectional view showing the process of formation of a high speed bipolar transistor according to the present invention.
Figure 2 is a sectional view of a high speed bipolar transistor according to the present invention.
As shown in this drawing, a buried layer 2 and an epitaxial layer 3 are formed on a silicon substrate 1, and a polysilicon base electrode is formed within the epitaxial layer 3, unlike the case of the conventional device. Further, a thick oxide layer 17 is formed under the base electrode 19 so that the base region 24, 25 and a collector region 13 are separated from each other, while a channel stop region 9 is formed under a field oxide layer 8 which serves to separate the different parts.
Meanwhile, an oxide layer 22 is formed upon the polysilicon layer 19 serving as a base electrode, and thereupon, a collector electrode 28 and an emitter electrode 27 made of polysilicon are formed in contact with an emitter region 26 and the collector region 13.
Thereupon, an oxide layer 29 serving as an insulating layer is formed, and thereupon, the respective polysilicon base electrode 19, polysilicon emitter electrode 27 and polysilicon collector electrode 28 are electrically connected to metal electrodes 30 to 32 through contact devices.
Figure 3 is a sectional view showing the formation process for the high speed bipolar transistor according to the present invention, and the formation process will be described below referring to Figure 3.
Figure 3A illustrates the step of forming a buried layer and an epitaxial layer on the silicon substrate 1 by applying a conventional method, as is well known to those skilled in the art.
Upon a P type silicon substrate 1 having a specific resistivity of 10 to 30 fl.m and a crystal face of < 100 > , there is formed an N+ buried layer 2 by applying the usual buried layer forming process, and then, an N epitaxial layer 3 having a specific resistivity of 0.3 to 0.5 n .m is formed in the thickness of 0.8 to 1.2 #m.
Then, an oxide layer 4 is formed, having a thickness of 400 A to 800 A, on the epitaxial layer 3 by applying a usual thermal oxidation method, and thereupon, a nitride layer 5 is deposited having a thickness of 1000
A to 1500 A, by applying a low pressure chemical vapour deposition method (LPCVD).
Figure 3B illustrates the step of opening the region other than the active region, ie, the field region by applying a usual photo-etching process. After spreading a photo-sensitive material on the nitride layer 5, the N epitaxial layer 3 is exposed by sequentially photo-etching the nitride layer 5 and the oxide layer 4 which are formed on the field region, and the exposed epitaxial layer 3 is etched by about 0.4 to 0.6 ssm, with the photo-sensitive material being removed thereafter.
Figure 3C illustrates the step of forming a channel stop region. After spreading a photo-sensitive material 6 on the whole surface of the substrate, the portion of the N type epitaxial layer 3 where a channel stop region is to be formed is exposed by applying a photo-etching method, and an ion-implantation region 7 is formed by ion-implanting boron (B) ions in the intensity of 2 to 20 x 1012 ions/cm2 with an energy of 15 to 30
KeV.
As shown in Figure 3D, after removing the photosensitive material 6, a field oxide layer 8 is grown in the thickness of 9000 A to 11000 A by applying a usual thermal oxidation method, and then the nitride layer 5 and the oxide layer 4 are successively removed. Under this condition, the ion-implanted boron ions, which are ion-implanted during the thermal oxidation process for forming the oxide layer 8, are diffused to form a channel stop region 9.
Figure 3E illustrates the step of forming a collector region. First an oxide layer 10 is grown in the thickness of about 500 A to 800 A on the whole surface of the substrate, and thereupon, a photo-sensitive material 11 is spread. Then the portion where the collector region is to be formed is exposed by etching the spread photo-sensitive material 11, and then, phosphorus (P) ions are ion-implanted through the opening 12 in the intensity of 1 to 3 x 1015 ions/cm2 and with an energy of 80 to 100 Kev. Thereafter an ordinary heat treating process is carried out, thereby completing the formation of a collector region 13.
Figures 3F to 3J illustrate steps of forming a polysilicon base electrode by etching the epitaxial layer 3, and forming a thick oxide layer under the polysilicon base electrode. First, referring to Figure 3F, a nitride layer 14 is formed on the oxide layer 10 by applying a low pressure chemical vapour deposition method after removing the photo-sensitive material 11, and thereupon, an oxide layer 15 is formed in the thickness of 5000 A to 7000 A by applying a conventional chemical vapour deposition method (CVD).
Then, a pattern is formed by applying an ordinary photo-etching process in order to separate the emitter and base regions from each other, and specifically, the pattern is formed in such a manner that, after spreading a photo-sensitive material on the oxide layer 15, the oxide layer 15, the nitride layer 14 and the oxide layer 10 are successively etched so as for the pattern to be formed, the photo-sensitive material being removed thereafter.
Referring to Figure 3G, the portion of the Nepitaxial layer 3 where a polysilicon base electrode is to be formed is anisotropically etched by about 0.6 to 0.8 pm using the oxide layer 15, the nitride layer 14 and the oxide layer 10 as the masks. As shown in Figure 3H, a nitride layer 16 is deposited by about 1000 A to 1500 A on the whole surface of the substrate by applying a low pressure chemical vapour deposition method, and then, the nitride layer 16 is anisotropically etched so as for a nitride layer 16' to remain only on the side wall as shown in Figure 31.
Figure 3J illustrates the step of forming an oxide layer within the epitaxial layer, and as shown in this drawing, a thick oxide layer 17 is grown in the thickness of 7000 A to 9000 A under the extrinsic base region by applying a thermal oxidation method using the nitride layer 16' of the side wall as the mask. Here, the growing of the oxide layer 17 is inhibited due to the nitride layer 16', so that the oxide layer 17 should be formed only on the epitaxial layer 3.
Figures 3K and 3L illustrate the step of forming a polysilicon base electrode. First, as shown in Figure 3K, the side wall nitride layer 16' is removed using phosphoric acid, and then, a polysilicon layer 18 is deposited in the thickness of 10000 A to 15000 A by applying a low pressure chemical vapour deposition method. Then, as shown in Figure 3L, the polysilicon layer 18 formed through a process described above is polished, in such a manner that the polysilicon layer 18 which is formed on the whole surface of the substrate is polished by applying an ordinary polishing process, thereby forming a smooth polysilicon base electrode 19.
Then an ion-implanting process is carried out in order to form a base region, in such a manner that boron ions are ion-implanted into the whole surface of the substrate in an intensity of 3 to 6 x 1015 ions/cm2 and with an energy of 30 to 40 KeV.
Referring to Figure 3M, the oxide layer 15 on the nitride layer 14 is removed by applying a wet etching method, and then, an oxide layer 20 is formed in the thickness of 3000 A to 5000 A by applying an ordinary thermal oxidation method on the polysilicon base electrode 19 having a flat face. Under this condition, the oxide layer 20 is formed only on the upper face and the side wall of the flat polysilicon base electrode 19.
Figures 3N and 30 illustrate the step of forming a side wall oxide layer on the side wall of the flat polysilicon base electrode 19. First, as shown in Figure 3N, the nitride layer 14 is removed by means of phosphoric acid solution and using the oxide layer 20 as the etching mask, and then, the pad oxide layer which is formed under the nitride layer 14 is also removed using an ordinary fluoric acid solution. Then, as shown in
Figure 30, a thermal oxide layer 21 is grown in the thickness of 300 A to 500 A at a temperature of about 9000C, and then, boron ions are ion-implanted into the whole surface of the substrate in an intensity of 1 to 10 x 1022 ions/cm2 and with an energy of 25 to 30 KeV.
Referring to Figure 3P, after carrying out the ionimplantation, an oxide layer is deposited on the whole surface of the substrate by applying a conventional chemical vapour deposition method (CVD), and this oxide layer is anisotropically etched, thereby forming a side wall oxide layer on the side wall (22) of the flat polysilicon base electrode 19.
Figures 3Q and 3R illustrate the ion-implanting step for forming a base region and an emitter region.
First, as shown in Figure 3Q, a polysilicon layer 23 is deposited on the whole surface of the substrate in the thickness of 2000 A to 4000 A by applying an ordinary low pressure chemical vapour deposition method (LPCVD), and then, boron ions are ion-implanted in the intensity of 1 to 5 x 1014 ions/cm2 and with an energy of 30 to 40 KeV.
After carrying out the ion-implantation, a diffusion is carried out at a temperature of 9500C, so that an intrinsic base region 24 and extrinsic base region 25 should be formed on the silicon substrate.
Referring to Figure 3R, arsenic (As) ions are ion-implanted into the polysilicon layer 23 in an intensity of 5 to 10 x 1015 ions/cm2 and with an energy of 80 to 120 KeV, and then, a diffusion is carried out by applying an ordinary thermal diffusion method at a temperature of about 10000C. In this way, the emitter region 26, the intrinsic base region 24 and the extrinsic base region 25 of the bipolar transistor are formed.
Referring to Figure 3S, the polysilicon layer 23 is etched by applying an etching process, and in this way, a polysilicon emitter electrode 27 and a polysilicon collector electrode 28 are formed. Then, an oxide layer 29 is deposited on the whole surface of the substrate in the thickness of 3000 A to 5000 A by applying a plasma activated chemical vapour deposition method (PACVD), and then, an etching process is carried out in such a manner that the portions of the oxide layers on which a collector electrode, a base electrode and an emitter electrode are to be formed should be exposed by the etching. Then, an ordinary metallization process is carried out to form an emitter electrode 30, a base electrode 31 and a collector electrode 32.Finally, an alloying process is carried out at a temperature of 4000C to 4500C for 30 to 60 minutes, thereby completing the whole process of forming the high speed bipolar transistor according to the present invention.
According to the present invention as described above, a base electrode in the form of a polysilicon layer is formed, an extrinsic base region is formed by diffusing the impurity from the base electrode, and a thick oxide layer is formed under the base electrode so that the base region and the collector region are separated. This brings the result that the junction capacity and the transit time between the extrinsic base region and the collector region are reduced, thereby improving the micro-wave characteristics of the transistor. Further, the reach-through phenomenon caused by the high concentration base region can be eliminated, so that a high breakdown voltage level should be obtained. Consequently, with the same breakdown voltage characteristics of the transistor, the thickness of the epitaxial layer can be further reduced, and therefore, the high speed characteristics of the transistor can be improved.
Claims (9)
1. A bipolar transistor comprising: a buried layer and an epitaxial layer formed on a silicon substrate; a channel stop region formed under a field oxide layer for device isolation; and polysilicon electrodes electrically connected to metal electrodes, wherein said polysilicon base electrode is formed within said epitaxial layer; a relatively thick oxide layer is formed under the base electrode so that said base region and a collector region are separated from each other; an oxide layer is formed under said polysilicon layer serving as a base electrode; a collector electrode and an emitter electrode are formed thereupon in contact with an emitter region and said collector region in the longitudinal direction; and said polysilicon base electrode is contacted with said extrinsic base region in the lateral direction.
2. A fabrication process of a bipolar transistor, comprising: forming an N+ buried layer on a silicon substrate by applying a buried layer process, and growing an N- epitaxial layer; forming an oxide layer and a nitride layer, carrying out a photo-etching to expose the portion where a field oxide layer is to be formed, carrying out an ion-implantation, and carrying out a thermal oxidation to form a field oxide layer and a channel stop region; growing an oxide layer, spreading a photo-resist, forming an opening by photo-etching, ionimplanting an impurity into said opening using said photo-resist as the mask, and diffusing to form a collector region; growing a relatively thick oxide layer within said epitaxial layer; carrying out a polishing process after deposition of a polysilicon layer to form a planarized polysilicon base electrode; forming a base region; forming an emitter layer by a diffusion process after ion-implanting an N type impurity into a polysilicon layer; forming a polysilicon emitter electrode and a polysilicon collector electrode by photoetching said polysilicon layer; depositing an oxide layer on the whole surface of said substrate by a PECVD (Plasma
Enhanced Chemical Vapour Deposition), carrying out a photo-etching process to open the area where a collector electrode, a base electrode and an emitter electrode are to be formed; and carrying out a metallization process to form an emitter electrode, a base electrode and a collector electrode.
3. A fabrication process as claimed in Claim 2, wherein the step of forming said thick oxide layer comprises: forming a nitride layer on said oxide layer by a low pressure chemical vapour deposition method (LPCVD); successively etching an oxide layer, a nitride layer and an oxide layer to form a pattern; anisotropically etching the area of said N- epitaxial layer where a polysilicon base electrode is to be formed; depositing a nitride layer on the whole surface of said substrate by a low pressure chemical vapour deposition method; anisotropically etching said nitride layer to form a side wall nitride layer; and forming a relatively thick oxide layer within said epitaxial layer by a local thermal oxidation method.
4. A fabrication process as claimed in Claim 2-or
Claim 3, wherein said side wall nitride layer is used as a mask so that said oxide layer is formed only on said epitaxial layer.
5. A fabrication process as claimed in any of Claims 2 to 4, wherein the step of forming said base region comprises: ion-implanting an impurity into the whole surface of said substrate after forming said polysilicon base electrode; removing said oxide layer by a wet etching method; growing an oxide layer on said polysilicon base electrode; removing said nitride layer and said oxide layer, and then, ion-implanting a P type impurity after growing a thin oxide layer; depositing an oxide layer, and then, carrying out an anisotropic etching to form a side wall spacer; depositing a polysilicon layer on the whole surface of said substrate; ion-implanting an impurity into said polysilicon layer, and then, carrying out a diffusion to form an intrinsic base region and an extrinsic base region.
6. A fabrication process as claimed in Claim 5, wherein said nitride layer is used as a mask so that said oxide layer is formed substantially only on the top and side walls of said polysilicon base electrode.
7. A fabrication process as claimed in Claim 5 or
Claim 6, wherein said oxide layer is used as an etching mask when etching said nitride layer and said pad oxide layer.
8. A bipolar transistor substantially as hereinbefore described with reference to, and as illustrated by, Figures 2 and 3 of the accompanying drawings.
9. A fabrication process for a bipolar transistor substantially as hereinbefore described with reference to and as illustrated by, Figures 2 and 3 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900014093A KR920007211A (en) | 1990-09-06 | 1990-09-06 | High speed bipolar transistor and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9027182D0 GB9027182D0 (en) | 1991-02-06 |
| GB2247778A true GB2247778A (en) | 1992-03-11 |
Family
ID=19303325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9027182A Withdrawn GB2247778A (en) | 1990-09-06 | 1990-12-14 | Bipolar transistors |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH06342801A (en) |
| KR (1) | KR920007211A (en) |
| FR (1) | FR2666685A1 (en) |
| GB (1) | GB2247778A (en) |
| IT (1) | IT1244329B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3366919B2 (en) * | 1997-06-27 | 2003-01-14 | エヌイーシー化合物デバイス株式会社 | Semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0188291A2 (en) * | 1985-01-17 | 1986-07-23 | Kabushiki Kaisha Toshiba | Bipolar semiconductor device and method of manufacturing the same |
| EP0293641A1 (en) * | 1987-05-21 | 1988-12-07 | Siemens Aktiengesellschaft | Process for the manufacture of a full self-aligned bipolar transistor |
| US4824799A (en) * | 1985-01-17 | 1989-04-25 | Kabushiki Kaisha Toshiba | Method of making a bipolar semiconductor device |
| EP0329401A2 (en) * | 1988-02-16 | 1989-08-23 | Sony Corporation | Bipolar transistors and methods of production |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62141768A (en) * | 1985-12-16 | 1987-06-25 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPS62189753A (en) * | 1986-02-17 | 1987-08-19 | Hitachi Ltd | Semiconductor device |
-
1990
- 1990-09-06 KR KR1019900014093A patent/KR920007211A/en not_active Application Discontinuation
- 1990-12-13 IT IT02236890A patent/IT1244329B/en active IP Right Grant
- 1990-12-14 GB GB9027182A patent/GB2247778A/en not_active Withdrawn
- 1990-12-24 FR FR9016242A patent/FR2666685A1/en active Pending
-
1991
- 1991-05-21 JP JP3144102A patent/JPH06342801A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0188291A2 (en) * | 1985-01-17 | 1986-07-23 | Kabushiki Kaisha Toshiba | Bipolar semiconductor device and method of manufacturing the same |
| US4824799A (en) * | 1985-01-17 | 1989-04-25 | Kabushiki Kaisha Toshiba | Method of making a bipolar semiconductor device |
| EP0293641A1 (en) * | 1987-05-21 | 1988-12-07 | Siemens Aktiengesellschaft | Process for the manufacture of a full self-aligned bipolar transistor |
| EP0329401A2 (en) * | 1988-02-16 | 1989-08-23 | Sony Corporation | Bipolar transistors and methods of production |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2666685A1 (en) | 1992-03-13 |
| JPH06342801A (en) | 1994-12-13 |
| IT9022368A0 (en) | 1990-12-13 |
| IT9022368A1 (en) | 1992-03-07 |
| IT1244329B (en) | 1994-07-08 |
| KR920007211A (en) | 1992-04-28 |
| GB9027182D0 (en) | 1991-02-06 |
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