FR2666685A1 - BIPOLAR TRANSFORMER OPERATING AT HIGH SPEED AND METHOD FOR MANUFACTURING SUCH TRANSISTOR. - Google Patents

Abstract

In this transistor comprising a buried layer (2) and an epitaxial layer (3) formed on a silicon substrate (1), a channel stop region (9) located below a field oxide layer (8) and polysilicon electrodes (27, 19, 28) connected to electrodes (30-32), a base electrode (19) is formed in an epitaxial layer (3), an oxide layer (17) is formed under the electrode (19) and separates the base region (25) and a collector region, an oxide layer (21) is formed under the electrode (19), and a collector electrode (28) and an emitter electrode (24) are formed on this layer, in contact with an emitter region (26) and the collector region (13), in the vertical direction, while the electrode (19) is. in contact with the base region (25), in the lateral direction. Application in particular to bipolar transistors exhibiting high frequency performance.

Description

The present invention relates to a bi-transistor

  polar and a method for forming such a transistor and se-

  wherein a base electrode in the form of a polysilicon layer is formed within an epitaxial layer, and a thick oxide layer is formed beneath the polysilicon base electrode of in that the collector region and the base region are separated from one another and the extrinsic base region diffuses laterally from the

-based polysilicon.

  Figure 1, attached to this application, refers to

  shows a sectional view of a conventional bipolar transistor

  A buried layer 52 and an epitaxial layer 53 are formed on a silicon substrate 51;

  an extrinsic base region 55 and a collection region

  56 are separated from each other by the insertion of a field oxide layer 57; and a channel stop region 58 is formed below the field oxide layer 57. The reference numeral 57 denotes an emitter region.

  In addition, respective polysilicon electrodes

  59-61 are formed on the substrate, and an iso-

  lante 65 is formed on these electrodes, while 62-64 metal electrodes are electrically connected.

  with polysilicon electrodes 59-61.

  In general terms, the cut-off frequency (f T) of a self-aligned NPN bipolar transistor is defined by the following formula: 1 k T f T = lTF + Rc CJBC + (CJEB + CJBC) 1 2 N q Ic with TF = TE + TEBD + TB + T Cp D In addition, Rc represents the k collector resistance, a constant, IC the collector current q, CJEB the capacitance of the junction between the emitter and the base, CJBC the capacitance of the junction between the base and the collector, TE the transit time in the transmitter, 'EBD the propagation delay in the emitter-base depletion layer, TB the transit time in the base, and TCBD the delay of spread in the layer

of base-collector depletion.

  Generally, in the above formula

  critical factors influencing the characteristics of

  performance characteristics of a transient

  self-aligned NPN tor, are the CJBC capacitance of the junction between the base region and the collector region, and the TCBD delay occurring in the collector-base depletion layer.

  In general, to reduce the resistance

  base internal rbb 'in a bipolar transistor, it

  to boost the extrinsic base region with a concentration

  If the extrinsic base region is doped with a high concentration, the capacity of the junction

  between the base area and the collector area is ac-

  relatively high, which affects performance

  at high frequencies of the transistor.

  In addition, to improve the high-frequency characteristics, the series resistance must be reduced.

  collector by reducing the thickness of the epilayer

  If the thickness of the epitaxial layer is

  Too little, there is a drilling phenomenon such that a depletion layer extends from the extrinsic base region at high concentration to the layer

  -excellent, given the polarization voltage

  This has the effect of reducing the breakdown voltage

(B Vc EO) of the transistor.

  The present invention aims to eliminate the

  described drawbacks of conventional techniques.

  Therefore, the object of the present invention is to provide a bipolar transistor operating at

  high speed and a method for making such a transistor

  tor, in which the drilling phenomenon is suppressed and the capacity of the junction and the delay in the base-collector depletion layer is reduced, which improves

  the high frequency characteristics of the transis-

  tor. According to the solution for achieving the above-mentioned objective, the drilling phenomenon due to the high concentration extrinsic base region is eliminated by forming a base electrode in the form of a polysilicon layer. at

  inside the epitaxial layer, and by means of

  thick oxide layer below the electrode

  As a result, it becomes pos-

  sible to reduce the thickness of the epitaxial layer in a state such that the breakdown voltage of the transistor is

  maintained at the same level, and therefore the resistance

  collector series is reduced, which has the effect that the junction capacity and the propagation time

  between the extrinsic base region and the region of

are reduced.

  In addition, to achieve the stated objective

  previously, the bipolar transistor operating at high speed, according to the present invention consists of

  in such a way that a buried layer and a layer

  on a silicon substrate, forming a channel stopping region beneath a field oxide layer for separating different components, and electrically connecting respective polysilicon electrodes to electrodes. by means of

  contact, so as to form a bipolar transistor operating

  at high speed, and the transistor according to the present invention is arranged in such a manner that

  forms a polysilicon base electrode in a layer of

  epitaxial; that a thick oxide layer is formed over

  under the polysilicon base electrode so as to separate the base region and the collector region from each other; forming another oxide layer on the base electrode in the form of a polysilicon layer; a collector electrode and a polysilicon emitter electrode are in contact with a collector region and an emitter region, in the

  longitudinal direction; and that the base electrode in po-

  lysilicon is in contact with the extrinsic base region

  sque, in the lateral direction.

  In addition, to achieve the stated objective

  previously, the method of forming the bipolar transistor according to the present invention includes the step of forming a buried layer

  of type N + and a buried layer of type N_ in a sub-

  silicon stratum, by means of the use of a conventional method of forming a buried layer;

  the step of exposing the part used

  for the formation of a field oxide layer, medium-

  the application of a photochemical corrosion process after the formation of an oxide layer and a

  nitride, and to form a field oxide layer and a

  channel stopper by carrying out a thermal oxidation operation after implementation of an ion implantation; the step of spreading an oxide layer,

  to provide an opening through photochromic corrosion

  after spreading a photosensitive material, introducing

  removing impurities by ion implantation in the aperture using the photosensitive material in masking tanit, and forming a collector region by carrying out heat treatment; the step of forming a thick oxide layer inside the epitaxial layer; the step of forming a base electrode

  having a uniform and flat surface by means of a polishing

  wise after spreading a layer of polysilicon; the step of forming a base region; the step of forming an emitter region

  through the introduction of an N-type impurity by

  ionic planting and diffusion of the impurity introduced

  by ion implantation, on the basis of a thermal diffusion process; the step of forming an electrode

  emitter and a collector electrode by means of

  erosion of the polysilicon layer on the basis of a

  yielded photochemical corrosion; the step of depositing an oxide layer on the entire surface of the substrate by performing a chemical vapor deposition process

  with activation by a plasma, and to implement a

  photochemical corrosion to expose the

  a collector electrode, a base electrode and an emitter electrode must be formed; and the step of forming a metallization to form an emitter electrode, a base electrode and

a collector electrode.

  During the fabrication process of the bi-transistor

  fleece operating at high speed, in accordance with the

  invention, the step of forming the layer

thick oxide includes: -

  the partial step of forming a nitride layer on the oxide layer by means of a low pressure deposition process and forming an oxide layer thereon by means of a chemical deposition process;

  vapor phase with activation by a plasma, the step

  forming structure by successive corrosion of the oxide layer, the

  nitride and the oxide layer, the partial step

  both to apply anisotropic corrosion to the portion of the N-type epitaxial layer, when a base electrode is to be formed, the partial step of depositing

  a nitride layer over the entire surface of the sub-

  strat using a chemical phase deposition process

  low pressure, the partial step of

  a sidewall forming nitride layer by means of anisotropic corrosion of the coating layer, and the partial step of forming a thick oxide layer in the base region using oxidation

usual thermal.

  During the fabrication process of the bi-transistor

  fleece operating at high speed, in accordance with the

  In this invention, the step of forming the base region includes: the partial step of introducing by ion implantation an impurity into the entire surface of the substrate after forming a polysilicon base electrode; method of removing the oxide layer by a wet corrosion process, the partial step of growing an oxide layer on the polysilicon base electrode,

  the partial step of eliminating the layer of

  trure and the interlayer oxide layer, the partial step

  consisting in introducing by ion implantation an impulse

  type P after having again grown a

  thin oxide layer, the partial step of forming

  sea a spacer on the side wall by performing anisotropic corrosion after depositing an oxide layer,

  the partial step of depositing a layer of poly-

  silicon on the entire surface of the substrate, and the partial step of forming an intrinsic base region and an extrinsic base region by running

  diffusions after an ion implantation of an impu-

  P-type bond in the polysilicon layer.

  Other features and advantages of the pre-

  invention will emerge from the description given below.

  afterwards, with reference to the accompanying drawings, on

  which: Figure 1, which has already been mentioned, shows a sectional view of the conventional bipolar transistor operating at high speed; Figure 2 shows a sectional view of the bipolar transistor operating at high speed, according to the present invention; and

  S S 3 A to S 3 S, r e p r e -

  s e N t e nt e N e a t th e p rc ed for the manufacture of the bipolar transistor operating at great

  speed, according to the present invention.

  FIG. 2 is a sectional view of the transistor

  bipolar system operating at high speed, in accordance with the

  As shown in this drawing,

  a buried layer 2 and an epitaxial layer 3 are formed.

  On a silicon substrate 1 and a polysilicon base electrode is formed in the epitaxial layer 3, in contrast to the case of the conventional device. Further, a thick oxide layer 17 is formed below the base electrode 19. to separate the base region 24, 25 and a collector region from one another

  13, while a channel stop region 9 is formed

  under a layer of field oxide 8, which serves to separate

the different parts.

  Furthermore, an oxide layer 22 is formed on a polysilicon layer 19 used as an electrode

  base, and on this layer of oxide are formed an elec-

  and a collector electrode 27 and a polysilicon emitter electrode 27, which are in contact with a region

  transmitter 26 and the collector region 13

  seems to be formed an oxide layer 29 used as

  insulation layer and on this layer are formed the elec-

  polysilicon base trode 19, the emitter electrode

  polysilicon 27 and the polysilicon collector electrode

  which are electrically connected to metal electrodes 30-32 via contact devices. S 3 A to S 35 represent in section the manufacturing process of the bipolar transistor.

  operating at high speed, in accordance with this

  tion, and this method of manufacturing is described below.

tion with reference to these figures.

  FIG. 3A illustrates the step of forming a buried layer and an epitaxial layer on the substrate

  in silicon 1, using the usual method.

  On a P-type silicon substrate 1, possessed

  with a specific resistivity equal to 10-30 μm and a crystalline face <100>, a buried layer 2 of N + type is formed using the usual method of forming a buried layer, and then an epitaxial layer 3 is formed.

  N- type, having a specific resistivity equal to 0.3-

  0.5 μm, over a thickness of 0.2-1.2 μm.

  Then, an oxide layer 4 is formed on a

  thickness between 40 and 80 nm on the epitaxial layer

  3 using a conventional thermal oxidation process, and on this layer is deposited a nitride layer 5 to a thickness of between 100 and 150 nm using a chemical phase deposition process

low pressure steam (LPCVD).

  Figure 3B illustrates the step of exposing the region other than the active region, i.e., the field region using a conventional photochemical corrosion process. After spreading a photosensitive material

  on the nitride layer 5, the epitaxial layer is exposed

  N-type taxicoid 3 by carrying out photochromic corrosion

  successive layer of the nitride layer 5 and the oxide layer 4, which are formed on the field region, and

  corrodes the exposed epitaxial layer 3, about 0.4 to 0.6

  pm, by removing the photosensitive material.

  FIG. 3C illustrates the step of forming a channel stop region. After spreading a photosensitive material 6 over the entire surface of the substrate, the part of the N-type epitaxial layer 3 is exposed. wherein a channel stopping region is to be formed, using a photochemical corrosion process, and forming an ion implantation region 7 by performing the implantation of boron ions (B) with an intensity of 2 at 20 x 1012 ions / cm 2 and an energy of 15 to 30 ke V. Figure 3 D will be described after the removal-from

  light-sensitive material 6, a layer of oxy-

  of field 8, over a thickness of 900 to 1100 nm using

  using a conventional thermal oxidation process, and then

  successively mine the nitride layer 5 and the oxide layer 4. In these conditions, the boron ions, which are

  implanted during the thermal oxidation operation of

  to form the oxide layer 8, diffuse so as to

  forming a channel stop region 9.

  Figure 3 E illustrates the step of forming a collector region. First, an oxide layer 10, at a thickness of about 50 to 80 nm, is grown over the entire surface of the collector region. substrate, and on this layer, a photosensitive material 11 is diffused. Then, the part in which the collector region is to be formed is exposed, corroding the photosensitive material.

  11, then phosphorous (P) ions are implanted

  towards the opening 12, with an intensity of 1 to 3 x 1015 ions / cm 2 and an energy of 80 to 100 ke V Then,

  a standard heat treatment operation is carried out

  which completes the formation of the region of

13.

  Figures 3 F to 3 J illustrate the steps

  to form a polysilicon base electrode at

  corrosion of the epitaxial layer 3, and

  sea a thick oxide layer below the electrode of

  polysilicon base First of all, with reference to the

  3, a nitride layer 14 is formed on the oxide layer 10 using a low pressure chemical vapor deposition process after removal of the photosensitive material 11, and on this layer a layer is formed. of oxide to a thickness between 500 and 700 nm using a conventional chemical deposition process

in the vapor phase (CVD).

  Then, a structure is formed using a

  conventional photochemical corrosion process to separate the emitter and base regions from each other, and the structure is specifically shaped in such a way that after spreading a photosensitive material on the oxide 15, this oxide layer 15, the nitride layer 14 and the oxide layer 10 are successively corroded so as to form the structure, the photosensitive material

being subsequently eliminated.

  With reference to FIG. 3G, a correction is applied

  anisotropic erosion at the part of the epitaxial layer 3 of

  type N, in which a polysilicon base electrode

  It should be formed at a depth of about 0.6 to 0.8 μm using the oxide layer 15, the layer

  nitride 14 and the oxide layer 10 as masks.

  As shown in FIG. 3H, a layer of nitride 16 is deposited on a thickness of about 100 to

  nm over the entire surface of the substrate, using

  a chemical process for deposition in the low-pressure vapor phase, then the anisotropic corrosion of the nitride layer 16 is carried out so that a layer of nitride

  16 'remains only on the side wall, as

  FIG. 3 illustrates the step of forming an oxide layer in the epitaxial layer, and as shown in this figure, a thick oxide layer 17 is 700 to 900 nm thick below the extrinsic base region by employing a

  thermal oxidation process using the layer of

  As shown here, the growth of the oxide layer 17 is inhibited by the presence of the nitride layer 16 'so that the oxide layer 17 is formed solely on the FIG. 3 K and 3 L illustrate the step of forming a polysilicon base electrode First, as shown in FIG. 3K, the nitride layer 16 'present on the wall is eliminated. lateral using

  phosphoric acid, then a layer of polysaccharide

  18 having a thickness of 1000 to 1500 nm using

  Then, as shown in FIG. 3 L, the polysilicon layer 18 formed by means of a method described above is polished so as to polish the layer of polysilicon 18, which is formed over the entire surface of the substrate, by means of the use of a conventional polishing process, which makes it possible to obtain an electrode

plain polysilicon base 19.

  Then, an implementation process io-

  to form a base region, by implanting boron ions throughout the surface of the substrate, with an intensity of 3 to 6 x 10 15 ions / cm 2 and an energy of 30 to 40 ke V. Referring to FIG. 3 M eliminates the oxide layer 15 located on the nitride layer 14 by implementing a wet corrosion process, and then

  form an oxide layer 20 having a thickness of

  between 300 and 500 nm using a process

  usual thermal oxidation at the base electrode in poly-

  In these conditions, the oxide layer 20 is formed only on the upper surface and on the side wall of the base electrode.

flat polysilicon 19.

  Figures 3 N and 30 illustrate the step

  Both to form an oxide layer on the side wall of the polysilicon flat base electrode 19 First, as shown in FIG. 3N, the nitride layer 14 is removed by employing a phosphoric acid solution. and using the oxide layer 20 as a mask of

  corrosion, then the oxide layer is removed.

  tercalaire, which is formed below the layer of ni-

  trure 14, using a solution of ordinary hydrofluoric acid Then, as shown in FIG.

  a thermal oxide layer 21 is grown

  with a thickness of 30 to 50 nm, at a temperature of about 9000 C, then boron ions are implanted in the entire surface of the substrate with an intensity of 1 to 10 x 1022 ions / cm 2 and with a Between 30 keV and 30 keV With reference to FIG. 3P, after carrying out the ion implantation, a layer is deposited

  of oxide on the entire surface of the substrate in

  using a conventional chemical vapor phase deposition process

  fear (CVD), and this layer is anisotropically corroded

  of oxide, so as to form an oxide layer on the

  lateral king 22 of the flat polysilicon base electrode

19.

  Figs. 3Q and 3R illustrate the ion implantation step for forming a base region and an emitter region. First, as shown in Fig. 3Q, a layer of polysilicon 23 is deposited on the ground. the entire surface of the substrate, over a thickness of between 200 and 400 nm using a conventional low pressure chemical vapor deposition (LPCVD) process,

  then boron ions are implanted with a

  between 1 and 5 x 10 14 inches / cm 2 and with

  taken between 30 and 40 ke V After having carried out

  ionization, diffusion is carried out at a temperature of

  of 9500 C, so as to form a basic

  trinsec 24 and an extrinsic base region 25 on the

silicon substrate.

  With reference to FIG. 3 R, arsenic (As) ions are implanted in the polysilicon layer 23, with an intensity of between 5 and 10 × 10 5 ions / cm 2 and with an energy of between 80 and 120 ke V, then we run

  a diffusion by implementing a usual method of diffe-

  Thermal melting at a temperature of about 1000 ° C. In this way, the emitter region 26, the intrinsic base region 24 and the extrinsic base region 25 are formed.

bipolar transistor.

  With reference to FIG. 3S, the layer is corroded

  of polysilicon 23 by implementing a method of

  erosion and in this way an electrode is formed

  polysilicon emitter 27 and a collector electrode

  Then, an oxide layer 29 is deposited on the entire surface of the substrate, over a thickness of between 300 and 500 nm, using a chemical vapor deposition process with activation by a laser. plasma (PACVD), then a corrosion process is carried out in order to expose the parts

  oxide layers, on which an electrode of col-

  a base electrode and an emitter electrode must be formed. Next, a conventional metallization method is used to form an emitter electrode, a base electrode 31 and a collector electrode.

  Finally, an alloying process is applied at one time.

  between 4000.degree. C. and 4500.degree. C. for 30 to 60 minutes.

  in order to complete the entire process of

  of the bipolar transistor operating at large

  in accordance with the present invention.

  In accordance with the present invention as described above, a base electrode is formed

  in the form of a layer of polysilicon,

  forms an extrinsic base region by diffusing the impurity from the base electrode, and forming a thick oxide layer below the base electrode so as to separate the region from one another base and collector region This has the effect that the junction capacity and the propagation time between the extrinsic base region and the collector region are reduced,

  which improves the characteristics of the transistor in

  In addition, the phenomenon of piercing caused

  the high concentration base region can be sup-

  awarded, so that one can get a high level for the

  breakdown voltage Therefore, with the same

  the breakdown voltage of the transistor, it is possible to

  to further increase the thickness of the

  taxonomy and therefore improve the characteristics of

  high speed of operation of the transistor.

Claims (6)

  1 Bipolar transistor operating at high voltage   with a buried layer (2) and a layer   epitaxial element (3) formed on a silicon substrate, a   channel stopper (9) formed beneath a field oxide layer (8) for providing isolation of the device, and polysilicon electrodes (27,19,28)   electrically connected to metal electrodes (30-   33), characterized in that said base electrode made of   lysilicon (19) is formed within said layer   epitaxial layer (3), that a thick layer of oxide (17) is   arranged below a base electrode (19) so as to separate said base region (25) and a collector region from one another, an oxide layer (21) is formed below said polysilicon layer (19) used as a base electrode, that a collector electrode (28) and an emitter electrode (27) are formed on the   previous oxide layer and are in contact with a   emitter region (26) and a collector region (13) in the vertical direction, and said polysilicon base electrode (19) is in contact with said base region   extrinsic (25), in the lateral direction.   2 Method for manufacturing a bipolar transistor   operating at high speed, characterized in that it in-   the step of forming a buried layer (2) of Ni type on a silicon substrate (1) by using a conventional method of forming a buried layer, and growing an epitaxial layer (3). ) N-type, the step of forming a layer   of oxide (4) and a layer of nitride (5), to perform a   photochemical erosion to expose the part o a   oxide layer must be formed, to carry out an implemen-   ionization and thermal oxidation to form a field oxide layer (8) and a channel stop region (9), the step of growing an oxide layer (10), to be spread a photoresist (11),   to provide an opening (12) by photochemical corrosion,   ionically implanting an impurity in said aperture (12) using said photoresist as a mask and diffusing said impurity to form a collector region (13), growing a layer of thick oxide (17) in said epitaxial layer (3), the step of performing a   polishing operation after the deposition of a layer of poly-   silicon (18) to form a polysilicon planar base electrode (19), the step of forming a base region, the step of forming an emitter layer (26) by the conventional diffusion method after introduction by ion implantation of an N-type impurity in a polysilicon layer (23), the step   of forming a polysilicon emitter electrode   (27) and a polysilicon collector electrode   (28) by photochemical corrosion of said layer of poly-   silicon (23), the step of depositing an oxide layer (29) over the entire surface of said substrate (1) by means of a conventional PECVD method (improved chemical vapor deposition with the use of of a plasma),   and to carry out a photochromic corrosion operation   to clear the area where an electrode of col-   reader, a base electrode and an emitter electrode must be formed, and the step of performing a metallization operation to form an electrode   transmitter (30), a base electrode (31) and a collector trode (32).   3 Method of manufacturing a bipolar transistor   high-speed operating film according to claim 2, characterized in that the step of forming said thick oxide layer (17) includes the partial step of forming a nitride layer (14) on said   oxide layer (10) by means of a conventional method of   low-pressure chemical vapor phase (LPCVD) process, the partial step of successively corroding an oxide layer (15), a nitride layer (14) and a   oxide layer (10) to form a network, the step   method of anisotropically corroding the surface of said N- type epitaxial layer (3), wherein a polysilicon base electrode is to be formed, and   the partial step of depositing a layer of   trurizing (16) across the surface of said substrate by a low pressure chemical vapor deposition process, the partial step of anisotropically etching said nitride layer (16) to form a layer nitride (16 ') forming a side wall, and a partial step of forming a thick oxide layer (17) in said epitaxial layer by means of a   conventional method of local thermal oxidation.   4 Process for manufacturing a bipolar transistor   operating at high speed according to claim 3,   characterized in that said nitride layer (16 ') forming a side wall is used as a mask for forming said oxide layer (17) only on said epitaxial layer (3).   A method of manufacturing a high speed bipolar transistor according to claim 2, characterized in that the step of forming said   base region includes the partial step of introducing   ion-implanting an impurity in the set of the surface of said substrate after formation of said polysilicon base electrode (19), the partial step -consisting in removing said oxide layer (15) by means of   of a wet corrosion process, the step   method of growing an oxide layer (20) on said polysilicon base electrode (19), the partial step of removing said nitride layer (14) and said oxide layer (10), then introduce by ion implantation a P-type impurity after having   a thin oxide layer (21), the step   to deposit an oxide layer and then to apply   causing anisotropic corrosion to form a sidewall spacer (22), the partial step of depositing a polysilicon layer (23) over the entire surface of said substrate, and the partial step of   to introduce an impurity by ion implantation into the   said polysilicon layer (23), then to perform a different   merge to form an intrinsic base region (24) and   an extrinsic base region (25).   6 Process for manufacturing a bipolar transistor   operating at high speed according to claim 5,   characterized in that said nitride layer (14) is used as a mask to form said layer   oxide (20) only on the top wall and the   side kernels of said polysilicon base electrode (19).   7 Process for manufacturing a bipolar transistor   operating at high speed according to claim 5,   characterized in that said oxide layer (20) is used as a corrosion mask during corrosion of said   layer (14) and said intercalated oxide layer (10).