GB2246222A

GB2246222A - Central processing unit

Info

Publication number: GB2246222A
Application number: GB9112910A
Authority: GB
Inventors: Masayuki Hirokawa
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1990-06-18
Filing date: 1991-06-14
Publication date: 1992-01-22
Anticipated expiration: 2011-06-14
Also published as: GB9112910D0; DE4120058A1; JPH0448331A; GB2246222B

Abstract

There is provided a central processing unit that includes a flash EEPROM 16 which stores micro instructions. The advantage of such a memory device is that the micro instructions can be erased and written with an electrical signal from the control circuit 17. Also inexpensive packaging of the CPU is possible in comparison with previously used EPROMS. <IMAGE>

Description

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CENTRAL PROCESSING UNIT Background of the Invention (Field of the Invention)

The present invention relates to an inexpensive central processing unit (CPU) including instruction systems adapted for associated respective purposes.

(Description of the Prior Art)

FIG. 3 is a plan view of a general-purpose microcomputer which comprises a central processing unit (CPU)40, an input/output circuit 41, a ROM42, and a RAM43, and which has wide applications to communication equipment such as facsimiles or to machine tools, and the like.

In recent practice of such a microcomputer, a micro code is written in a non-volatile memory such as a ROM or the like included in the CPU40 according to the types of microcomputers applied.

FIG. 4 is a block diagram illustrating the control of a prior CPU by such a micro code, for example. In the same figure, designated at 1 is a micro code ROM in which micro codes are stored, 2 is a decoder for decoding a microcomputer instruction to a micro instruction to determine micro operation, 3 is a control signal from the decoder, 4 is a bus for reading instructions and the like supplied from the outside, 5 is an internal bus, 6 is an ALU for executing each micro code, 7 is a micro instruction 1 transfer bus for transferring a micro instruction corresponding to each instruction from the micro code ROM, 8 is a data bus for outputting a result of execution by the ALU, 9 is a flag bus indicating the status of the result of the execution, 10 is a flag register for storing the result of the execution, and 11 is a register for storing data required for execution of any instruction o'r results of execution of instructions.

Operation of the prior CPU is as follows.

The CPU reads an instruction with which the bus 4 is loaded. The decoder 2 decodes the instruction and issues the control signal 3 to the micro code ROMI. The micro code ROMI supplies a micro instruction corresponding to the control signal 3 to the micro instruction transfer bus 7.

The ALU6 executes an operation corresponding to the micro instruction. Necessary data for that operation is taken out from the internal bus 5 and a result of that operation is fed to the data bus 8 and to the flag bus 9. The flag register 10 stores a status at that time. If the contents in the register 11 are necessary in the executed instruction, they are outputted to the internal bus 5 and the contents in the internal bus 5 are stored in the register Herein, the micro code ROMI is assumed that it can not be altered.

Accordingly, there is proposed a CPU incorporating a 1 1 i i 1 i 1 i j 1 i 1 i micro code EPROM12 illustrated in JFIG. 5 instead of the aforementioned micro code ROM1. In the same figure, designated at 13 is a write control circuit for controlling write operation into the EPROM12, 14 are data and control signalsissued from the write control circuit, and 15 are write control and data signals inputted from the outside of the microcomputer.

Referring to FIGs. 60) and 60), a package for mounting the CPU on a substrate is illustrated in plan and sec'tional views. In the figures, designated at 21 is a CPU device, 22 is a ceramic substrate for fixing the CPU, 23 is an upper cover, 25 is an adhesive for fixing the upper cover, 26 is a lead wire for inputting a device, 21 input/output signal and power supply GND, and 24 is a glass transparent_ to ultraviolet rays.

Ordinary operation of the just-mentioned CPU as a central processing unit is quite the same as the foregoing case where the micro code ROM was employed. When it is desired to alter the contents in the micro code, the above operation is interrupted and the micro code EPROM12 is irradiated externally with ultraviolet rays to erase the contents therein. The package with the glass 24 shown in FIG. 6 is therefore necessary. After the contents are erased, the write control and data signals 15 are inputted from the outside, whereby the write control circuit 13 1 1 creates the data and control signals 14 required for the wr i te opera t i on and wr i tes necess ary da ta (code s) i n to th e micro code EPROM12.

The prior CPUs which incorporate a mask ROM instead of the micro code ROM as shown in FIG. 4 can not alter the micro code. Additionally, the other prior CPUs which incorporate the EPROM12 instead of the micro.code ROM as shown in FIG. 5 suffer from complicated work because irradiation of ultraviolet rays is necessary for altering the contents in the ROM, and further from the need of an expensive package.

Summary of the Invention

In view of the drawbacks with the prior art, it is an object of the present invention to provide a CPU in which an inexpensive plastic package is useable and which is capable of changing a sequence of instructions to those fitted for each purpose.

A CPU in accordance with the present invention writes micro instructions into a flush E'PROM which is erasable electrically in the lump. Therefore, the contents of a micro code can be erased and rewritten through an electric signal.

The above and other objects, features, and advantages of the invention will become more apparent from the following description when taken in conjunction with the accompanying

1 1 i 1 1 i - 5 drawings.

Brief Description of the Drawings

FIG. I is a block diagram illustrating an embodiment of a central processing unit according to the present invention; FIG. 2A and 2B are a plan view and a sectional view each illustrating the situation of the central processing unit of the present invention being housed in a package; FIG. 3 is a plan view exemplarily illustrating a microcomputer; FIGs. 4 and 5 are block diagrams each illustrating a prior central processing unit; and FIGs. 6A and 6B are a plan view and a sectional view each illustrating the situation of the prior central processing unit being housed in a package.

Description of the Preferred Embodiment

In what follows, an embodiment of the present invention will be described with reference to FIGs. I and 2.

As illustrated in FIG. 1, designated at 16 is a micro code storage section which comprises a flash E'PROM, 18 is a signal for erasing the contents in the flash E'PROMIC, 17 is an erase/write control circuit for erasing and writing the contents in the flash E.'PROM, and 19 is an external erase signal. Additionally, designated at 2 is a decoder for decoding an instruction of a microcomputer to a micro instruction to determine micro operation, 3 is a control signal from the decoder, 4 is a bus for reading an external instruction and the like, 5 is an internal bus, 6 is an ALU for executing each micro code, 7 is a micro instruction transfer bus for transferring a micro instruction corresponding to each instruction from a micro code ROM, 8 is a data bus for outputting an execution result by the ALU, 9 is a flag bus for indicating the status of the execution result, 10 is a flag register for storing the execbtion result, 11 is a register for storing data required for the execution of any instruction or an execution result, and 14 is data and a control signal.

Such a CPU device 21 is constructed by being molded with a plastic material 27 as illustrated in a plan view and a sectional view of FIGs. 2A and 2B. Herein, designated at 26 is a lead terminal.

Operation of the embodiment constructed as described above is as follows.

Ordinary operation is the same as in the prior CPU. When the contents in the micro code is desired to be altered, instruction execution is interrupted and the external erase signal 19 is inputted. The erase/write control circuit 17 is operable by the erase signal 19 to issue the electric signal 18 for erasing the contents in the flash E'PROM16. The contents in the flash E'PROM16 are 1 1 :z 1 i i 1 i - 7 erased by a series of the operations. In succession, the external write control signal and data signal 15 are inputted to operate the erase/write control circuit 17 which in turn issues the signal and data 14 needed to be written in the flash E'PROM16. Hereby, any necessary micro code is written in the flash E'PROM16.

Once the write operation is completed, the sections 14 through 19 required for the erase and write operation are separated as circuits and allowed to operate as CPUs.

According to the present invention, as described above, the CPU micro code (instruction) is stored in the flash E'PROM. Theref ore, a 1 tera t i on o f th e con ten ts i s as s tired and an inexpensive package is useable.

Claims

What is claimed is:

1. A central processing unit for reading an external program and decoding operation sections of instructions to execute the operation corresponding to each instruction, the central processing unit realizing, in the control of the execution of the decoding and operation of each said instruction, each said instruction in a combination of micro operations by decomposIng the actual opera tion in the central processing unit into further fine micro operations to execute the micro operations in the form of micro instructions, the improvement being such that said micro instructions are stored in a flash E'PROM.

2. A central processing unit according to claim 1 wherein it includes an erase/write control circuit for issuing an erase electric signal and data to the flash E2PROM.

Published 1992 at The Patent Office. Concept House. Cardiff Road. Newport. Gwent NP9 IRH. Further copies may be obtained Iron) Sales Branch. Unit 6. Nine Mile Point. Cwtrifelinfach. Cross Keys. Newport. NPI 7HZ. Printed by Multiplex techniqucs hd Si Mar Cray. Kent.

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