JPH0448331A - Central processing unit - Google Patents

Abstract

PURPOSE:To use an inexpensive package whose contents can be changed by storing a CPU microcode in a flash E<2>PROM. CONSTITUTION:The microinstructions are written into a flash E<2>PROM so that they are electrically erased en bloc. That is, an instruction executing operation is discontinued to change the contents of a microcode. Then an erasion signal 19 is inputted from the outside. Thus an erasion/write control circuit 17 works to output a signal 18 in order to erase the contents of a microcode flash E<2>PROM 16. Then a write control signal and the data 15 are inputted from the outside, the circuit 17 works to output a signal and the data 14 necessary for a writing operation. Thus a necessary microcode is written into the E<2>PROM 16. As a result,the contents of the microcode can be erased and rewritten with an electric signal. In such a constitution, an expensive plastic package is available.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is for realizing a central processing unit (CPU) having an instruction system tailored to each purpose at low cost.

[Conventional technology]

FIG. 3 is a plan view of a general microcomputer, in which 40 is a central processing unit (CPU);
1 is an input/output circuit, 42 is a ROM, 43 is a RAM,
Widely applied to communication equipment such as facsimile machines, machine tools, etc.

In recent years, the nonvolatile memory such as ROM included in the CPU 40 has been changed depending on the applicable model of the microcomputer.
We try to write the microcode appropriate for the model in question.

FIG. 4 is a block diagram showing, for example, conventional CPU microcode control. In FIG. 4, 1 is a microcode ROM in which the microcode is stored, 2
is a decoder that decodes microcomputer instructions into microinstructions and determines micro operations; 3 is a control signal from the decoder; 4 is a bus for reading out instructions from the outside; 5 is an internal bus; and 6 is each microcode. 7 is a microinstruction transfer bus that sends microinstructions corresponding to each instruction from the microcode ROM to the ALU, 8 is a data bus that outputs the execution results of the ALU, 9
10 is a flag bus that indicates the state of the execution result; 10 is a flag register that stores the result; and 11 is a register that stores data necessary for executing the instruction or the execution result.

Next, the operation will be explained. The CPU reads the instructions,
The data is loaded onto bus 4. The decoder 2 decodes the command and sends a control signal 3 to the microcode ROMI. The microcode ROM 1 sends a microinstruction corresponding to the control signal 3 to the microinstruction transfer bus 7. AL
U6 executes the operation corresponding to this microinstruction. At this time, data necessary for the operation is taken out from the internal bus 5 and the results are output to the data bus 8 and flag bus 9. The flag register 10 stores the state at this time. If necessary in an executed instruction, the contents of the register 11 are output to the internal bus 5, or the contents of the internal bus 5 are stored in the register 11. The microcode ROMI cannot be changed here.

Therefore, as shown in FIG.
Instead of MI, as shown in FIG. 5, a write control circuit controls the write, I4 is a data and control signal output from the write control circuit, and 15 is a write control and data signal input from outside the microcomputer. It is.

FIGS. 6(a) and 6(b) are a plan view and a sectional view showing a pan cage for mounting a CPU on a board, in which 21 is a CPU device and 22 is a ceramic substrate for fixing the CPU. , 23 is the top cover, 25 is the adhesive that fixes the top cover, 26 is the device 21 output signal, power supply G
The lead wire 24 for inputting the ND is made of glass that transmits ultraviolet rays.

In its normal operation as a central processing unit, it is exactly the same as a microcode ROM. When changing the contents of the microcode, stop the above operation, apply ultraviolet light to the microcode EPROM 12 from the outside,
Erase contents. Therefore, a pancage having a glass 24 as shown in FIG. 6 is required. After erasing the contents, write control and data signals 15 are input from the outside, and the write control circuit 13 creates signals and data 14 necessary for writing, and writes the necessary data (code) to the microcode EPROMI 2.

[Problem to be solved by the invention]

The conventional CPU has a microcode RO as shown in Figure 4.
If M is a mask ROM, the microcode cannot be changed. Also, as shown in Figure 5, even if the microcode ROM is replaced with EPROM12, the ROM
It is necessary to irradiate ultraviolet rays to change the content of the powder, which makes the work cumbersome and requires an expensive puff cage.

This invention was made to solve the above problems, and allows the use of inexpensive plastic packages.
The purpose is to obtain a CPU whose instruction system can be changed to one suitable for each purpose.

[Means to solve the problem]

The CPU according to the present invention is designed to write microinstructions in a flash E'' FROM which can be electrically erased all at once.

[Effect]

The CPU according to the present invention can erase and rewrite the contents of the microcode using electrical signals, making it possible to use an inexpensive plastic package.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. In Fig. 1, 16 is a microcode storage unit, which is composed of a flash E" FROM. 18 is a signal for erasing the contents of the flash E2 PROMI, etc., and 17 is a control for erasing and writing the contents of the flash E" FROM. A circuit 19 is an external erase signal. 2 is a decoder that decodes microcomputer instructions into microinstructions and determines micro operations; 3 is a control signal from the decoder; 4 is a bus for reading instructions from the outside; 5 is an internal bus; 6 is each ALU for executing the microcode; 7 is a microinstruction transfer bus that sends microinstructions corresponding to each instruction from the microcode ROM to the ALU; 8 is a data bus that outputs the execution results of the ALU; 9 is the execution result 10 is a flag register for storing the result; 11 is a register for storing data or execution results necessary for executing an instruction; 1;
4 is data and control signals.

Such a CPU device 21 is shown in FIG. 2(a).

As shown in the plan view and cross-sectional view of (b), it is constructed by molding a plastic material 27. Note that 26 is a lead terminal.

Next, we will explain the operation. 0 Normal operation is the conventional CPU.
It is similar to When changing the contents of the microcode, the instruction execution operation is stopped and an erase signal 19 is input from the outside. Based on this erase signal 19, the erase/write control circuit 17 operates and outputs a signal 18 for erasing the contents of the flash E" FROMI 6. Through this series of operations, the contents of the flash E" FROMI 6 are erased. .

Next, a write control signal and a data signal 15 are input from the outside, and the erase/write control circuit 17 operates to output the signal and data 14 necessary for writing to the flash E'' FROMI 6. F
Write the necessary microcode to ROMI 6.

When writing is completed, the area necessary for erasing and writing 1
4 to 19 are separated in terms of circuitry and operate as a CPU.

〔Effect of the invention〕

As described above, according to the present invention, since the CPU microcode (instructions) is stored in the flash E'' FROM, the contents can be changed, and an inexpensive package can be used.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the central processing unit according to the present invention, FIGS. 2(a) and 2(b) are a plan view and a sectional view showing the central processing unit according to the present invention housed in a package, FIG. 3 is a plan view showing an example of a microcomputer, FIGS. 4 and 5 are block diagrams showing an example of a conventional central processing unit, and FIG. 6(a). (b) is a plan view and a sectional view showing a conventional central processing unit housed in a package. 1 is a microcode ROM, 2 is a decoder, 3 is a control signal, 4 is an instruction bus, 5 is an internal bus, 6 is an ALU, 7 is an instruction transfer bus, 8 is a data bus, 9 is a flag bus, 10 is a flag register, 11 is a register, 12 is a microcode EPROM, 13 is a write control circuit, 14 is a control signal, 15 is a control and data signal, 16 is a flash E2
PROM, 17 erase and write control circuit, 18 erase signal, 19 erase signal, 21 device, 22 ceramic substrate, 23 upper cover, 24 glass, 25 adhesive,
26 is a lead wire, and 27 is a plastic mold. Agent Patent attorney Jun Miyazono - Figure 2 (a) (b) Procedural amendment (spontaneous) Figure 6 Heisei Kamihira/June Kamiguchi

Claims (1)

[Scope of Claims] A central processing unit that reads a program from the outside, decodes the operation part of the instructions, and executes the operation corresponding to each instruction,
This method of controlling the decoding of each instruction and the execution of operations breaks down the actual operations within the central processing unit into smaller micro-operations, and executes the micro-operations in the form of micro-instructions. A central processing unit realized by a combination of the following: A central processing unit characterized in that microinstructions are stored in a flash E^2PROM.