GB2233823A

GB2233823A - Integrated circuit arrangement

Info

Publication number: GB2233823A
Application number: GB9015235A
Authority: GB
Inventors: Armin Lederer; Jurgen Zimmermann
Original assignee: Diehl GmbH and Co
Current assignee: Diehl Verwaltungs Stiftung
Priority date: 1989-07-15
Filing date: 1990-07-11
Publication date: 1991-01-16
Anticipated expiration: 2010-07-11
Also published as: DE3923533A1; FR2649851A1; GB9015235D0; GB2233823B

Abstract

In the arrangement of an integrated circuit chip 11 on a multilayered circuit carrier (substrate 15) substrate bond connections 20 are arranged in a narrow connection strip 26 outside the circus boundary 13 in accordance with the geometry of the chip connections 12. The front ends of vias 16 which are of large area in cross-section compared with the conductor-path transverse dimensions are situated on a wider edge strip 25 beneath the chip mounting region 22 and are connected by thin conductor paths 19 to the substrate bond connections 20. <IMAGE>

Description

v 1 ARRANGEMENT OF AN INTEGRATED CIRCUIT ON A CIRCUIT CARRIER This

invention relates to an arrangement of an integrated circuit on a circuit carrier, for example, for a compact circuit structure or assembly of signal processors in flying bodies in accordance with, for

instance, U.S. Patent Specification No. 4,698,729.

Such an arrangement is disclosed, for instance, in EP-OS 0 272 046 or in the PCT publication WO 87/01510. The circuit carrier built-up in a multilayer manner and selectively contacted between its conductor-path planes by means of electrically conductive through- paths or vias (see EP-OS 0 220 508) has, in the chip assembly (fitting) region, a depression with offset side walls, steps of which side walls are afforded by various substrate planes of the circuit carrier and equipped with connections for the bond wires to the circuit connections. As a result of this staggering transverse to the circuit boundary, more substrate connections can be accommodated along the boundary than in a narrow strip along the circuit boundary. In the case of wide staggering it is advantageous that the substrate connections can be designed so large in their cross-sectional surface area that they can at the same time serve as f ront or end regions of the associated vias into the sandwich or laminated plane, desired in circuitry respect, of the circuit carrier. What tends to be disadvantageous is, however, not only the relatively large space requirement around the circuit (which prohibits a dense arrangement of circuits on the circuit carrier) but, above all, the fact that for laying of the bond wires out of the connection planes of the circuit into connection planes (offset thereagainst), on the circuit carrier, no conventional bond device is usable, and that an increased risk of short-circuiting results from the path of the 2 bond wires bridging relatively large arcs with small lateral spacings. Basically, therefore, it should be striven after to arrange the substrate connections all in one plane and in each case closely adjacent to the circuit connections, as is known 'per sey from conventional chip bond technology of small circuits. However, in the case of highly- integrated large circuits (L.S.I's), along the boundaries thereof, however, so many bond connections are present that the geometrically associated, closely adjacent substrate connections cannot be designed large enough for formation of the wiring through-paths or vias into the interior of the laminated circuit carrier.

In recognition of these factors, an aim of the present invention is to provide an arrangement which allows, on the one hand, short bond wire connection and, on the other hand, vias which are large in crosssectional surface area as well as a close packing of the circuits on the circuit carrier.

In accordance with the present invention there is provided an arrangement of an integrated circuit on a circuit carrier, through-contacted in a multilayered manner, with bond wires between chip and substrate connections characterised in that in a narrow connection strip parallel to the boundary of the chip mounting region the substrate connections are arranged in to someextent identical or similar dimension and geometrical sequence as the chip connections on the circuit, in the plane of the substrate surface, on which thin conductor paths extend from the substrate connections into an edge strip of the chip mounting region under the integrated circuit and, spreading-out there, end at mutually offset front ends of vias, which vias have a cross-section which is considerably larger then the width of the conductor paths.

Accordingly, the narrow strip for the arrangement of the substrate connections need have only the surface-area requirement of the circuit connections and can therefore be arranged directly parallel to these outside the chip 5 boundary on the surface of the circuit carrier. The substrate connections may be connected in this uppermost plane by way of conductor paths to the f rontal ends of the vias, which outside the circuit take up no space on the circuit carrier, because they are displaced into a relatively wide edge strip of the chip assembly region under the circuit. There, seemingly, they can be fashioned in optimum cross-sectional dimension and mutual orientation and be equipped with a conductive core, which in addition to the electrical connection function also assumes a heat-dissipating function.

Preferably, the laminated circuit carrier is provided from a stack of ceramic leaves which are approximately paper-shaped in the unfired or unburnt state and which are printed in accordance with circuitry requirements With conductor-path (conductor-track) designs; after the via holes are introduced later axially in alignment with one another and are filled with core material. The mechanically secure ceramic circuit carrier emerges when the pressed stack is burnt (fired) and sintered. As a result of this heat treatment the ceramic substrate not only becomes (by reason of its high glass content) hermetically tight, but the initially still non-electrically conducting thick-layer conductor- path structure on the individual planes also becomes electrically conductive.

For the individual substrate layer, advantageously recourse is had to a material which is known under the trade name GREEN TAPE by Messrs. DU PONT. For realisation of the connection conductor paths between the substrate connections and the frontal ends of the vias,in 4 fine-conductor technology a film structure can be evaporated or vaporised on (AUFGEDAMPFT), which is known as high-energy explosion coating DYBO of Messrs. Schering. However, also other f ine-structure processes are usable, such as for instance the additive application of chemical copper of Messrs. Schering or the gold-powder immersion seeding (BEKEIMEN) known as the DU PONT PCS process. Compared with conventional thin-film technology, these relatively thick-layer processes for the formation of the fine conductor paths have the advantage that larger currents can f low by way of the small conductor cross-sections; and, moreover, these thicker structures are more insensitive to fine-crack formation by reason of mechanical stresses. The shrinkage, occurring upon the sinter process, of the conductor-path exposure pattern is indeed anisotropic over the material, but quantitatively known, so that a compensation by correspondingly distorted geometry upon the application of the exposure conductor paths can be realised prior to the sintering process. This applies in accordance with the position of the vias, in order to avoid the holes in the individual substrate layers having such a mutual displacement that no continuous conduction core would arise upon stacking of the filled holes.

Additional alternatives and further developments as well as further features and advantages of the present invention will become apparent from the sub claims and from the following description of a preferred example of the present invention which is shown, by way of example only, in the much simplified drawing in a highly abstracted manner but approximately true-to-scale. The sole figure of the drawing shows in broken-away representation the top view of a multilayer circuit carrier with an integrated circuit mounted thereon.

The integrated circuit 11 (IC-chip) (shown in a much enlarged manner and cut-away) of square structure with bond connections 12 (Pads) in a narrow connection strip 26 along each of its lateral boundaries 13, is a socalled large circuit (L. S. I.), which is distinguished by a multiplicity of signal -process ing- technology functions realised therein and by a (thereby occasioned) very large number of connections 12 for supply of the operatingvoltage levels and of items of input information, as well as for the issuance of items of processing information.

The undersurface of the circuit 11 is fastened (not discernible in the drawing) in known 'per sel manner by means of a good heat-conducting adhesive, directly, or respectively, if required, along with interpolation of an electrical insulating layer (under a conducting layer to the rear-side potential connection at the circuit 11), in a predetermined mounting region 22 (the pad), onto the surface 14 of a multilayer circuit carrier 15 (substrate). Carrier 15 has on its individual carrier layers, mounted above one another, conductor-path structures for the connection of specific chip connections 12 -with one another and with the connections of further circuits arranged appropriately on the carrier 15. The transverse connection between the individual conductor-path planes in the interior of the multilayer circuit carrier 15 is effected by means of so-called through-holes 16 (vias), thus by means of bores 17 which for the through-contacting have a core 18 made from electrically conductive material.

The f ront regions, reaching the substrate surf ace 14, of the vias 16 are connected in an electrically conductive manner, by way of conductor paths 19, to substrate connections 20 (Bonding Pads) on the substrate surface 14. The substrate connections 20 are arranged in a narrow strip 26 parallel to the circuit boundary 13, and outside the circuit surface, in a pattern which is at least geometrically similar to the arrangement pattern of 6 the chip connections 12, and preferably corresponds therewith by an identical or sequential or succession line (FOLGELINIE) and close staggering (see in the drawing the geometrical association of the substrate connections 20-shown square-with the chip connections 12 represented as small rings). The electrical connection between the geometrically associated chip and substrate connections 12-20 is effected in known 'per se' manner, e. g. by bond wires 21 or by a Tape Automatic Bonding process.

In order to accommodate the functionally necessary large number of connections 12 (and accordingly 20) along a circuit boundary 13, the width dimensions of the connections 12, 20 cannot be designed substantially larger than the conductor paths 19, extending side-byside, on the substrate surf ace 14. In practice, the connection dimensions are selected to be so small that e. g. an automatic laying of the bond wires 21 with commercially available bond devices is only just still feasible. These cross-sectional dimensions are, however, too little for the formation of the vias 16. This is because for technological reasons the bores 17, which are positioned in the individual layers of the circuit carrier 15 prior to completing lamination thereof, cannot have an arbitrarily small diameter, so that the mutual displacement, which cannot entirely be precluded, of the individual layers cannot lead to an interruption of the through-contacting core 18, nor lead to a contacting with closely approaching (but not correct) adjacent conductor paths in the respective carrier plane. If one wished to enlarge the substrate connections 20 themselves to such cross-sections that they could at the same time be used as f rontal ends of the vias 16, then the raster of the chip connections 12 might not remain adhered to; this is because, as a result of the diameter enlargement, the length of a chip boundary 13 would not be suf f icient to 7 be able to arrange all the vias 16 side-by-side in a line. One would, therefore, then have to stagger the vias 16 also transversely to the chip boundary 13, and thus fan or spread-out (AUFFACHERN) the vias in a fairly wide strip in two directions on the substrate surface 14. This would, however, on the one hand stand in the way of a closely adjacent arrangement of circuits 11 on the circuit carrier 15 (because around a circuit 11 the wider connection strip would be taken up for vias -16 arranged in fanned-out or spread-out manner) and, on the other hand, it would be disadvantageous that through-hole substrate connections situated further away from the circuit boundary 13 would require longer bond wires to the associated chip connections 12, which on account of the extremely thin wires and with respect to the mechanical stressability would be problematical in production-technology respects. Therefore, instead of that, fanning or spreading out the vias 16, of relatively large area in cross-section, (indeed in a strip 25 along the boundary 13) under the mounting region 22 of the circuit 11 is displaced onto the substrate surface 14. From there, the conductor paths 19 lead to the close succession or sequence of substrate connections 20 (associated with the chip connections 12), so that now the surface requirement of the connection strip 26 lies only in the order of magnitude of the surface area of the chip connections 12 themselves, as is evident from the drawing. In the mounting region 22 on the other hand, thus under the circuit 11, sufficient space is available in order to optimise the size and mutual arrangement of the vias 16 in view of the technological requirements upon the provision of the stratified circuit carrier 15, thus to distribute the vias end surfaces, which are very much larger in cross-section compared with the narrow conductor paths 19, on the edge strip 25.

Indeed, now a wide edge strip 25 of the mounting 8 region 22 (along the circuit boundary 13) is occupied by the arrangement of the vias 16 and their conductor paths 19. In the centre 23 of the mounting region 22, f ree space still remains for the arrangement of a heat sink in 5 the form of a heat-dissipating stamp 24, which in known ?per sel manner dissipates the waste heat upon operation of the circuit 11, out of the plane of the mounting region 22 into the interior of the circuit carrier 15 and, for example, transfers waste heat onto large- surface conductor-path regions. In the edge strip 25 the heatdissipation problems are on the other hand not so great, because the ambient atmosphere acts above the circuit edge in a larger-surface manner (over a large surface area). Moreover, an additional heat dissipation to the interior of the circuit carrier 15 is effected through the relatively close succession (sequence) of the through-hole or vias cores 18 (made from electrically and thermally good conductive material) which reach down into different substrate depths.

The narrow connection strip 26, now only needed outside the chip mounting surf ace 22, for the substrate connections 20 and the contiguous ends of their conductor paths 19, along the circuit boundary 13, is coverable by a correspondingly narrow frame after the formation of the bond connections 21, alongside which, such a connection strip for a circuit to be mounted adjacent thereto on the circuit-carrier surface 14 can directly follow.

Thus, to summarise, the arrangement of an integrated circuit chip 11 on a circuit carrier (substrate 15) through-contacted in a multilayered manner is effected in such a way that even in the case of an extremely large number of chip bond connections (pads 12) along each circuit boundary 13 conventional bond technologies remain usable for the provision of operationally reliable bond connections 21 and nevertheless a close packing of 9 circuits 11 on the substrate surface 14 becomes realisable. For this, the substrate bond connections 20 are arranged in a narrow connection strip 26 in front of the circuit boundary 13 in accordance with the geometry of the chip connections 12, but the front ends of through holes - vias 16 (which are of large area in cross-section compared with the conductor- path transverse dimensions) are displaced mutually offset to the switching connections on the lower-situated substrate planes into a wider edge strip 25 in the chip mounting region 22 and are connected by the thin conductor paths 19 to the substrate bond connections 20.

It is to be understood that the scope of the present invention is not to be unduly limited by the particular choice of terminology and that a specific term may be replaced or supplemented by any equivalent or generic term where sensible. Further it is to be understood that individual features, method or functions related to the integrated circuit and/or the circuit carrier or connection arrangement might be individually patentably inventive. Additionally, the singular may include the plural or vice versa where appropriate and any word or phrase herein being a translation of a word from the

Claims

German priority document should not be construed as unecessarily limiting

and is meant to encompass other possible English meanings. The present invention may comprise that contained in the characterising portion ofClaim 1.

Further according to the present invention there is provided an arrangement of an integrated circuit connected or connectable on a multilayered circuit carrier, having bond wires or bond electrical connection means extending in use between connections on the integrated circuit and connections on a substrate of the circuit carrier, and in which, in use, the substrate connections are arranged in a matching sequence with the connections on the integrated circuit, and preferably in the plane of the substrate surface, conductor paths extend from the substrate connections in underlying relationship with said integrated circut, and the conductor paths are connected to vias extending through the layers of the circuit carrier, said vias preferably being of a cross section larger than the width of the conductor paths.

11 CLAIMS 1. Arrangement of an integrated circuit on a circuit carrier, through- contacted in a multilayered manner, with bond wires between chip and substrate connections characterised in that in a narrow connection strip parallel to the boundary of the chip mounting region the substrate connections are arranged in to some extent identical or similar dimension and geometrical sequence as the chip connections on the circuit, in the plane of the substrate surface, on which thin conductor paths extend from the substrate connections into an edge strip of the chip mounting region under the integrated circuit and, spreading-out there, end at mutually offset front ends of vias, which vias have a cross-section which is considerably larger than the width of the conductor paths.
2. Arrangement according to Claim 1, in which the vias, of large area in cross-section, are fashioned as bores in the individual - layers of the circuit carrier and are filled by an electrically and thermally conductive core.
3. Arrangement according to Claim 1 or 2, in which the conductor paths are fashioned in thick-layer technology on the topmost layer of a stack of ceramic laminates.
4. Arrangement according to any one of the precedingclaims in which the connection strips outside the circuit boundary with their bond wires to the circuit connections are masked by a narrow frame.
5. Arrangement of an integrated circuit on a circuit carrier substantially as herein described with reference to the FIGURE of the drawing.

An arrangement of an integrated circuit connected or 12 connectable on a multi-layered circuit carrier, having bond wires extending in use between connections on the integrated circuit and connections on a substrate of the circuit carrier, and in which, in use, the substrate connections are arranged in a matching sequence with the connections on the integrated circuit, and in the plane of the substrate surface, conductor paths extend from the substrate connections in underlying relationship with said integrated circut, and the conductor paths are connected to vias extending through the layers of the circuit carrier, said vias being of a cross section larger than the width of the conductor paths.

Published 1991 at The Patent 0111ec. State Houm-- 66'71 Iflult lic, Iiinriz WC I R 4TP. Ftinlitr(.opic ni;i bt Irm- Ttic Sale, Branth. Si Marx.Cray- Kew BR5 31d)- Printed by Multiple., Si Man- Cray. Ken ' ( ' n]is.