GB9015235D0 - Arrangement of an integrated circuit on a circuit carrier - Google Patents
Arrangement of an integrated circuit on a circuit carrierInfo
- Publication number
- GB9015235D0 GB9015235D0 GB9015235A GB9015235A GB9015235D0 GB 9015235 D0 GB9015235 D0 GB 9015235D0 GB 9015235 A GB9015235 A GB 9015235A GB 9015235 A GB9015235 A GB 9015235A GB 9015235 D0 GB9015235 D0 GB 9015235D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- circuit
- arrangement
- carrier
- integrated circuit
- integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19893923533 DE3923533A1 (en) | 1989-07-15 | 1989-07-15 | ARRANGEMENT OF AN INTEGRATED CIRCUIT ON A CIRCUIT BOARD |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9015235D0 true GB9015235D0 (en) | 1990-08-29 |
GB2233823A GB2233823A (en) | 1991-01-16 |
GB2233823B GB2233823B (en) | 1993-04-14 |
Family
ID=6385175
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9015235A Expired - Fee Related GB2233823B (en) | 1989-07-15 | 1990-07-11 | Arrangement of an integrated circuit on a circuit carrier |
Country Status (3)
Country | Link |
---|---|
DE (1) | DE3923533A1 (en) |
FR (1) | FR2649851A1 (en) |
GB (1) | GB2233823B (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5557505A (en) * | 1994-07-22 | 1996-09-17 | Ast Research, Inc. | Dual pattern microprocessor package footprint |
US5818114A (en) * | 1995-05-26 | 1998-10-06 | Hewlett-Packard Company | Radially staggered bond pad arrangements for integrated circuit pad circuitry |
US5777853A (en) * | 1996-05-03 | 1998-07-07 | Ast Research, Inc. | Printed circuit board having a dual square pattern footprints for receiving one of two electronic components having equal printouts per size |
US5764488A (en) * | 1996-06-11 | 1998-06-09 | Ast Research, Inc. | Printed circuit board having a dual pattern footprint for receiving one of two component packages |
US5751557A (en) * | 1996-06-21 | 1998-05-12 | Ast Research, Inc. | Printed circuit board having a triple pattern footprint for receiving one of three component packages |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4109377A (en) * | 1976-02-03 | 1978-08-29 | International Business Machines Corporation | Method for preparing a multilayer ceramic |
US4221047A (en) * | 1979-03-23 | 1980-09-09 | International Business Machines Corporation | Multilayered glass-ceramic substrate for mounting of semiconductor device |
US4437141A (en) * | 1981-09-14 | 1984-03-13 | Texas Instruments Incorporated | High terminal count integrated circuit device package |
IL80683A0 (en) * | 1985-12-20 | 1987-02-27 | Hughes Aircraft Co | Chip interface mesa |
JPH0773117B2 (en) * | 1986-11-25 | 1995-08-02 | 株式会社東芝 | Semiconductor package |
GB2199182A (en) * | 1986-12-18 | 1988-06-29 | Marconi Electronic Devices | Multilayer circuit arrangement |
GB2209867B (en) * | 1987-09-16 | 1990-12-19 | Advanced Semiconductor Package | Method of forming an integrated circuit chip carrier |
EP0351581A1 (en) * | 1988-07-22 | 1990-01-24 | Oerlikon-Contraves AG | High-density integrated circuit and method for its production |
-
1989
- 1989-07-15 DE DE19893923533 patent/DE3923533A1/en not_active Ceased
-
1990
- 1990-07-11 GB GB9015235A patent/GB2233823B/en not_active Expired - Fee Related
- 1990-07-13 FR FR9008937A patent/FR2649851A1/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
GB2233823B (en) | 1993-04-14 |
GB2233823A (en) | 1991-01-16 |
FR2649851A1 (en) | 1991-01-18 |
DE3923533A1 (en) | 1991-01-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19940711 |