GB2232311A

GB2232311A - Temperature-compensated CMOS input interface circuit

Info

Publication number: GB2232311A
Application number: GB8918991A
Authority: GB
Inventors: Tae-Sung Jeong
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1989-05-27
Filing date: 1989-08-21
Publication date: 1990-12-05
Anticipated expiration: 2009-08-21
Also published as: JP2651246B2; DE3926657A1; GB8918991D0; GB2232311B; KR910009810B1; FR2647608B1; KR900019380A; DE3926657C2; NL190137C; JPH0311823A; NL8902048A; FR2647608A1; NL190137B

Description

1 CMOS INPUT BUFFER CIRCUIT The present invention relates to a CMOS input

buffer circuit, and in particular, to an input buffer circuit which is used for the CMOS-type ultra high density semiconductor device and which has a logic threshold voltage with temperature compensation.

Because of the trend towards high-integrity, highprecision and highperformance semiconductor devices, power consumption is increased. Hence, more careful consideration to the operating characteristics resulting from temperature change is required.

Generally, a CMOS input buffer circuit comprises cMOS inverters, to the input terminal of which is applied an input signal with a TTL voltage level, and from the output terminal of which is outputted an output signal which is converted i nto a CMOS vo I tage 1 eve 1. However, the logic threshold voltage of the CMOS inverter varies with every change of temperature. Therefore, at low temperature, the high level input characteristics worsen, since the logic threshold voltage level is raised. On the other hand, at high temperature, the low level input characteristics worsen, since the logic threshold voltage level is lowered.

2 Thus variations in the input characteristics, resulting from surrounding temperature changes, cause some problems, such as unstable operation or reduction in operation speed.

The logic threshold voltage of the CMOS inverter is a function of the ratio between the gain constants for a pchannel and an n-channel MOS transistor and the threshold voltage of the device.

The device gain constant(PS,), since the mobility of the channel carrier is decreased in accordance with the increase of temperature, is decreased to 13 cc 1/,.f-T3. However, since both the mobility of holes and of electrons are affected by temperature to a similar extent, the ratio between the gain constants (13 ratio = 13 n 113 P) is independent of the temperature.

On the other hand, the threshold voltages Vtn and Vtp of the device decrease, by the temperature coefficient of 2mV/ K, respectively, in accordance with the increase of temperature. Therefore, for example, if the temperature is increased by 50 C, the logic threshold voltage is decreased by 0.4V. Therefore, the low-level input characteristics of the CMOS input buffer circuit worsen for high-temperature range operation, and the high-level input characteristics worsen for low-temperature range operation.

Therefore, it is an object of this invention to provide Z 3 1 a CMOS input buffer circuit that has temperature-compensated logic threshold voltage characteristics, by varying the ratio of the MOS transistor gain constant in response to temperature change.

It is another object of this invention to provide a CMOS input buffer circuit that minimizes the change in input characteristics of very large scale integrated semiconductor devices with temperature change.

To accomplish these objects the CMOS input buffer circuit in accordance with the present invention comprises:

a first MOS transistor of a first conduction type and a second MOS transistor of a second conduction type which are interconnected in series between a first power supply and a second power supply line, and to the control electrodes of which is applied in parallel input voltage of a TTL voltage level, and to the common connection point of drains of which is supplied output voltage of a CMOS voltage level in correspondence to said input voltage; at least one combination of a MOS transistor of a first conduction type and a switching means which are interconnected in series between said first power supply line and said common connection point, the control electrode of the MOS transistor being coupled to said input voltage, and said switching means being turned on above a certain predetermined temperature and turned off below it; a temperature detection means having at least one output terminal - 4 connected to the control signal input terminal of said at least one switching means in order to control the same in accordance with temperature changes; whereby the overall gain constant value of the transistor for each of said transistors of a first conduction type is decreased at low temperature and increased at high temperature, and thus variation in logic threshold voltage is stabilized in accordance with temperature.

Preferably each of said first conduction type transistors is a pchannel MOS transistor, whilst each of said second conduction type transistors is an n-channel MOS transistor, and the switching means is a p-channel MOS transistor. Therefore, when the switching means is turned on, the gain constant 13 p of the p-channel transistors will be increased and thus the ratio between gain constants (0 ratio) of the n- and p-channel transistors, 4 r= 8 n/.8 p, will be decreased. Therefore, the ratio between the gain constants is adjusted according to the logic threshold voltage drop caused by temperature increase. This causes an increase in logic threshold voltage and, hence, compensation for temperature variation is accomplished.

Preferably,said temperature detection means of the CMOS buffer circuit of this invention comprises a plurality of temperature sensing means consisting of a current supply means and a polycrystalline silicon resistance means interconnected in series between the first power supply line and the second power supply line. Each of said temperature sensing means outputs different electrical output signals in response to the surrounding temperature of the polycrystalline silicon resistance means.

The resistance of polycrystalline silicon which is either not doped, or is lightly doped with impurity, is not only very large, but is alsogreatly changed according to temperature change.

Furthermore, the drain current in the subthreshold region of the MOS transistor is exponentially decreased when the gate voltage is lowered below the threshold voltage. Therefore, this device, which can detect the temperature of the semiconductor by using the subthreshold current of the MOS transistor and the resistance-temperature characteristics of polycrystalline silicon, has very little power consumption, and is thus very suited to very-largescale semiconductor devices.

The electrical output signal from each temperature sensing means of the temperature detection means is preferably converted into a digital signal through a digital conversion means, e.g., an inverter unit.

A current setting means is preferably added to said temperature detection means to set the drain current in the subthreshold region of the MOS transistor. The said current setting means may comprise a first MOS transistor of a first conduction and exponentially 1 6 type which has a first current electrode connected to the first power supply line, a control electrode connected to the second power supply line, and a second current electrode connected to a first node; a second MOS transistor of a second conduction type which has a first current electrode and a control electrode connected to the said first node, and a second current electrode connected to the second power supply line, and which has a sufficiently large geometric size in comparison with the geometric size of the first MOS transistor to allow it to be operated in the subthreshold region; a third MOS transistor of a second conduction type which has a control electrode connected to the control electrode of the said second MOS transistor, a first current electrode connected to said second power supply line and a second current electrode connected to a second node, and which has a sufficiently small geometric size in comparison with the geometric size of said second MOS transistor; and a fourth MOS transistor of a first conduction type which has a first current electrode connected to the first power supply line, and a control electrode and a second current electrode together connected to the said second node, and which has a sufficiently large geometric size in comparison with the geometric size of the said third MOS transistor to allow it to be operated in the subthreshold region, said 7 control electrode being connected to the control electrode of the MOS transistor of said current supply means.

The setting of the drain current of the MOS transistor of the current supply means i.s defined only by the drain current value of the first MOS transistor of the current setting means and by the ratio -between the geometrical sizes of the above-mentioned MOS transistors. Hence, the current of the current supply means has a value independent of the process and temperature change. Said temperature detection means has different supply current values, since each MOS transistor making up the current supply device has a different geometrical size. Therefore, the different electrical output signals, corresponding to any given surrounding temperature, can be obtained by the palycrystalline silicon resistance means which has an resistance value.

As an alternative to the above, the different electrical output signals corresponding to any given surrounding temperature can be obtained by making the resistance value of each polycrystalline silicon resistance different in the case of equivalent supply current.

Further, this invention can be modified as follows.

The first modification of this invention comprises at least one combination of a MOS transistor and switching -means which are interconnected in series between the second power supply line and the common connection point, to vary 8 the above-mentioned gain constant value according to the temperature; wherein said MOS transistor and switching means are the second conduction type transistors.

Therefore, if the temperature is lowered, the switching means will be turned on at a specific temperature and the gain constant value of the second conduction type MOS transistor will be increased. If, for example, the second conduction type is n-channel, the gain constant 13 n will be increased and the ratio between gain constants, a r= 9 n/ G P, will also be increased. The logic threshold voltage becomes low as the ratio between gain constants increase. Thus temperature compensation is accomplished. Another modification of this invention comprises at least one combination of MOS transistor and switching means interconnected in series between the first power supply line and the common connection point to vary the above-mentioned gain constant value according to temperature, and least one combination of.MOS transistor and switching means interconnected in series between the second power supply line and the same common connection point.

Here, the temperature compensation of the logic threshold voltage is accomplished by turning on the former switching means, when the temperature rises, to decrease the ratio between transistor gain constants, and by turning on the latter switching means, when the temperature falls, to - 9 increase the ratio of transistor gain constants..

Brief Description of the Drawinqs

The invention, together with its object and the advantages thereof, may best be understood by reference to the detailed description of exemplary embodiments taken in conjunction with the accompanying drawings in which:

Figure 1 illustrates a conventional CMOS input buffer circuit.

Figure 2 is a graph showing the relationship between logic threshold voltage characteristics and temperature changes for a conventional CMOS input buffer.

Figure 3 illustrates an embodiment of the CMOS input buffer circuit in accordance with the present invention.

Figure 4 is a circuit diagram of an example of the temperature detection means of the CMOS input buffer circuit shown in Figure 3.

Figure 5 is a graphical illustration of voltage characteristics of logic threshold as against the temperature changes for the CMOS input buffer circuit shown in Figure 3.

Figure 6 illustrates another embodiment of the CMOS input buffer circuit in accordance with the present invention.

Figure 7 illustrates further another embodiment of the CMOS input buffer circuit in accordance with the present invention.

In figure 1, a first MOS transistor M1 of a first conduction type (here, p-channel) and a second MOS transistor M2 of a second conduction type (here, nchannel) are interconnected in series between the first power supply line 1, e.g., the Vcc voltage supply line, and the second power supply line 2, e.g., the Vss voltage supply line. Input voltage of TTL voltage level is applied to their gate electrodes, and output voltage of CMOS voltage level corresponding to the said input voltage is delivered to their drain common connection point. Here, the logic threshold voltage V inv is Vnn + Vtp + Vtn.F ( n p n p V inv (V in= V cut ) = - - - - - - 1 +.F ( where Vnn = Vcc + Vss: Supply voltage, VtP = threshold voltage for p-channel MOS element, Vtn = threshold voltage for n-channel MOS element, 9 P = gain constant for n-channel MOS element, 13 n = gain constant for n-channel MOS element, 11 The above-mentioned gain constant ratio, 4 r=4 n/,e p, is independent of the temperature, but is dependent on the size of the element. Thus, the logic threshold voltage value according to temperature change is dependent on the threshold voltages of the elements, Vtp and Vtn, and is lowered if the temperature is raised, and vice versa.

Therefore, Low input characteristics go bad at high temperatures and High input characteristics go bad at low temperatures.

Figure 3 is a circuit diagram of a preferred embodiment of this invention. Figure 3 is the same as Figure 1, except for the serial connection of the third p-channel MOS transistor M3 with the fourth P-channel MOS transistor M4 and the serial connection of the fifth P-channel MOS transistor M5 with the sixth P-channel MOS transistor M6 between the Vcc supply line 1 and the common connection point 3, and the connection of gates of said fourth and sixth MOS transistors M4, M6 to the output terminals T1, T2 of the temperature detection means 10.

Therefore, in this embodiment, the temperature compensation of the logic threshold voltage is achieved by varying the overall gain constant.8 p of the p-channel device, since the fourth and sixth MOS transistors M4, M6 are switched according to the combination of output conditions for the output terminals TI and T2 of the temperature detection means 10.

12 Figure 4 is circuit diagram for said temperature detection means. In figure 4, the first and second current supply means 11,13 consist of P-channel MOS transistors Mil, M12 which are operated in the subthreshold region.

the source is connected to the first power supply line 1, the drain to the third node N3, and the gate to the current setting means 15. The first terminal of the polycrystalline silicon resistance means 12 is connected to third node N3, and the other terminal is connected to the second power supply line 2.

For the P-channel MOS transistor M12, the source is connected to the first power supply line 1, the drain to the fourth node N4, and the gate to the current set-ting means 15. The first terminal of the polycrystalline silicon resistance means 14 is connected to the fourth node N4, and the other terminal is connected to the second power supply line 2.

The above-mentioned current setting means 15 consists of four Mos transistors. For the first p-channel MOS transistor M7, the source is connected to the first power supply line 1, the gate to the second power supply line 2,_ the drain to the first node N1, and the drain current IN is applied to said first node N1. For the second nchannel MOS transistor M8, both the drain and the gate are For the p-channel MOS transistor M11, 13 connected to said first node N1, and the source is connected to the second power supply line 2. Here,in order to operate subthreshold its source is and its drain the second MOS transistor Ma in the region, the ratio between the geometric sizes of the first and the second MOS transistor is made so that W7< W8 (L7=L8).

In order that the third n-channel MOS transistor M9 has the same gate bias voltage as that of the second MOS transistor MS, its gate is connected to the first node N1, connected to the second power supply line 2, is connected to the second node N2. Therefore, the third MOS transistor M9 will be operated in the subthreshold region, regardless of its channel width. The drain current ID3 of the third MOS transistor M9 is W9 W8 ID3 = ID1 - - (for W9< W8,Lg = L8) For the fourth p-channel MOS transistor M10, both the gate and the drain are connected to the said second node N2, and the source is connected to the first power supply line 1. Here, in order to operate the fourth MOS transistor M10 in the subthreshold region, the ratio between the geometric sizes of the third and the fourth MOS transistors M9, M10 are made so that W9( WlO(L9=LIO).

The gates of the fifth and the sixth p-channel MOS transistors, M11, M12 constituting said current supply - 14 means, are connected to the second node N2. Therefore, the fifth and sixth P-channel MOS transistors M11, M12 will have the same gate voltage as that of the fourth MOS transistor M10 and will be operated in the subthresold region. Here, the ratio of the geometric sizes between the fourth and fifth MOS transistors M101 M11 is made so that W10) W11(L1O=L11). Hence the drain current ID5 of the fifth MOS transistor will become W11 ID5 = ID1 - - - - - W10 W9 we where ID1: the drain current of the first MOS transistor W8- W11: the channel width of each MOS transistor Moreover, the ratio between the geometric sizes of the fourth and the sixth MOS transistors M10, M12 is made so that W10 W12 (L10=L12). Hence the drain current ID6 of the sixth MOS transistor will become W9 W12 ID6 = ID1 W8 W10 In addition, both the third node N3, which is the connection point for the fifth MOS transistor M11 and the first polycrystalline silicon resistance means 12, and the fourth node N4, which is the connection point for the Z sixth MOS transistor M12 and the second polycrystalline silicon resistance means 14, are connected to the output terminals T1, T2 via the digital conversion means 16, 17 respectively. Here, the digital conversion means 16, 17 consist of, for example, the two-stage cascaded inverters IN1, IN2 and IN3, IN4. The drain currents of the fifth and the sixth Mos transistor M11, M12 are determined by the following inequality, i.e., ID5 < ID6 (W11 < W12) Therefore, if the first and the second Polycrystalline silicon resistance means 12, 14 are formed to have the same resistance values, the node voltages VN3, VN4 at the third and fourth nodes will become VN3 (T) = ID5 X RT1 (T) VN4 (T) = ID6 X RT2 (T) where RT1 is resistance of the first polycrystalline silicon at T K and RT2 is resistance of the second polycrystalline silicon at T K.

Since ID5 ( ID6 at the same temperature (T K), VN3(T)( VN4 (T) will result.

For example, if the node voltage VN3 is set to reach the trip voltage of the first inverter means IN1 at 293 K (20C), and the node voltage VN4 is set to reach the trip 16 voltage of the third inverter device IN3 at 323 K (501C), the output conditions at their respective output terminals 11,12 are changed as shown in < Table 1>- ( Table l>

R 1 \ Temperature( K) 1 i i 1 \ - - - - - - - -- 263- 2931 293- 3231 323355 1 Output Terminal 1 1 1 ---------- ---------------- T1 1 HIGH j LOW 1 LOW -------------------------- T2 1 HIGH HIGH LOW L - - - - - - - - - The change in the ratio between gain constants, 4 r, vs, the temperature change in the circuit of Figure 3, is listed in < Table 2>.

< Table 2

K - - - - - - - - - -- T- -- -- _r - - - - -T- - 1 \ Temperature(o K) 1 1 1 1 263- 2931 293- 3231 1 1 1 1 1 1 -- - - - - - 1.8 p 1 Ja 1 1e 1 + 6 3 j 8 1 +.8 3 +,6 5 1 -- - - - - - - - - - - - - - - - - - - - - - - - - - - 1 i i L - 6 r = e n fi p i 323-355 ----------------- OFF i ON 1 ON --------------------- 1 OFF 1 OFF- 1 ON M4 M6 1 1 1 Large Medium Small -----L-----L----A- - As is indicated in the dotted line in Figure 5, the logic threshold value is lowered as the temperature is raised, but the ratio between the gain constants of the transistors 17 - becomes 8 r (above 323 K) n 1 +.,8 3 + 6 5 and is decreased. Hence the logic threshold voltage is compensated as indicated in the solid line in Figure 5. Thus deterioration in low-input level characteristics according to the temperature increase is prevented.

In the same manner, if the temperature is lowered, the logic threshold value is increased as indicated in dotted line in Figure 5, but the ratio between the gain constants of the transistors is increased to 6 n 13 r (below 293 K) = and the logic threshold voltage will be compensated as indicated in the solid line in Figure 5. Thus, deterioration in high input level characteristics according to the temperature decrease will be prevented.

Figure 6 shows a modified example of this invention. In Figure 6, both the serially connected third n-channel MOS transistor M13 and fourth nchannel MOS transistor M14, and the serially connected fifth and sixth nchannel MOS transistors M15, M16 are connected between the Vss supply line 2 and the common connection point 3 as shown in Figure 1. The gates of the third and fifth MOS transistors M13, 18 - M15 are connected to the output terminals T1, T2 of the temperature detection means 10 as shown in Figure 4, respectively. The change in the gain constants ratio 6 r vs the temperature change in the circuit of Figure 6 is shown in ( Table 3).

( Table 3) - - - - - - - - - - T- Temperature(' K)l 1 M13 1 M15 263- 293 1 293- 3231 323- 3551 1 1 1 --------------- ON 1 OFF 1 OFF 1 1 ON 1 ON 1 OFF ---------------------- 1.8 2+.8 14+ig 16 1 8 2+,6 161 6 2 1 n r L - - - - - - - - - L - - - - - - - - L - - - - 4 n - Large 13 p 1 1 1 Medium Small Therefore, the ratio between the gain constants of the transistors will become 4 r (above 323 K) =.8 2/,6 P, as the temperature is increased, and will become 4 r (below 293 K) = (6 2 + 8 14 + 13 16)/,6 p, as the temperature is lowered. Hence the temperature characteristics of the logic threshold voltage in Figure 5 can be obtained.

Figure 7 shows another modified example of this invention. Figure 7 is the same as Figure 1, except that the serially connected third and fourth p-channel MOS transistors M17, M18 are connected between the Vcc supply 19 line 1 and the common connection paint 3, and the serially connected fifth and sixth n-channel MOS transistors M19, M20 are connected between the Vss supply line 2 and the common connection point 3. The gates of said fourth p-channel and fifth n-channel transistors M18, M19 are respectively connected to the output terminal T2, T1 of the temperature detection means 10 as shown in Figure 4. The change in the in the gain constant ratio 13 r vs the temperature change circuit of Figure 7 is shown in ( Table 45.

( Table 4)

N - - - - - - - - 1 \ Temperature(' K) p n n r p M18 M19 263- 293 - - - - - - - - 1 - - - - - - 293- 3231 1 1 323- 355 OFF OFF ON ---------------ON 1 OFF 1 OFF --------------- J9 1 1 a 1 1 fi 1 + 8 17 ------------------- 4 2+4 20 1 6 2 1 6 2 1 ---------------- 1 1 1 Large Medium Small L Therefore, the ratio ig r of the gain constants of the 8 2 transistors will decrease to.8 r (above 323 K) = 6 1+,6 17 as the temperature is increased, and will increase to 4 r (below 293 K) e 2 + 6 2 0 16 1 as the temperature is - 20 decreased. Hence the temperature characteristics of the logic threshold voltage as shown in figure 5 can be obtained.

As discussed above, in this invention, by increasing the ratio between element sizes, i.e., the ratio of the gain constants of the transistors in the low temperature region, to suppress increase of the logic threshold voltage level and by decreasing the ratio between the gain constants of the transistors in the high temperature region, to suppress decrease of the logic threshold voltage level, the input level characteristics of the CMOS input buffer circuit vs temperature change can be stabilized.

So far, although the present invention was described by examples having two temperature-compensation points, further examples having more then two temperature-compensation points will be readily practised within the scope of this invention as defined in the accompanying claims, by any person having ordinary skill in the art to which this invention pertains.

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Claims

Claims:

A CMOS input buffer circuit comprising; a first MOS transistor of a first conduction type and a second MOS transistor of a second conduction type which are interconnected in series between a first power supply and a second power supply line, and to the control electrodes of which is applied in parallel input voltage of a TTL voltage level, and to the common connection point of drains of which is supplied output voltage of a CMOS voltage level in correspondence to said input voltage; at least one combination of a MOS transistor of a first conduction type and a switching means which are interconnected in series between said first power supply line and said common connection point, the control electrode of the MOS transistor being coupled to said input voltage, and said switching means being turned on above a certain predetermined temperature and turned off below it; a temperature detection means having at least one output terminal connected to the control signal input terminal of said at least one switching means in order to control the same in accordance with temperature changes; whereby the overall gain constant value of the transistor for each of said transistors of a first conduction type is decreased at low temperature and increased at high temperature, and thus variation in logic threshold voltage is stabilized in accordance with 22 temperature.
2. The CMOS input buffer circuit as claimed in claim 1, wherein each of said transistors of first conduction type is a p-channel MOS transistor and said transistor of second conduction type is an n-channel MOS transistor and said switching means is a p-channel MOS transistor.
3. The CMOS input buffer circuit as claimed in claim 2, wherein said temperature detection means comprises a plurality of temperature sensing means consisting of a current supply means and a polycrystalline silicon resistance means interconnected in series between the first power supply line and the second power supply line, each of said temperature sensing means outputting a different electrical output signal in response to the surrounding temperature of the polycrystalline silicon resistance means.
4. The CMOS input buffer circuit as claimed in claim 31 wherein said temperature detection means further comprises digital conversion means which convert the electrical output signal of said temperature sensing means into digital form.
5. The CMOS 2 input buffer circuit as claimed in claim 4, wherein said digital conversion means comprises two-stage cascaded inverters, the input terminal of the first-stage inverter being connected to the common connection point of the current supply means and a 23 - polycrystalline silicon resistance means, and the output terminal of the second inverter being connected to the control signal input terminal of said switching means.
6. The CMOS input buffer circuit as claimed in any one of claims ' 3 to 5 wherein said polycrystalline silicon resistance means is not doped, or is lightly doped with impurity.
7. The CMOS input buffer circuit as claimed in claim 6, wherein said current supply means comprise transistors which are operated in the subthreshold region.
8. The CMOS input buffer circuit as claimed in claim 7, wherein said temperature detection means further comprises a current setting means for setting the drain current of the MOS transistor of the said current supply means.
9. The CMOS input buffer circuit as claimed in claim 8, wherein said current setting means comprises:

a first MOS transistor of a first conduction type which has a first current electrode connected to the first power supply line, a control electrode connected to the second power supply line, and a second current electrode connected to a first node; a second MOS transistor of a second conduction type which has a first current electrode and a control electrode connected to the said first node, and a second current electrode connected to the second power supply line, 24 and which has a sufficiently large geometric size in comparison with the geometric size of the first MOS transistor to allow it to be operated in the subthreshold region; a third MOS transistor of a second conduction type which has a control electrode connected to the control electrode of the said second MOS transistor, a first current electrode connected to the said second power supply line and a second current electrode connected to a second node, and which has a sufficiently small geometric size in comparison with the geometric size of said second MOS transistor; and a fourth MOS transistor of a first conduction type which has a first current electrode connected to the first power supply line, and a control electrode and a second current electrode together connected to the said second node, and which has a sufficiently large geom-tric size in comparison with the geometric size of the said third MOS transistor to allow it to be operated in the subthreshold region, said control electrode being connected to the control electrdde of the MOS transistor of said current supply means.
10. The CMOS input buffer circuit as claimed in claim 9, wherein each of the MOS transistors of said current supply means for said temperature sensing means is constituted so as to have different geometric size in order that each of said temperature sensing means generates different electrical signals in response to with the surrounding temperature of the polycrystalline silicon resistance means.
11. The CMOS input buffer circuit as claimed in claim 10, wherein each of the polycrystalline silicon' resistance means of said temperature sensing means is constituted so as to have different resistance values in order that each of said temperature sensing means generates different electrical signals in response to the surrounding temperature of the polycrystalline silicon resistance means.
12. A CMOS input buffer circuit comprising:

a first MOS transistor of a first conduction type and a second MOS transistor of a second conduction type which are interconnected in series between a first power supply line and a second power supply line, and to the control electrodes of which is applied in parallel input voltage ofa M voltage level, and to the common connection point of drains of which is supplied output voltage of a CMOS voltage level in correspondence to said input voltage; at least one combination of a MOS transistor of a second conduction type and a switching means which are interconnected in series between said second power supply line and said common connection point, the control electrode of the MOS transistor being coupled to said input 'voltage, and said switching means being turned off above a certain 26 predetermined temperature and turned on below it: a temperature detection means having at output terminal connected to the control signal input terminal.,of said at least one switching means to least one control the same in accordance with temperature changes; whereby the overall gain constant value of the transistor for each of said transistors of the second conduction type is decreased at high temperature and increased at low temperature, and thus variation in logic threshold voltage is stabilized in accordance with temperature.
13. The CMOS input buffer circuit as claimed in claim 12, wherein said transistor of first conduction type is a pchannel MOS transistor and each of the transistors of second conduction type is an n-channel MOS transistor and said switching means is an n-channel MOS transistor.
14. The CMOS input buffer circuit as claimed in claim 13, wherein said temperature detection means comprises a plurality of temperature sensing means having a current supply means and a polycrystalline silicon resistance means interconnected between the first power supply line and the second power supply line, said temperature sensing means generating different electrical signals in response to the surrounding temperature of the polycrystalline silicon resistance means.

27
15. The CMOS input buffer circuit as claimed in claim 14, wherein said temperature detection means further comprises a digital conversion means which converts the electrical output signal Of the temperature sensing means into digital form.
16. The CMOS input buffer circuit as claimed in claim 15, wherein said digital conversion device comprises twostage cascaded inverters, the input terminal of the firststage inverter being connected to the common connection point for the said current supply means and the polycrystalline silicon resistance means, and the output terminal of the second inverter being connected to the control signal input terminal of the said switching means.
17. The CMOS input buffer circuit as claimed in any one of claims 14 to 16, wherein said polycrystalline silicon resistance means is not doped or is lightly doped with impurity.
18. The CMOS input buffer circuit as claimed in claim 17, wherein each of the current supply means consists of MOS transistor which is operated in the subthreshold region.
19. The CMOS input buffer circuit as claimed in claim 18, wherein the said temperature detection means further comprises a current setting means for setting the drain current of the MOS transistor of the said current supply means.
20. The CMOS input buffer circuit as claimed in claim 28 19, wherein said current setting means comprises; a first MOS transistor of a first conduction type which has a first current electrode connected to the first power supply line, a control electrode connected to the second power supply line, and a second current electrode connected to a first node; a second MOS transistor of a second conduction type which has a first current electrode connected to said first node and a second current electrode connected to the second power supply line, and which has a sufficiently large geometric size in comparison with the geometric size of said first MOS transistor to allow it to be operated in the subthreshold region; a third MOS transistor of the second conduction type which has a control electrode connected to the control electrode of said second MOS transistor, a first current electrode connected to the second power supply line and a second current electrode connected to a second node, and which has a sufficiently small geometric size in comparison with the geometric size of said second MOS transistor; and a fourth MOS transistor of a first conduction type which has a first current electrode connected to the first power supply line, and a control electrode and a second current electrode commonly connected to a said second node, and which has a sufficiently large geometric size in 1 i 29 comparison with the geometric size of a said third MOS transistor to allow it to be operated in the subthreshold region, the said control electrode being commonly connected to the control electrode of the MOS transistor of the said current supply means.
21. The CMOS input buffer circuit as claimed in claim 20, wherein each MOS transistor of said current supply means for said temperature sensing means is constituted so as to have different geometric size in order that said temperature sensing means generates different electrical signals in response to the surrounding temperature of the polycrystalline silicon resistance means.
22. The CMOS input buffer circuit as claimed in claim 21, wherein each polycrystalline silicon resistance means of said temperature sensing means is constituted so as to have different resistance values in order that said temperature sensing means generates different electrical signals in response to the surrounding temperature of the polycrystalline silicon resistance means.
23. A CMOS input buffer circuit comprising:

a first MOS transistor of a first conduction type and a second MOS transistor of a second conduction type which are interconnected in series between a first power supply line and a second power supply line, and to the control electrodes of which is applied in parallel input voltage of a TTL voltage level, and to the common connection point of drains of which is supplied output voltage of a CMOS voltage level in correspondence to said input voltage; at least one combination of a MOS transistor of a first conduction type and a first. switching means interconnected in series between the said first power supply line and the common connection point, the control electrode of the said MOS transistor being connected to the input voltage and said first switching means being turned on above a certain temperature and turned off below it; at least one combination of a MOS transistor of a second conduction type and a second switching means interconnected in series between the second power supply line and said common connection point, the control electrode of said MOS transistor being connected to the input voltage, and said second switching means being turned off above a certain temperature and turned on below it; a temperature detection means which has a plurality of output terminals connected to the control signal input terminals of the first switching means and the second switching means; whereby the overall gain constant value for said transistors of the first conduction type increase at high temperature and the overall gain constant value for saidtransistors of the second conduction type decrease at low temperature so that the variation in logic threshold 1 31 voltages can be stabilized.
24. The CMOS input buffer circuit as claimed in claim 23, wherein the said first switching means is a first conduction type MOS transistor and said second switching means is a second conduction type MOS transistor; and the said first conduction type transistors are P-channel MOS transistors and the said second conduction type transistors are n-channel MOS transistors.
25. The CMOS input buffer circuit as claimed in claim 24, wherein said temperature detection means comprises a plurality of temperature sensing means which has current supply means and a-polycrystalline silicon resistance means interconnected in series between the first power supply line and the second power supply line, each of said temperature sensing means generating different electrical output signals in response to the surrounding temperature of the polycrystalline silicon resistance means.
26. The CMOS input buffer input buffer circuit as claimed in claim 25, wherein said temperature detection means further comprises a plurality of digital conversion means which converts the electrical output signal of the said temperature sensing means into digital form.
27. The CMOS input buffer circuit as claimed in claim 26, wherein each of said digital conversion means comprises a twc-stage cascaded inverter, the input terminal of the firststage inverter being connected to the common connection 1 32 point for said current supply means and the polycrystalline silicon resistance means, and the output terminal of the second inverter being connected to the control signal input terminal of said switching means.
28. The CMOS input buffer circuit as claimed in any one of claims 25 to 27, wherein the said polycrystalline silicon resistance means is not doped, or is lightly doped with impurity.
29. The CMOS input buffer circuit as claimed in claim 28, wherein each of said current supply means comprises a MOS transistor which is operated in the subthreshold region.
30. The CMOS input buffer circuit as claimed in claim 29, wherein the said temperature detection means further comprises a current setting means for setting the drain current of the MOS transistor of the said current supply means.
31. The CMOS input buffer circuit as claimed in claim 30, wherein said current setting means comprises:

a first MOS transistor of a first conduction type which has a control electrode connected to the first power supply line, and a second current electrode connected to a first node; a second MOS transistor of a second conduction type which has a first current electrode connected to the first node and a second current electrode connected to the 33 - second power supply line, and which has a sufficiently large geometric size in comparison with the geometric size of the first MOS transistor to allow it to be operated in the subthreshold region; a third MOS transistor of a second conductance type which has a control electrode connected to the control electrode of said MOS transistor, a first current electrode connected to the second power supply line and a second current electrode connected to a second node, and which has a sufficiently small geometric size in comparison with the geometric size of said second MOS transistor; and a fourth MOS transistor of a first conduction type which has a first current electrode connected to the first power supply line, and a control electrode and a second current electrode connected to the said second node, and which has a sufficiently large geometric size in comparison with the geometric size of the third MOS transistor to allow it to be operated in the subthreshold region, the said control electrode being connected to the control electrode of the MOS transistor of the said current supply means.
32. The CMOS input buffer circuit as claimed in claim 31, wherein each MOS transistor of the current supply means for said temperature sensing means has a different geometrical size in order that the said temperature sensing 1 1 -34means can generate different electrical output signals in response to the surrounding temperatures of the polycrystalline silicon resistance means.
33. The CMOS input buffer circuit as claimed in claim 31 or 32, wherein each polycrystalline silicon resistance means has a different resistance value in order that said temperature sensing means can generate different electrical output signals in response to the surrounding temperatures of the polycrystalline silicon resistance means.
34. CMOS input buffer circuits substantially as hereinbefore described with reference to Figs. 3 to 7 of the accompanying drawings.

Published 1990 at The Patent Office. State House. 66 71 High HoIborn. LondcnI%TClR4TP Further copies maybe obtainedfrom The Patent Office Sales Branch, St Mary Cray, Orpington. Kent BR5 3RD. Printed by Multiplex techniques ltd, St Mary Cray. Kent, Con. 1/87