JPH07113862B2 - Reference voltage generation circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generating circuit for supplying a stabilized constant reference output voltage in a semiconductor memory device or the like.

(Prior Art) Conventionally, as a technology in such a field, there is, for example, one as shown in FIG. 2 and FIG. The configuration will be described below.

FIG. 2 is a circuit diagram showing a configuration example of a conventional reference voltage generating circuit.

This reference voltage generation circuit is a circuit that generates a standard output voltage of 1/2 of the power supply voltage VCC, and a reference voltage generation unit 1 that outputs the standard voltage Vr, and a voltage of 1/2 · VCC based on the reference voltage Vr. The driving unit 10 outputs a stabilized constant reference output voltage Vo.

The reference voltage generator 1 has a resistance element 2 having one end connected to the power supply voltage VCC and the other end connected to a node N1, and the MOS transistors 3 and 4 and the resistance element 5 are connected in series between the node N1 and the ground potential. It is connected to the. Further, the driving unit 10 has a MOS transistor 11 whose drain is connected to the power supply voltage VCC and whose gate is connected to the node N1, respectively, and the source of the MOS transistor 11 is connected to the output terminal 12 for outputting the reference output voltage Vo,
Further, a load MOS is provided between the output terminal 12 and the ground potential.
Transis evening 13 is connected.

In the above configuration, the reference voltage generator 1 supplies the power supply voltage VC
The reference voltage Vr (= 1/2) is obtained by stepping down C with the resistance element 2 and adding the threshold voltage Vt of the MOS transistors 3 and 4 to 1/2 of the power supply voltage VCC.
・ VCC + Vt) is output from node N1. Then, the reference voltage Vr controls the amount of current between the drain and source of the MOS transistor 11 in the driving unit 10, and the reference output voltage of 1/2 VCC
Vo is output from the output terminal 12 and supplied to a load such as a semiconductor memory.

For example, the reference output voltage Vo is 1/2 VCC due to load fluctuations.
When the voltage is lower than that by α, the drain of the MOS transistor 11 becomes VCC, its gate becomes (1/2 · VCC + Vt), and its source becomes (1/2 · VCC−α), and it is turned on. When this MOS transistor 11 is turned on, the output terminal 12 is charged from the power supply voltage VCC side, and the output terminal 1
The reference output voltage Vo of 2 rises to 1/2 · VCC. When the reference output voltage Vo becomes higher than 1/2 · VCC by voltage α, the drain of the MOS transistor 11 is VCC, its gate is (1/2 · VCC + Vt), and its source is (1/2 · VCC + α). ) Voltage, and it is turned off. Therefore, the MOS transistor 13 lowers the reference output voltage Vo of the output terminal 12 and the voltage Vo becomes 1/2 · VCC. In the reference voltage generating circuit of FIG. 2, the final voltage of the output terminal 12 is the ON resistance when the MOS transistor 11 is in the weak ON state and the MOS transistor 1
The on-resistance of 3 is determined at the balanced point.

FIG. 3 is a circuit diagram of another conventional reference voltage generating circuit.

This reference voltage generation circuit consists of a reference voltage generation unit 20 that generates a reference voltage Vr of 1 / 2.VCC, and a 1/2 based on the reference voltage Vr.
The drive unit 30 that outputs a constant reference output voltage Vo that stabilizes VCC. In the reference voltage generator 20,
The resistance elements 21 and 22 are connected in series between the power supply voltage VCC and the ground potential, and the reference voltage Vr of 1/2 · VCC is output from the node N2 which is the connection point of the resistance elements 21 and 22. The drive unit 30 has a differential amplifier 31, an output terminal 32 of the differential amplifier 31 is connected to a (−) side input terminal, and a (+) side input terminal thereof is connected to a node N2. This differential amplifier 31 has a voltage follower configuration, and ignoring its offset voltage, a reference output voltage Vo having a voltage equal to the reference voltage Vr of 1/2 · VCC input to the (+) side input terminal is output terminal 32. Is output from. In this way, the drive unit 30 outputs the reference output voltage Vo by using the voltage follower output, thereby enhancing the drive capability of the output terminal 32.

(Problems to be Solved by the Invention) However, the reference voltage generating circuit configured as described above has the following problems.

In the circuit of FIG. 2, the reference voltage generator 1 is connected to the resistance elements 2, 5 and M
Since it is composed of OS transistors 3 and 4, the balance between the ON resistance of MOS transistors 3 and 4 and the value of resistance elements 2 and 5, MO
Processes such as substrate effect coefficient of S-transistors 3 and 4
The reference voltage Vr output from the node N1 fluctuates due to the fluctuation (variation) of the parameter, which causes the output terminal 12
The final voltage of will also change. In addition, even during standby when the value of the reference output voltage Vo is within the set range, the drive unit 10
Power consumption increases because the standby current flows from the power supply voltage VCC side to the ground potential side. In order to reduce the power consumption, the dimensions (size) of the MOS transistors 11 and 13 may be reduced to reduce the standby current.
If you reduce the dimensions of S-transistors 11 and 13,
The drive capability of the output terminal 12 becomes small, which causes a problem of speed delay in the case of a large capacity load.

In the circuit of FIG. 3, the reference voltage generator 20 is connected to the resistance element 2
Since it is composed of only 1,22, the fluctuation of the reference output voltage Vo due to the process parameter is small, but when the standby current flows through the driving unit 30 and it is attempted to reduce it, the driving capability becomes small and the second Similar to the figure, there is a problem that a speed delay occurs when a large capacity load is applied.

Thus, none of the conventional circuits has been technically satisfactory.

The present invention has, as a problem that the above-mentioned conventional technology has, a change in the reference output voltage due to a change in process parameters,
The present invention provides a reference voltage generation circuit that solves the problems of standby current and low drive capacity.

(Means for Solving Problems) In order to solve the above problems, the present invention provides a reference voltage generating unit, a comparing unit, and a driving unit in a standard voltage generating circuit that outputs a stable and constant output voltage. It has and.

Here, the reference voltage generating unit includes a voltage dividing resistor having first and second nodes, and the first reference voltage defined by the voltage dividing resistor is applied to the first node at the second reference voltage. A second reference voltage, which is defined by the voltage dividing resistor and is different from the first reference voltage, is applied to each node. The comparing section compares the first and second reference voltages given from the first and second nodes with the output voltage outputted from the output node by the first and second comparing means, and compares them. A corresponding control signal is output from the first and second comparing means. Further, the driving unit includes a switch connected between the first potential supply node to which the first voltage is supplied and the second potential supply node to which the second potential is supplied and which is controlled by the control signal. The output voltage is output to the output node.

(Operation) According to the present invention, since the standard voltage generating circuit is configured as described above, the reference voltage generating section uses the voltage dividing resistor to stabilize the stable first and second standard parameters. The voltage is output from the first and second nodes. The first and second comparing means of the comparing section compare the first and second reference voltages from the reference voltage generating section with the output voltage on the output node output from the driving section, and respond to them. The control signal controls ON / OFF of the switch in the drive unit. The drive unit operates so that the switch constituting the drive unit is turned off in the standby state to cut off the through current between the first potential supply node and the second potential supply node, and the dimension of the switch is increased. As a result, the driving ability when driving the load is improved. Therefore, the above problems can be eliminated.

(Embodiment) FIG. 1 is a configuration block diagram of a reference voltage generating circuit showing an embodiment of the present invention.

This reference voltage generation circuit compares a reference voltage generation unit 40 that generates at least two first and second reference voltages Vr1 and Vr2 with at least two reference voltages Vr1 and Vr2 and a reference output voltage Vo. The comparison unit 50 outputs the first and second control signals S1 and S2, and the drive unit 60 that outputs a stable and constant reference output voltage Vo based on the first and second control signals S1 and S2.
The reference output voltage Vo is output to the output terminal (output node) 70.

An example of the structure of this reference voltage generating circuit is shown in FIG.

In the standard voltage generating circuit of FIG. 4, the reference voltage generating unit 40
Has a resistance element 41 having a resistance value R1, a resistance element 42 having a resistance value r, and a resistance element 43 having a resistance value R2.
43 is a first potential supply node for supplying a first potential (eg, power supply voltage VCC) or a second potential (eg, ground potential)
Are connected in series between the second potential supply nodes which supply the voltage dividing circuit. The resistance elements 41 and 42 are connected to each other at the first node N10, and the resistance elements 42 and 43 are connected to each other at the second node N11.
1 outputs the second reference voltage Vr2 from the node N11.

The comparison unit 50 has first and second comparators 52 and 51 which are first and second comparison means, and the (−) of the second comparator 51.
The side input terminal is connected to the node N11, and the (−) side input terminal of the first comparator 52 is connected to the node N10. Further, the (+) side input terminals of the comparators 51 and 52 are commonly connected to the output terminal 70, and the control signals S1 and S2 are output from the output terminals of the comparators 51 and 52, respectively. There is.

Further, the driving unit 60 includes two switches connected in series, for example, a P-channel MOS transistor (hereinafter referred to as PMOS) 6
1 and N-channel MOS transistor (hereinafter referred to as NMOS) 62
The source of the PMOS 61 is connected to the power supply voltage VCC, the gate thereof is connected to the output terminal of the comparator 51, and the drain thereof is connected to the output terminal 70. In the NMOS 62, its drain is the output terminal 70, its gate is the output terminal of the comparator 52,
The sources are each connected to ground potential.

The operation of the reference voltage generating circuit configured as described above will be described with reference to FIG.

FIG. 5 is an operation explanatory diagram showing the relationship between the reference output voltage Vo and the internal state of the circuit.

As shown in FIG. 5, when the reference output voltage Vo is higher than the first reference voltage Vr1, the temporary state A is set, and the reference output voltage Vo is the same as that of the first and second reference voltages Vr1 and Vr2. The respective operations will be described assuming that the time is between them as the temporary state B and the time when the reference output voltage Vo is lower than the second reference voltage Vr2 as the temporary state C.

In the case of the temporary state A (Vo> Vr1), one comparator 51 compares the reference output voltage Vo fed back from the output terminal 70 with the second reference voltage Vr2, and since Vo> Vr2, it is at a high level. The control signal S1 (hereinafter referred to as "H") is output, and the PMOS
Give to the 61 gate. The other comparator 52 is the reference output voltage.
Vo is compared with the first reference voltage Vr1, and since Vo> Vr1, the control signal S2 of "H" is output and given to the gate of the NMOS 62.

Then, the PMOS 61 of the driving unit 60 is turned off and the NMOS 62 is turned on, so that the reference output voltage on the output terminal 70 is passed through the NMOS 62.
Vo drops.

In the case of the temporary state B (Vr1>Vo> Vr2), the control signal S1 output from one comparator 51 is “H” and the control signal S2 output from the other comparator 52 is at a low level (hereinafter, “L”). Therefore, both the PMOS 61 and the NMOS 62 of the drive unit 60 are turned off,
The output terminal 70 is in a high impedance state. for that reason,
No current flows through the drive unit 60.

In the case of the temporary state C (Vo <Vr2), the control signal S1 output from one comparator 51 is “L”, and the control signal S2 output from the other comparator 52 is “L”, so that the drive unit 60 PMOS 61 turns on, NMOS 62 turns off, and the power supply voltage VC passes through the PMOS 61.
The output terminal 70 side is charged from the C side, and the reference output voltage Vo rises.

As described above, the reference output voltage Vo on the output terminal 70 is equal to the first and second reference voltages Vr1 and Vr output from the reference voltage generator 40.
Determined by 2. Here, the first and second reference voltages Vr1, V
r2 is expressed by the following equation.

Each first term of the equations (1) and (2) is the reference output voltage Vo to be set, and each second term shows the variation range of the reference output voltage Vo. If R1 = R2, then (1), (2)
The formula is as follows.

As is clear from the equations (3) and (4), the reference output voltage Vo has a value of 1/2 · VCC.

Similarly, by changing the ratio of the resistance values R1 and R2, the above (1), (2)
Of expression If the value of is changed, the reference output voltage Vo of another value is output.
Can be output from. For example, when R1: R2 = 1: 2, Vo = 1/3 · VCC.

In this embodiment, since the reference voltage generator 40 is composed of the resistance voltage dividing circuit, it is possible to generate stable reference voltages Vr1 and Vr2 that do not depend on the fluctuation of the process parameters, and thereby prevent the fluctuation of the reference output voltage Vo. In addition, by changing the ratio of resistance values in the reference voltage generator 40, the standard output voltage
Vo value can be set freely. In addition, the PMOS in the drive unit 60
Since the 61 and the NMOS 62 are in the OFF state in the standby state and no current flows, the standby current is the reference voltage generation section 40 and the comparison section.
It is determined only by the current flowing through 50. Therefore, it is possible to increase the dimension of the drive unit 60 in accordance with the load to be driven by the reference voltage generation circuit, and thereby the speed can be increased several tens of times with the same power consumption as compared with the conventional circuit. It is confirmed.

The present invention is not limited to the illustrated embodiment. For example,
The circuit of the reference voltage generating unit 40 in FIG. 4 may be modified to another configuration, the number of comparators 51 and 52 in the comparing unit 50 may be set to three or more, and the number of transistors in the driving unit 60 may be changed accordingly. The number and connection structure may be changed to other ones. The driving unit 60 may be composed of transistors other than MOS transistors.

(Effect of the Invention) As described in detail above, according to the present invention, since the reference voltage generating unit is configured by the voltage dividing resistor, it is possible to prevent the fluctuation of the output voltage due to the fluctuation (variation) of the process parameter. Moreover, even if the process parameters vary, the switch in the drive unit is turned off during standby, so that the shoot-through current of the drive unit can be greatly reduced with a simple configuration. As a result, it is possible to increase the dimension of the switch in the drive unit, which can improve the drive capability.

[Brief description of drawings]

1 is a block diagram of a reference voltage generating circuit showing an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional reference voltage generating circuit, and FIG. 3 is a circuit diagram of another conventional reference voltage generating circuit. FIG. 4 is a circuit diagram showing the configuration example of FIG. 1, and FIG. 5 is an operation explanatory diagram of FIG. 40 …… Reference voltage generator, 41,42,43 …… Resistance element, 50 ……
Comparator, 51, 52 …… Comparator, 60 …… Drive unit, 61 …… PMO
S, 63 …… NMOS, 70 …… Output terminals, S1, S2 …… Control signals,
VCC: Power supply voltage, Vo: Reference output voltage, Vr1, Vr2: Reference voltage.

Claims (1)

[Claims] 1. A voltage dividing resistor having first and second nodes, wherein a first reference voltage defined by the voltage dividing resistor is applied to the first node and the voltage dividing resistor is applied to the second node. A reference voltage generator defined by a piezo-resistor and providing a second reference voltage different from the first reference voltage, and the first and second reference voltages and outputs provided from the first and second nodes. A first potential is supplied to a comparison unit that compares the output voltage output from the node with the first and second comparison units and outputs a connection signal corresponding to the output voltage from the first and second comparison units. Connected between a first potential supply node and a second potential supply node to which a second potential is supplied,
A reference voltage generating circuit comprising: a switch controlled by the control signal; and a driving unit that outputs the output voltage to the output node.