KR910009810B1

KR910009810B1 - Cmos input buffer circuit

Info

Publication number: KR910009810B1
Application number: KR1019890007106A
Authority: KR
Inventors: 정태성
Original assignee: 삼성전자 주식회사; 김광호
Priority date: 1989-05-27
Filing date: 1989-05-27
Publication date: 1991-11-30
Also published as: NL8902048A; NL190137B; KR900019380A; GB8918991D0; JPH0311823A; NL190137C; FR2647608B1; FR2647608A1; DE3926657C2; GB2232311A; GB2232311B; JP2651246B2; DE3926657A1

Abstract

a first conductivity MOS transistor which control electrode receiving the input votlage is connected between the first power supply line and the common connection point; switching means connected in series and turned ON when the temp. is greater than preset one and turned OFF at lower temp., and a temperature detecting means (10) having output terminals more than one and connected to the control signal input terminal of the switching means for controlling the switching means according to the variation of the temperature.

Description

CMOS input buffer circuit

제1도는 종래의 CMOS 입력 버퍼회로.1 is a conventional CMOS input buffer circuit.

제2도는 온도 변화에 따른 종래의 CMOS 입력 버퍼 회로의 로직 스레쉬 홀드전압 특성 그래프선도.2 is a graph illustrating a logic threshold hold voltage characteristic of a conventional CMOS input buffer circuit according to a temperature change.

제3도는 본 발명에 의한 일실시예의 회로도.3 is a circuit diagram of an embodiment according to the present invention.

제4도는 제3도의 온도 검출수단의 바람직한 일실시예의 회로도.4 is a circuit diagram of a preferred embodiment of the temperature detecting means of FIG.

제5도는 제3도의 온도에 따른 로직 스레쉬 홀드 전압 특성 그래프선도.5 is a graph of logic threshold hold voltage characteristics according to the temperature of FIG.

제6도는 본 발명에 의한 변형된 다른 실시예의 회로도.6 is a circuit diagram of another modified embodiment according to the present invention.

제7도는 본 발명에 의한 변형된 또다른 실시예의 회로도.7 is a circuit diagram of another modified embodiment according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

1 : 제1전원 공급선 2 : 제2전원 공급선1: first power supply line 2: second power supply line

3 : 공통접속점 10 : 온도 검출수단3: common connection point 10: temperature detection means

11, 13 : 전류 공급수단 12, 14 : 다결정 실리콘 저항수단11, 13 current supply means 12, 14 polycrystalline silicon resistance means

15 : 전류 설정수단 16, 17 : 디지털 변환 수단15: current setting means 16, 17: digital conversion means

M1∼M20 : MOS트랜지스터 IN1∼IN4 : 인버터M1 to M20: MOS transistor IN1 to IN4: Inverter

N1∼IN4 : 노드 T1, T2 : 온도 검출 수단의 출력단자N1 to IN4: nodes T1 and T2: output terminals of the temperature detecting means

본 발명은 CMOS 입력 버퍼회로에 관한 것으로, 특히 CMOS형, 초고집적 반도체 장치에 있어서, 온도 보상되는 로직 스레쉬 홀드 전압을 가지는 입력 버퍼 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS input buffer circuit, and more particularly to an input buffer circuit having a temperature threshold compensated logic threshold hold voltage in a CMOS type, ultra-high density semiconductor device.

반도체 장치의 고집적화, 미세화 및 고성능화등의 추세에 따라 소비전력이 증대되므로 온도에 따른 동작 특성에 대한 보다 세심한 고려가 요구되고 있다.As the power consumption increases according to the trend of high integration, miniaturization, and high performance of semiconductor devices, more careful consideration of operating characteristics according to temperature is required.

통상 CMOS 입력 버퍼 회로는 CMOS 인버터로 구성하고 그 입력단에 TTL 전압레벨을 가진 입력신호가 인가되고 그 출력단에 CMOS 전압레벨로 변환된 신호가 출력되도록 되어 있다. 그러나 CMOS 인버터는 그 로직 스레쉬 홀드전압이 온도에 따라 변동되는바, 저온에서 로직 스레쉬 홀드 전압레벨이 상승하게 되어 입력 하이레벨 특성이 나빠지게 되고 고온에서는 로직 스레쉬 홀드 전압레벨이 하강하게 되어 입력로우 레벨 특성이 나빠지게 된다. 그러므로 주변온도 변화에 따라 입력특성이 변화되게 되므로 동작이 불안정하게 되거나 동작속도가 지연되는 문제점이 발생된다.In general, a CMOS input buffer circuit is composed of a CMOS inverter, and an input signal having a TTL voltage level is applied to an input terminal thereof, and a signal converted to a CMOS voltage level is output to an output terminal thereof. However, in the case of CMOS inverter, the logic threshold hold voltage fluctuates with temperature, so the logic threshold hold voltage level rises at low temperatures, resulting in poor input high level characteristics, and the logic threshold hold voltage level drops at high temperatures. The input low level characteristic is deteriorated. Therefore, the input characteristic is changed according to the change of the ambient temperature, so that the operation becomes unstable or the operation speed is delayed.

CMOS 인버터의 로직 스레쉬 홀드 전압은 p-채널 MOS 및 n-채널 MOS 트랜지스터의 이득 상수의비, 소자의 스레쉬 홀드 전압의 함수이다.The logic threshold hold voltage of a CMOS inverter is a function of the ratio of the gain constants of the p-channel and n-channel MOS transistors and the threshold hold voltage of the device.

소자 이득 상수(β)는 온도가 증가하면 채널 캐리어의 이동도가 감소되므로, 그 결과

으로 감소되게 된다. 그러나 정공과 전자의 이동도가 온도에 대해 비슷하게 영향을 받게 되기 때문에 이득상수가 비(β ratio=βn/βp)는 온도에 대해서 독립적이다.The device gain constant β decreases as the channel carrier mobility increases as temperature increases.

Will be reduced. However, the gain constant ratio (β ratio = βn / βp) is independent of temperature because the mobility of holes and electrons is similarly affected with temperature.

그러나, 소자의 스레쉬 홀드전압 Vtn 및 Vtp은 온도 증가에 따라 각각 2mV/°K정도의 온도계수가 감소된다. 따라서 예컨대 50℃의 온도 상승시 로직 스레쉬 홀드전압은 0.4V 감소되게 된다. 그러므로 CMOS 입력 버퍼 회로는 고온 영역에서 동작시 입력 로우레벨 특성이 나빠지게 되고, 반대로 저온 영역에서 동작시 입력 하이레벨 특성이 나빠지게 된다.However, the threshold hold voltages Vtn and Vtp of the device decrease the temperature coefficients of about 2 mV / ° K, respectively, as the temperature increases. Thus, for example, when the temperature rises to 50 ° C, the logic threshold hold voltage is reduced by 0.4V. Therefore, the CMOS input buffer circuit deteriorates the input low level characteristic when operating in the high temperature region, and conversely, the input high level characteristic becomes poor when operating in the low temperature region.

따라서 본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 온도변화에 따라 MOS 트랜지스터의 이득상수의 비가 가변되도록 함으로써 온도보상이 되는 로직 수레쉬 홀드전압 특성을 가지는 CMOS 입력 버퍼 회로를 제공하는데 있다.Accordingly, an object of the present invention is to provide a CMOS input buffer circuit having a logic repair hold voltage characteristic that is compensated for temperature by varying the ratio of the gain constant of the MOS transistor according to temperature change in order to solve the problems of the prior art. have.

본 발명의 다른 목적은 초고집적 반도체 장치의 온도에 따른 입력 특성의 변화를 최소화 할 수 있는 CMOS 입력 버퍼 회로를 제공하는데 있다.Another object of the present invention is to provide a CMOS input buffer circuit capable of minimizing changes in input characteristics with temperature of an ultra-high density semiconductor device.

상기 목적을 달성하기 위하여 본 발명은 제1전원 공급선 및 제2전원 공급선의 사이에 서로 직렬로 연결되고, 그들의 제어전극에 병렬로 인가되는 TTL 전압레벨을 가지는 입력전압에 대응하여 그들의 드레인 공통 접속점에 CMOS 전압레벨을 가지는 출력전압을 공급하도록된 제1전도형의 제1 MOS 트랜지스터 및 제2전도형의 제2 MOS 트랜지스터를 구비한 것에 있어서, 상기 제1전원 공급선과 상기 공통접속점의 사이에 상기 입력전압과 결합되는 제어전극을 가지는 제1전도형의 MOS 트랜지스터와, 소정의 온도 이상에서 온되고 그 이하에서는 오프되는 스위칭 수단을 서로 직렬로 연결한 것을 적어도 하나이상 구비하고, 상기 적어도 하나이상의 스위칭 수단을 온도 변화에 따라 제어하도록 상기 스위칭 수단의 제어 신호 입력단에 결합되는 적어도 하나이상의 출력단자를 가지는 온도 검출수단을 구비하여서, 상기 제1전도형의 트랜지스터들의 총트랜지스터 이득 상수 값이 저온에서 감소되고 고온에서 증가되도록하여 온도에 따른 로직 스레쉬 홀드 전압레벨의 변동을 안정화시킬 수 있는 것을 특징으로 한다.In order to achieve the above object, the present invention is connected to each other in series between a first power supply line and a second power supply line, and corresponding to an input voltage having a TTL voltage level applied in parallel to their control electrodes at their drain common connection points. A first conductive MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type configured to supply an output voltage having a CMOS voltage level, wherein the input is provided between the first power supply line and the common connection point. At least one switching means having a first conductive MOS transistor having a control electrode coupled to a voltage, and at least one switching means connected in series with each other in a predetermined temperature or less, and in series therewith; At least one output coupled to the control signal input of the switching means to control the By having a temperature detecting means having a power terminal, the total transistor gain constant value of the transistors of the first conductivity type is reduced at low temperature and increased at high temperature to stabilize the variation of the logic threshold hold voltage level with temperature. It is characterized by.

상기 제1전도형의 트랜지스터들은 p-채널 MOS 트랜지스터로 하고 상기 제2전도형의 트랜지스터는 n-채널 MOS 트랜지스터로 하며 상기 스위칭 수단은 p-채널 MOS 트랜지스터로 한다. 따라서 스위칭 수단이 온되면 p-채널 트랜지스터의 이득 상수 βp가 증가 되므로 N- 및 p-채널 트랜지스터의 이득 상수비(β ratio)는

이므로 감소하게 된다.The first conductivity type transistors are p-channel MOS transistors, the second conductivity type transistors are n-channel MOS transistors, and the switching means are p-channel MOS transistors. Therefore, when the switching means is turned on, the gain constant βp of the p-channel transistor is increased, so the gain constant ratio (β ratio) of the N- and p-channel transistors is increased.

Will decrease.

따라서 온도 상승에 의한 로직 스레쉬 홀드 전압의 강하분에 대응하여 이득 상수의 비가 조정되어 로직 스레쉬 홀드 전압이 상승되도록 하여 온도 보상이 이루어지도록 된 것이다.Therefore, the ratio of the gain constant is adjusted in response to the drop of the logic threshold hold voltage caused by the temperature rise, so that the logic threshold hold voltage is raised to thereby perform temperature compensation.

상기 온도 검출수단은 제1전원 공급선과 제2전원 공급선의 사이에 서로 직렬로 연결된 전류 공급수단과 다결정 실리콘 저항수단을 각각 가지는 복수의 온도 감지수단을 구비하고, 상기 각 온도 감지수단들은 각각의 다결정 실리콘 저항수단의 임의의 주변 온도에 대응하여 서로 다른 전기적 출력신호를 발생하도록 된 것을 특징으로 한다.The temperature detecting means comprises a plurality of temperature sensing means each having a current supply means and a polycrystalline silicon resistance means connected in series between a first power supply line and a second power supply line, wherein each of the temperature sensing means is a respective polycrystal. Characterized in that it generates a different electrical output signal corresponding to any ambient temperature of the silicon resistance means.

도우핑 되지 않거나 아주 미약하게 불순물이 도우핑된 다결정 실리콘은 그 저항값이 매우 클 뿐만 아니라 온도 변화에 따라 그 저항값이 지수적으로 매우 크게 변한다.Not only doped or very lightly doped polycrystalline silicon has a very large resistance value, but the resistance value changes exponentially with temperature.

또한 MOS 트랜지스터의 문턱이하(Subthreshold)영역에서의 드레인 전류는 게이트 전압이 문턱 전압보다 작아질 때 지수적으로 감소한다. 따라서 이와같은 MOS 트랜지스터의 문턱 이하 전류 및 다결정 실리콘의 저항 온도 특성을 이용하여 반도체 온도를 검출할 수 있도록 구성함으로써 소비전력이 매우 작을 뿐만 아니라 초고집적 반도체 장치에 설치가 매우 적합하다.In addition, the drain current in the subthreshold region of the MOS transistor decreases exponentially when the gate voltage becomes lower than the threshold voltage. Therefore, the semiconductor temperature can be detected by using the sub-threshold current of the MOS transistor and the resistance temperature characteristic of the polycrystalline silicon, so that the power consumption is very small and it is very suitable to be installed in an ultra-high density semiconductor device.

상기 온도 검출수단의 각 온도 감지수단들의 전기적 출력신호는 디지털 변환수단, 예컨대 인버터 수단등을 통해서 디지털 신호로 변환하여 출력되도록 구성한다.The electrical output signal of each temperature sensing means of the temperature detecting means is configured to be converted into a digital signal through a digital converting means, such as an inverter means, and output.

상기 온도 검출수단의 전류 공급수단으로 이용되는 MOS 트랜지스터의 문턱이하 영역에서의 드레인 전류를 설정하기 위하여 전류 실정수단을 부가한다. 이 전류 설정수단은 상기 제1전원 공급선과 결합되는 제1 전류 전극, 상기 제2전원 공급선과 결합되는 제어전극 및 제1노드와 결합되는 제2전류전극을 가지는 제1전도형의 제1 MOS 트랜지스터; 상기 제1노드에 함께 결합되는 제1전류전극 및 제어전극과 상기 제2전원 공급선과 결합되는 제2전류전극을 가지며, 문턱이하 영역에서 동작되도록 상기 제1 MOS 트랜지스터의 기하학적 크기에 대해 충분히 큰 기하학적 크기를 갖도록 형성되는 제2전도형의 제2 MOS 트랜지스터; 상기 제1 MOS 트랜지스터의 제어전극과 결합되는 제어전극, 상기 제2전원 공급선과 결합되는 제1 전류전극 및 제2노드와 결합되는 제2전류전극을 가지며, 상기 제2 MOS 트랜지스터의 기하학적 크기에 대해 충분히 작은 기하학적 크기로 형성되는 제2전도형의 제3 MOS 트랜지스터; 상기 제1전원 공급선과 결합되는 제1전류전극, 상기 제2노드에 함께 결합되는 제어전극 및 제2전류전극을 가지며, 문턱이하 영역에서 동작되도록 상기 제3 MOS 트랜지스터의 기하학적 크기에 대해 충분히 큰 기하학적 크기로 형성되고 상기의 그의 제어전극이 상기 전류공급수단의 MOS 트랜지스터의 제어전극과 공통으로 결합되는 제1전도형의 제4 MOS 트랜지스터로 구성된 것을 특징으로 한다.Current actual means is added to set the drain current in the region below the threshold of the MOS transistor used as the current supply means of the temperature detection means. The current setting means includes a first MOS transistor having a first current electrode coupled to the first power supply line, a control electrode coupled to the second power supply line, and a second current electrode coupled to the first node. ; A first current electrode coupled to the first node and a control electrode and a second current electrode coupled to the second power supply line, the geometry being large enough for the geometric size of the first MOS transistor to operate in a sub-threshold region; A second MOS transistor of a second conductivity type formed to have a size; A control electrode coupled with a control electrode of the first MOS transistor, a first current electrode coupled with the second power supply line, and a second current electrode coupled with a second node, and with respect to a geometric size of the second MOS transistor A third MOS transistor of the second conductivity type formed with a sufficiently small geometric size; A first current electrode coupled to the first power supply line, a control electrode coupled to the second node, and a second current electrode, the geometry being large enough for the geometric size of the third MOS transistor to operate in a sub-threshold region; And a fourth MOS transistor of the first conductivity type formed in size and commonly coupled to the control electrode of the MOS transistor of the current supply means.

이와같은 구성은 전류 공급수단의 MOS 트랜지스터의 드레인 전류가 전류설정 수단의 제1 MOS 트랜지스터의 드레인 전류값과 상기 MOS 트랜지스터들의 기하학적 크기의 비에 의해서만 설정되도록 한다. 따라서 전류공급수단의 공급전류가 공정 및 온도변화에 무관한 값을 가지게 된다.This configuration allows the drain current of the MOS transistor of the current supply means to be set only by the ratio of the drain current value of the first MOS transistor of the current setting means to the geometric size of the MOS transistors. Therefore, the supply current of the current supply means has a value independent of process and temperature changes.

상기 온도검출 수단은 전류 공급수단을 구성하는 각 MOS 트랜지스터들의 기하학적 크기를 서로 다르게 하여 서로 다른 공급 전류값을 갖도록 함으로써 동일 저항값을 가지는 다결정 실리콘 저항 수단에 의해 임의의 주변온도에 대응하여 서로 다른 전기적 출력신호를 얻을 수 있다.The temperature detecting means has different supply current values by varying the geometric sizes of the respective MOS transistors constituting the current supply means so as to have different electrical currents corresponding to an arbitrary ambient temperature by the polycrystalline silicon resistance means having the same resistance value. The output signal can be obtained.

다른 방편으로는 공급전류가 동일한 경우에 각각의 다결정 실리콘 저항 수단의 저항값을 서로 달리 함으로써 임의의 주변 온도에 대응하여 서로 다른 전기적 출력신호를 얻을 수 있다.On the other hand, when the supply currents are the same, different electrical output signals can be obtained corresponding to an arbitrary ambient temperature by different resistance values of the respective polycrystalline silicon resistance means.

본 발명은 다음과 같이 변형 실시될 수 있다.The present invention can be modified as follows.

제1변형된 본 발명은 상술한 이득 상수값을 온도에 따라 변화시키기 위한 MOS 트랜지스터 및 스위칭 수단의 서로 직렬 연결된 것을 제2전원 공급선과 공통접속점과의 사이에 적어도 하나이상 구비하고, 상기 MOS 트랜지스터 및 스위칭 수단은 제2전도형의 트랜지스터로 구성하여서 된 것을 특징으로 한다.According to a first modified embodiment of the present invention, at least one of the MOS transistor and the switching means connected in series with each other in order to change the above-described gain constant value according to temperature is provided between the second power supply line and the common connection point, wherein the MOS transistor and The switching means is constituted by a transistor of the second conductivity type.

따라서 여기서 온도가 떨어지면 스위칭 수단이 소정 온도에서 온되도록 하여 제2전도형의 MOS 트랜지스터의 이득 상수값이 증가되게 된다. 예컨대 제2전도형을 n-채널로 하면 이득 상수 βn이 증가되므로 이득 상수의 비

는 증가되게 한다. 이득 상수의 비가 증가되면 로직 스레쉬 홀드전압은 낮아지게 되므로 온도보상이 이루어지게 된다.Therefore, when the temperature drops here, the switching means is turned on at a predetermined temperature, thereby increasing the gain constant value of the MOS transistor of the second conductivity type. For example, when the second conductivity type is n-channel, the gain constant βn increases, so the ratio of the gain constant

Is to be increased. If the ratio of the gain constant is increased, the logic threshold hold voltage is lowered, resulting in temperature compensation.

제2변형된 본 발명은 상술한 이득 상수값을 온도에 따라 변화시키기 위한 MOS 트랜지스터 및 스위칭 수단의 서로 직렬 연결된 것을 제1전원 공급선과 공통 접속점 사이에 적어도 하나이상 연결하고 제2전원 공급선과 상기 공통 접속점 사이에는 적어도 하나이상 연결하여서 된 것이다.According to a second modified embodiment of the present invention, the MOS transistor and the switching means connected in series with each other in series with each other between the first power supply line and the common connection point for changing the above-described gain constant value according to temperature, and the second power supply line and the common At least one connection is made between the connection points.

여기서 온도가 상승하면 전자의 스위칭 수단이 온되도록하여 트랜지스터 이득 상수비가 감소되도록 하고 온도가 하강되면 후자의 스위칭 수단이 온되도록 하여 트랜지스터 이득 상수비가 증가되도록 하여 로직 스레쉬 홀드 전압이 온도보상 되도록 된 것이다.When the temperature rises, the former switching means is turned on to reduce the transistor gain constant ratio, and when the temperature decreases, the latter switching means is turned on so that the transistor gain constant ratio is increased so that the logic threshold hold voltage is temperature compensated. .

이하 첨부한 도면을 참조하여 본 발명을 보다 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제1도는 종래의 CMOS 입력 버퍼 회로도이다.1 is a conventional CMOS input buffer circuit diagram.

제1도에서 제1전원 공급선(1), 예컨대 V_cc전압 공급선과 제2전원 공급선(2), 예컨대 V_ss전압 공급선 또는 접지라인과의 사이에 제1전도형(여기서 p-채널)의 제1 MOS 트랜지스터(M1) 및 제2전도형(여기서 n-채널)의 제2 MOS 트랜지스터(M2)를 서로 직렬로 연결하고 이들의 게이트 전극에 TTL 전압레벨을 가지는 입력전압이 병렬로 가해지도록 연결하고, 이들의 드레인 공통 접속점에 상기 입력전압에 대응하는 CMOS 전압 레벨을 가지는 출력전압이 공급되도록 연결하여서 된 것이다.In FIG. 1, the first conductive type (here p-channel) is formed between the first power supply line 1, for example, the V _cc voltage supply line and the second power supply line 2, for example, the V _ss voltage supply line or the ground line. 1 MOS transistor M1 and the second MOS transistor M2 of the second conductivity type (where n-channel) are connected in series with each other such that an input voltage having a TTL voltage level is applied to their gate electrodes in parallel. The output voltages having the CMOS voltage levels corresponding to the input voltages are connected to these drain common connection points.

여기서 로긱 스레쉬 홀드전압(Vinv)은Where the Logic Threshold Hold Voltage (Vinv)

V_DD=V_cc+V_{ss :}공급전압V _DD = V _cc + V _ss: Supply voltage

Vtp=p-채널 MOS 소자의 스레쉬 홀드전압Vtp = Threshold Hold Voltage for p-Channel MOS Devices

Vtn=n-채널 MOS 소자의 스레쉬 홀드전압Threshold Hold Voltage of Vtn = n-Channel MOS Device

βp=p-채널 MOS 소자의 이득 상수βp = Gain Constant of p-Channel MOS Devices

βn=n-채널 MOS 소자의 이득 상수Gain Constant of βn = n-Channel MOS Devices

이다. 상기 이득 상수비(βr)=βn/βp는 온도에 대해 독립적이고 소자의 크기의 비에 대해 종속적이다. 따라서 온도 변화에 대해 로직 스레쉬 홀드 전압값은 소자의 스레쉬 홀드 전압 Vtp, Vtn에 의존해서 제2도에 도시한 바와같이 온도가 상승하면 낮아지고 온도가 하강하면 높아지게 된다. 그러므로 고온에서 로우입력 특성이 나빠지게 되고 저온에서 하이입력 특성이 나빠지게 된다.to be. The gain constant ratio βr = βn / βp is independent of temperature and dependent on the ratio of the size of the device. Therefore, for the temperature change, the logic threshold hold voltage value decreases as the temperature increases and increases as the temperature decreases, as shown in FIG. 2 depending on the threshold hold voltages Vtp and Vtn of the device. Therefore, the low input characteristic is deteriorated at high temperature, and the high input characteristic is deteriorated at low temperature.

제3도는 본 발명의 바람직한 일실시예의 회로도이다. 제3도에서 제1도의 V_cc공급선(1)과 공통접속점(3)과의 사이에 서로 직렬 연결된 제3 p-채널 MOS 트랜지스터(M3) 및 제4 p-채널 MOS 트랜지스터(M4)와, 서로 직결 연결된 제5 p-채널 MOS 트랜지스터(M5) 및 제6 p-채널 MOS 트랜지스터(M6)를 함께 연결하고 또한 상기 제4 및 제6 MOS 트랜지스터(M4)(M6)의 각 게이트는 온도검출수단(10)의 출력단자(T1)(T2)에 각각 연결하여서 된 것이다.3 is a circuit diagram of one preferred embodiment of the present invention. In FIG. 3, the third p-channel MOS transistor M3 and the fourth p-channel MOS transistor M4 connected in series with each other between the V _cc supply line 1 and the common connection point 3 of FIG. The fifth p-channel MOS transistor M5 and the sixth p-channel MOS transistor M6 which are directly connected to each other are connected together, and each gate of the fourth and sixth MOS transistors M4 and M6 is connected to a temperature detecting means ( This is connected to the output terminals T1 and T2 of 10).

따라서 본 실시예는 온도 검출수단(10)은 T1, T2출력 단자의 출력상태 조합에 따라 제4 및 제6 MOS 트랜지스터(M4)(M6)를 스위칭시킴으로써 p-채널 소자들의 총체적인 이득 상수(βp)를 변화시켜 로직 스레쉬 홀드전압의 온도보상이 이루어지게 된다.Therefore, in the present embodiment, the temperature detecting means 10 switches the fourth and sixth MOS transistors M4 and M6 according to the combination of the output states of the T1 and T2 output terminals, and thus the overall gain constant βp of the p-channel elements. The temperature compensation of the logic threshold hold voltage is made by changing.

제4도는 상기 온도 검출수단의 일실시예의 회로도이다. 제4도에서 제1 및 제2전류공급수단(11)(13)으로는 문턱이하 영역에서 동작되는 p-채널 MOS 트랜지스터(M11)(M12)로 각각 구성한다. 상기 p-채널 MOS 트랜지스터(M11)의 소오스는 제1전원 공급선(1)에 연결하고, 드레인은 제3노드(N3)에 연결하며 게이트는 잔류 설정수단(15)에 연결한다. 다결정 실리콘 저항수단(12)의 일단은 상기 제3노드(N3)에 연결하고, 그의 타단은 제2전원 공급선(2)에 연결한다.4 is a circuit diagram of one embodiment of the temperature detecting means. In FIG. 4, the first and second current supply means 11 and 13 are composed of p-channel MOS transistors M11 and M12 respectively operated in sub-threshold regions. The source of the p-channel MOS transistor M11 is connected to the first power supply line 1, the drain is connected to the third node N3, and the gate is connected to the residual setting means 15. One end of the polycrystalline silicon resistance means 12 is connected to the third node N3, and the other end thereof is connected to the second power supply line 2.

상기 p-채널 MOS 트랜지스터(M12)의 소오스는 제1전원 공급선(1)에 연결하고, 드레인은 제4노드(N4)에 연결하며 게이트는 전류 설정수단(15)에 연결한다.The source of the p-channel MOS transistor M12 is connected to the first power supply line 1, the drain is connected to the fourth node N4, and the gate is connected to the current setting means 15.

다결정 실리콘 저항수단(12)의 일단은 상기 제4노드(N4)에 연결하고, 그의 타단은 제2전원 공급선(2)에 연결한다.One end of the polycrystalline silicon resistance means 12 is connected to the fourth node N4, and the other end thereof is connected to the second power supply line 2.

상기 전류 설정수단(15)은 4개의 MOS 트랜지스터로 구성한다.The current setting means 15 is composed of four MOS transistors.

제1 p-채널 MOS 트랜지스터(M7)는 소오스를 제1전원 공급선(1)에 연결하고 그의 게이트는 제2전원 공급선(2)에 연결하며, 그의 드레인은 제1노드(N1)에 연결하고, 그의 드레인 전류(ID1)를 상기 제1노드(N1)에 공급한다. 제2 n-채널 MOS 트랜지스터(M8)은 드레인 및 게이트를 상기 제1노드(N1)에 함께 연결하고 그의 소오스는 제2전원 공급선(2)에 연결한다. 여기서 제2 MOS 트랜지스터(M8)가 문턱이하 영역에서 동작되도록 제1 및 제2 MOS 트랜지스터의 기하적 크기의 비는 W7〈W8(L7=L8)로 되도록 형성한다. 제3 n-채널 MOS 트랜지스터(M9)는 상기 제2 MOS 트랜지스터(M8)와 동일한 게이트 바이어스전압을 갖도록 그의 게이트를 상기 제1노드(N1)에 연결하고, 소오스는 제2전원 공급선(2)에 연결하며 드레인은 제2노드(N2)에 연결한다. 따라서 제3 MOS 트랜지스터(M9)는 그의 채널폭에 상관없이 문턱이하 영역에서 동작하게 된다. 제3 MOS 트랜지스터(M9)의 드레인 전류(ID3)는 다음과 같다.The first p-channel MOS transistor M7 connects the source to the first power supply line 1, the gate thereof to the second power supply line 2, the drain thereof to the first node N1, Its drain current ID1 is supplied to the first node N1. The second n-channel MOS transistor M8 connects a drain and a gate together to the first node N1 and its source is connected to the second power supply line 2. Here, the ratio of the geometric size of the first and second MOS transistors is formed such that W7 < W8 (L7 = L8) so that the second MOS transistor M8 operates in the sub-threshold region. The third n-channel MOS transistor M9 connects its gate to the first node N1 to have the same gate bias voltage as the second MOS transistor M8, and the source is connected to the second power supply line 2. The drain is connected to the second node N2. Therefore, the third MOS transistor M9 operates in a sub-threshold region regardless of its channel width. The drain current ID3 of the third MOS transistor M9 is as follows.

제4 p-채널 MOS 트랜지스터(M10)는 상기 제2노드(N2)에 게이트 및 드레인을 함께 연결하고, 소오스를 제1전원 공급선(1)에 연결한다. 여기서 제4 MOS 트랜지스터(M10)가 문턱이하 영역에서 동작되도록 제3 및 제4 MOS 트랜지스터(M9)(M10)의 기하학적 크기의 비는 W9≪W10(L9=L10)로 되도록 형성한다.The fourth p-channel MOS transistor M10 connects a gate and a drain to the second node N2 and a source to the first power supply line 1. In this case, the ratio of the geometric size of the third and fourth MOS transistors M9 and M10 is formed such that the fourth MOS transistor M10 operates in a region below the threshold, such that W9 < W10 (L9 = L10).

상기 제2노드(N2)에는 상술한 전류 공급수단을 구성하는 제5 및 제6 p-채널 MOS 트랜지스터(M11)(M12)의 게이트가 연결된다. 따라서 제5 및 제6 p-채널 MOS 트랜지스터(M11)(M12)는 제4 MOS 트랜지스터(M10)와 동일한 게이트 전압을 가지게 되어 문턱이하 영역에서 동작하게 된다. 여기서 제4 및 제5 MOS 트랜지스터(M10)(M11)의 기하학적 크기의 비는 W10≪W11(L10=L11)로 되도록 형성한다. 그러므로 제5 MOS 트랜지스터의 드레인 전류(ID5)는 다음 식으로 설정된다.Gates of the fifth and sixth p-channel MOS transistors M11 and M12 constituting the current supply means are connected to the second node N2. Accordingly, the fifth and sixth p-channel MOS transistors M11 and M12 have the same gate voltage as the fourth MOS transistor M10 to operate in a sub-threshold region. The ratio of the geometric sizes of the fourth and fifth MOS transistors M10 and M11 is formed such that W10 < W11 (L10 = L11). Therefore, the drain current ID5 of the fifth MOS transistor is set by the following equation.

ID1 : 제1 MOS 트랜지스터의 드레인 전류ID1: drain current of the first MOS transistor

W9∼W10 : 각 MOS 트랜지스터의 채널폭W9 to W10: Channel width of each MOS transistor

또한 제4 및 제6 MOS 트랜지스터(M10)(M12)의 기하학적 크기의 비는 W10≫W12(L10=L12)로 되도록 형성한다. 그러므로 제6 MOS 트랜지스터의 드레인 전류(ID6)는 다음 식으로 설정된다.In addition, the ratios of the geometric sizes of the fourth and sixth MOS transistors M10 and M12 are formed such that W10 »W12 (L10 = L12). Therefore, the drain current ID6 of the sixth MOS transistor is set in the following equation.

또한 제5 MOS 트랜지스터(M11) 및 제1다결정 실리콘 저항수단(12)의 접속점인 제3노드(N3), 제6 MOS 트랜지스터(M12) 및 제2다결정 실리콘 저항수단(14)의 접속점인 제4노드(N4)는 각각 디지털 변환수단(16)(17)을 통하여 출력단자(T1)(T2)에 연결한다. 여기서 디지털 변환수단(16)(17)은 예컨대 2단 종속접속 인버터(IN1)(IN2) 및 (IN3)(IN4), 특히 CMOS형 인버터로 구성한다. 상기 제5 및 제6 MOS트랜지스터(M11)(M12)의 드레인 전류(ID5)(ID6)는, ID5〈ID6(W11〈W12)으로 결정되도록 한다.

Further, a fourth node N3 which is a connection point of the fifth MOS transistor M11 and the first polycrystalline silicon resistance means 12, a fourth point which is a connection point of the sixth MOS transistor M12 and the second polycrystalline silicon resistance means 14. The node N4 is connected to the output terminals T1 and T2 through the digital conversion means 16 and 17, respectively. The digital conversion means 16, 17 here comprise, for example, two stage cascaded inverters IN1 (IN2) and (IN3) (IN4), in particular CMOS inverters. The drain currents ID5 and ID6 of the fifth and sixth MOS transistors M11 and M12 are determined to be ID5 < ID6 (W11 < W12).

따라서 제1 및 제2다결정 실리콘 저항수단(12)(14)의 저항값을 동일하게 구성하면 제3 및 제4노드의 노드전압(VN3)(VN4)은Therefore, if the resistance values of the first and second polycrystalline silicon resistance means 12 and 14 are configured to be the same, the node voltages VN3 and VN4 of the third and fourth nodes are equal.

VN3(T)=ID5×RT1(T)VN3 (T) = ID5 × RT1 (T)

VN4(T)=ID6×RT2(T)VN4 (T) = ID6 × RT2 (T)

(RT1 : T°K에서의 제1다결정 실리콘의 저항값 RT2 : T°K에서의 제2다결정 실리콘의 저항값)으로 되며, 만약 동일온도(TK)에서 ID5〈ID6이므로 VN3(T)〈 VN4(T)로 되게된다.(RT1: resistance value of the first polycrystalline silicon at T ° K RT2: resistance value of the second polycrystalline silicon at T ° K), and if it is ID5 <ID6 at the same temperature (TK), VN3 (T) <VN4 It becomes (T).

예컨대, 292°K(20℃)dptj 제1인버터 수단(IN1)의 트립전압에 노드전압(VN3)이 도달되도록 설정하고 323°K(50℃)에서 제3인버터 수단(IN3)의 트립전압에 노드전압(VN3)이 도달되도록 설정하고 323°K(50℃)에서 제3인버퍼수단(IN3)의 트립전압에 노드전압(VN3)이 도달되도록 설정하고 323°K(50℃)에서 제3인버퍼수단(IN3)의 트립전압에 노드전압(VN4)이 도달되도록 설정하면, 그 출력단자(T1)(T2)의 출력상태는 다음 표 1과 같이 변하게 된다.For example, the node voltage VN3 is set to reach the trip voltage of the first inverter means IN1 at 292 ° K (20 ° C.), and the trip voltage of the third inverter means IN3 at 323 ° K (50 ° C.). The node voltage VN3 is set to be reached and the node voltage VN3 is set to reach the trip voltage of the third buffer means IN3 at 323 ° K (50 ° C), and the third voltage is reached at 323 ° K (50 ° C). When the node voltage VN4 is set to reach the trip voltage of the inbuffer means IN3, the output state of the output terminals T1 and T2 changes as shown in Table 1 below.

[표 1]TABLE 1

그러므로 제3도의 온도변화에 따른 이득 상수의 비(βr)의 변하는 다음 표 2와 같이 변하게 된다.Therefore, the change of the ratio (βr) of the gain constant according to the temperature change of FIG. 3 is changed as shown in Table 2 below.

[표 2]TABLE 2

따라서 제5도에 도시한 바와같이 로직 스레쉬 홀드값은 온도가 상승하면 점선 파형으로 낮아지게 되나 트랜지스터 이득 상수의 비는Therefore, as shown in FIG. 5, the logic threshold hold value is lowered by the dotted line waveform when the temperature rises, but the ratio of the transistor gain constant is

로 되어 작아지게 되므로 제5도의 실선파형으로 로직 스레쉬 홀드전압이 보정되게 된다. 그러므로 온도 상승에 따른 로우 입력레벨 특성이 저하되는 것이 방지되게 된다.The logic threshold hold voltage is corrected by the solid line waveform of FIG. Therefore, the degradation of the low input level characteristic due to the temperature rise is prevented.

마찬가지로 온도가 하강하면 제5도의 점선파형으로 로직 스레쉬 홀드값이 높아지게 되나 트랜지스터 이득 상수의 비가Likewise, if the temperature drops, the logic threshold value becomes higher due to the dotted wave in FIG. 5, but the ratio of the transistor gain constant

로 되어 커지게 되므로 제5도의 실선파형으로 로직 스레쉬 홀드전압이 보정되게 된다. 그러므로 온도 상승에 따른 하이 입력레벨 특성이 저하되는 것이 방지되게 된다.The logic threshold hold voltage is corrected by the solid line waveform of FIG. Therefore, the degradation of the high input level characteristic due to the temperature rise is prevented.

제6도에서 본 발명의 변형된 실시예를 도시한 것이다. 제6도에서는 제1도의 V_ss공급선(1)과 공통접속점(3)과의 사이에 서로 직렬로 연결된 제3 n-채널 MOS 트랜지스터(M13) 및 제4 n-채널 MOS 트랜지스터(M14)와, 서로 직렬로 연결된 제5 및 제6 n-채널 MOS 트랜지스터(M15)(M16)를 함께 연결하고 또한 상기 제3 및 제5 MOS 트랜지스터(M13)(M15)의 각 게이트는 제4도에 도시한 온도검출수단(10)의 출력단자(T1)(T2)에 각각 연결하여서 된 것이다.6 shows a modified embodiment of the present invention. 6 shows a third n-channel MOS transistor M13 and a fourth n-channel MOS transistor M14 connected in series with each other between the V _ss supply line 1 and the common connection point 3 of FIG. The fifth and sixth n-channel MOS transistors M15 and M16 connected in series with each other are connected together, and each gate of the third and fifth MOS transistors M13 and M15 is connected to the temperature shown in FIG. It is connected to the output terminals T1 and T2 of the detection means 10, respectively.

제6도의 온도변화에 따른 이득 상수의 비(βr)의 변화는 다음 표 3과 같이 변하게 된다.The change in ratio (r) of the gain constant according to the temperature change of FIG. 6 is changed as shown in Table 3 below.

[표 3]TABLE 3

따라서 트랜지스터 이득상수의 비값이 온도가 상승하면 βr(323°K이상)= β2/βp로 되고 온도가 하강하면 βr(293°K이하)=(β2+β14+β16)/βp로 되게된다. 그러므로 제5도의 로직 스레쉬 홀드전압 온도특성을 얻을 수 있다.Therefore, when the temperature rises, the ratio of the transistor gain constant becomes βr (323 ° K or more) = β2 / βp and when the temperature decreases, βr (293 ° K or less) = (β2 + β14 + β16) / βp. Therefore, the logic threshold hold voltage temperature characteristic of FIG. 5 can be obtained.

제7도는 본 발명의 변형된 다른 실시예를 도시한 것이다. 제7도에서 제1도의 Vcc 공급선(1)과 공통접속점(3)과의 사이에 서로 직렬로 연결된 제3 및 제4 p-채널 MOS 트랜지스터(M17)(M18)를 연결하고 V_ss공급선(2)과 공통접속점(3)과의 사이에 서로 직렬로 연결된 제5 및 제6 n-채널 MOS 트랜지스터(M19)(M20)를 연결하고, 또한 상기 제4 p-채널 및 제5 n-채널 MOS 트랜지스터(M18)(M19)의 각 게이트는 제4도에 도시한 온도검출수단(10)의 출력단자(T2)(T1)에 각각 연결하여서 된 것이다.7 illustrates another modified embodiment of the present invention. In FIG. 7, the third and fourth p-channel MOS transistors M17 and M18 connected in series with each other between the Vcc supply line 1 and the common connection point 3 of FIG. 1 are connected to each other, and the V _ss supply line 2 is connected. ) And the fifth and sixth n-channel MOS transistors M19 and M20 connected in series with each other, and the fourth p-channel and fifth n-channel MOS transistors. Each gate of M18 and M19 is connected to the output terminals T2 and T1 of the temperature detecting means 10 shown in FIG.

제7도의 온도변화에 따른 이득 상수의 비(βr)는 변하는 다음 표 4와 같은 변하게 된다.The ratio of the gain constant βr according to the temperature change of FIG. 7 is changed as shown in Table 4 below.

[표 4]TABLE 4

따라서 트랜지스터 이득 상수의 비(βr)값이 온도가 상승하면 βr(323°K이상)

로 감소되고 온도가 하강하면 βr(293°K이하)

으로 증가되게 된다. 그러므로 제5도의 로직 스레쉬 홀드전압 온도 특성을 얻을 수 있다.Therefore, if the ratio (βr) of the transistor gain constant rises in temperature, βr (above 323 ° K)

Decreases and the temperature decreases, βr (below 293 ° K)

To increase. Therefore, the logic threshold hold voltage temperature characteristic of FIG. 5 can be obtained.

이상과 같이 본 발명에서 저온영역에서 로직 스레쉬 홀드 전압레벨이 상승되는 것을 소자크기의 비, 즉 트랜지스터 이득 상수의 비를 크게 함으로서 로직 스레쉬 홀드 전압레벨의 상승을 억제시키고, 고온영역에서 트랜지스터 이득 상수의 비를 작게 함으로써 로직 스레쉬 홀드 전압레벨의 하강을 억제시킴으로써 CMOS 입력 버퍼 회로의 온도에 따른 입력 레벨 특성을 안정화시킬 수 있게 된다.As described above, the increase in the logic threshold hold voltage level in the low temperature region is suppressed by increasing the ratio of the element size, that is, the transistor gain constant, in the low temperature region, thereby suppressing the increase in the logic threshold hold voltage level and increasing the transistor gain in the high temperature region. By reducing the ratio of the constants, it is possible to stabilize the input level characteristics according to the temperature of the CMOS input buffer circuit by suppressing the drop in the logic threshold hold voltage level.

본 명세서에서 두 개의 온도보정점을 가지는 실시예를 통하여 본 발명을 설명 하였으니 두 개 이상의 온도 보정점을 가지는 것도 당업자라면 본 발명의 기술적 사상 및 청구범위 내에서 용이하게 실시할 수 있다.Since the present invention has been described through an embodiment having two temperature correction points in the present specification, having two or more temperature correction points can be easily implemented by those skilled in the art within the spirit and claims of the present invention.

Claims

Supply an output voltage having a CMOS voltage level to their drain common connection points corresponding to an input voltage having a TTL voltage level connected in series between each of the first power supply line and the second power supply line in series and applied to their control electrodes in parallel. A first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type, each having a control electrode coupled to the input voltage between the first power supply line and the common connection point. At least one connected in series with a first conducting MOS transistor and a switching means turned on at a temperature higher than a predetermined temperature and turned off at a lower temperature, wherein the at least one switching means is controlled to change according to a temperature change; And a temperature detecting means having at least one output terminal coupled to the control signal input of the switching means. Yeoseo, said first conductivity has a total transistor gain constants of the transistors of the type being reduced at a low temperature to be increased at a high temperature, characterized in that to stabilize the logic thread rest variation in threshold voltage level corresponding to the temperature CMOS input buffer circuit.

2. The transistor of claim 1, wherein the first conductivity type transistors are p-channel MOS transistors, the second conductivity type transistors are n-channel MOS transistors, and the switching means are p-channel MOS transistors. CMOS input buffer circuit.

3. The apparatus of claim 2, wherein the temperature detecting means comprises a plurality of temperature sensing means each having a current supply means and a polycrystalline silicon resistance means connected in series between a first power supply line and a second power supply line. And the sensing means are adapted to generate different electrical output signals in response to an arbitrary ambient temperature of each polycrystalline silicon resistance means.

4. The CMOS input buffer circuit according to claim 3, wherein digital conversion means for converting the electrical output signal of said temperature sensing means into a digital signal is added.

The output terminal of the second stage inverter is coupled to the control signal input terminal of the switching means, wherein the digital conversion means is respectively coupled to an input terminal of the first stage inverter at a common connection point of the current supply means and the polycrystalline silicon resistance means. CMOS input buffer circuit comprising a two stage cascade inverter coupled.

6. The CMOS input buffer circuit according to any one of claims 1 to 5, wherein said polycrystalline silicon resistance means is doped or lightly doped with impurities.

7. The CMOS input buffer circuit of claim 6, wherein each of the current supply means comprises a MOS transistor configured to operate in a sub-threshold region.

8. The CMOS input buffer circuit according to claim 7, wherein each of the MOS transistors additionally includes a common current setting means for setting a drain current.

9. The method of claim 8, wherein the current setting means has a first conduction electrode having a first current electrode coupled to the first power supply line, a control electrode coupled to the second power supply line, and a second current electrode coupled to the first node. Type MOS transistor; A first current electrode coupled to the first node and a control electrode and a second current electrode coupled to the second power supply line, the geometry being large enough for the geometric size of the first MOS transistor to operate in a sub-threshold region; A second MOS transistor of a second conductivity type formed to have a size; And a control electrode coupled to the control electrode of the second MOS transistor, a first current electrode coupled to the second power supply line, and a second current electrode coupled to the second node, with respect to the geometric size of the second MOS transistor. A third MOS transistor of the second conductivity type formed with a sufficiently small geometric size; A first current electrode coupled to the first power supply line, a control electrode coupled to the second node, and a second current electrode, the geometry being large enough for the geometric size of the third MOS transistor to operate in a sub-threshold region; And a fourth MOS transistor of a first conductivity type which is formed in size and whose control electrode is commonly coupled with the control electrode of the MOS transistor of the current supply means.

10. The CMOS input of claim 9, wherein the temperature sensing means are formed such that each of the MOS transistors of the current supply means has a different geometric size to generate different electrical output signals in response to an arbitrary ambient temperature. Buffer circuit.

11. The CMOS input buffer circuit according to claim 10, wherein the temperature sensing means are formed such that each polycrystalline silicon resistance means has a different resistance value in order to generate different electrical output signals in response to an arbitrary ambient temperature.

Supply an output voltage having a CMOS voltage level to their drain common connection points in correspondence with an input voltage having a TTL power level connected in series between each of the first power supply line and the second power supply line and applied in parallel to their control electrodes. A first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type have a control electrode coupled with the input voltage between the second power supply line and the common connection point. And at least one second connecting MOS transistor of the second conductivity type and a switching means which is turned off above a predetermined temperature and turned on below, in order to control the at least one switching means according to a temperature change. Obtaining temperature detecting means having at least one output terminal coupled to the control signal input of the switching means Hayeoseo, wherein the second conductive has a total transistor gain constants of the transistors of the type being increased at a low temperature to ensure that reduction at a high temperature CMOS type, characterized in that to stabilize the logic thread rest variation in threshold voltage level corresponding to the temperature of the buffer circuit.

13. The transistor of claim 12, wherein the first conductivity type transistor is a p-channel MOS transistor, the second conductivity type MOS transistors are an n-channel MOS transistor, and the switching means is an n-channel MOS transistor. CMOS input buffer circuit.

14. The apparatus of claim 13, wherein the temperature detecting means comprises a plurality of temperature sensing means each having a current supply means and a polycrystalline silicon resistance means connected in series between a first power supply line and a second power supply line. And the sensing means are adapted to generate different electrical output signals in response to an arbitrary ambient temperature of each polycrystalline silicon resistance means.

15. The CMOS input buffer circuit according to claim 14, wherein digital conversion means for converting the electrical output signal of said temperature sensing means into a digital signal is added.

16. The digital conversion means according to claim 15, wherein the input terminal of the first stage inverter is coupled to the common connection point of the current supply means and the polycrystalline silicon resistance means, respectively, and the output terminal of the second stage inbuffer is connected to the control signal input terminal of the switching means. CMOS input buffer circuit comprising a two-stage cascaded in-buffer coupled together.

17. The CMOS input buffer circuit according to any one of claims 11 to 16, wherein the polycrystalline silicon resistance means is doped or lightly doped with impurities.

18. The CMOS input buffer circuit according to claim 17, wherein each current supply means comprises a MOS transistor configured to operate in a sub-threshold region.

19. The CMOS input buffer circuit according to claim 18, wherein each of the MOS transistors additionally provides a common current setting means for setting a drain current.

20. The method of claim 19, wherein the current setting means has a first current electrode having a first current electrode coupled to the first power supply line, a control electrode coupled to the second power supply line, and a second current electrode coupled to the first node. Type MOS transistor; A first current electrode coupled to the first node and a control electrode and a second current electrode coupled to the second power supply line, the geometry being large enough for the geometric size of the first MOS transistor to operate in a sub-threshold region; A second MOS transistor of a second conductivity type formed to have a size; And a control electrode coupled to the control electrode of the second MOS transistor, a first current electrode coupled to the second power supply line, and a second current electrode coupled to the second node, with respect to the geometric size of the second MOS transistor. A third MOS transistor of the second conductivity type formed with a sufficiently small geometric size; A first current electrode coupled to the first power supply line, a control electrode coupled to the second node, and a second current electrode, the geometry being large enough for the geometric size of the third MOS transistor to operate in a sub-threshold region; And a fourth MOS transistor of a first conductivity type which is formed in size and whose control electrode is commonly coupled with the control electrode of the MOS transistor of the current supply means.

21. The CMOS input of claim 20, wherein said temperature sensing means are formed such that each MOS transistor of said current supply means has a different geometric size to generate different electrical output signals in response to an arbitrary ambient temperature. Buffer circuit.

22. The CMOS input buffer circuit according to claim 21, wherein the temperature sensing means are formed such that the polycrystalline silicon resistance means have different resistance values so as to generate different electrical output signals in response to an arbitrary ambient temperature.

Supply an output voltage having a CMOS voltage level to their drain common connection points corresponding to an input voltage having a TTL voltage level connected in series between each of the first power supply line and the second power supply line and applied in parallel to their control electrodes. A first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type, each having a control electrode coupled with the input voltage between the second power supply line and the common connection point. A first conducting MOS transistor and a first switching means connected to each other in series above and below a certain temperature in series and coupled to the input voltage between the second power supply line and the common connection point; A second conductivity type MOS transistor having electrodes and being turned off above and below any other temperature above said any temperature. Is provided with at least one connecting each of the second switching means in series with each other, and has a temperature detecting means having a plurality of output terminals coupled to the control signal input terminals of the at least one first and second switching means. And stabilize the variation of the logic threshold hold voltage level by causing the total transistor gain constant value of the first conductivity type transistors to be increased at high temperature and the total transistor gain constant value of the second conductivity type transistors to be increased at low temperature. CMOS input buffer circuit, characterized in that.

24. The method of claim 23, wherein the first switching means is a MOS transistor of a first conductivity type, the second switching means is a MOS transistor of a second conductivity type, and the transistors of the first conductivity type are a p-channel MOS transistor. And the second conductivity type transistors are n-channel MOS transistors.

25. The apparatus according to claim 24, wherein the temperature detecting means comprises a plurality of temperature sensing means each having a current supply means and a polycrystalline silicon resistance means connected in series between a first power supply line and a second power supply line. And the sensing means are adapted to generate different electrical output signals in response to an arbitrary ambient temperature of each polycrystalline silicon resistance means.

27. The CMOS input buffer circuit according to claim 25, wherein digital conversion means for converting the electrical output signals of said temperature sensing means into digital signals is added.

26. The digital conversion means according to claim 25, wherein the input terminals of the first stage inverter are coupled to the common connection point of the current supply means and the polycrystalline silicon resistance means, respectively, and the output terminal of the second stage inverter is coupled to the control signal input terminal of the switching means. A CMOS input buffer circuit comprising a two stage cascade connected inverter.

28. The CMOS input buffer circuit according to any one of claims 23 to 27, wherein the polycrystalline silicon resistance means is doped or lightly doped with impurities.

29. The CMOS input buffer circuit of claim 28, wherein each of the current supply means comprises a MOS transistor configured to operate in a sub-threshold region.

30. The CMOS input buffer circuit according to claim 29, wherein each of the MOS transistors additionally includes a common current setting means for setting a drain current.

30. The device of claim 29, wherein the current setting means comprises: a first MOS transistor of a first conductivity type having a control electrode coupled to the first power supply line and a second current electrode coupled to a first node; A first current electrode coupled to the first node and a control electrode and a second current electrode coupled to the second power supply line, the geometry being large enough for the geometric size of the first MOS transistor to operate in a sub-threshold region; A second conductivity type second MOS transistor formed to have a size; And a control electrode coupled to the control electrode of the second MOS transistor, a first current electrode coupled to the second power supply line, and a second current electrode coupled to the second node, with respect to the geometric size of the second MOS transistor. A third MOS transistor of the second conductivity type formed with a sufficiently small geometric size; A first current electrode to which the first power supply line is coupled, a control electrode and a second current electrode coupled to the second node, and have a geometry large enough for the geometric size of the third MOS transistor to operate in a sub-threshold region. And a fourth MOS transistor of a first conductivity type which is formed in size and whose control electrode is commonly coupled with the control electrode of the MOS transistor of the current supply means.

32. The CMOS input of claim 31, wherein the temperature sensing means are formed such that each of the MOS transistors of the current supply means has a different geometric size so as to generate different electrical output signals correspondingly at any ambient temperature. Buffer circuit.

32. The CMOS input buffer circuit according to claim 31, wherein the temperature sensing means are formed such that each polycrystalline silicon resistance means has a different resistance value in order to generate different electrical output signals in response to an arbitrary ambient temperature.