GB2222024A

GB2222024A - Programmable integrated circuits

Info

Publication number: GB2222024A
Application number: GB8819669A
Authority: GB
Inventors: Roger Leslie Baker; Paul John Rosser; Stephen Robert Jennings; Colin Nicholas Duckworth
Original assignee: STC PLC
Current assignee: STC PLC
Priority date: 1988-08-18
Filing date: 1988-08-18
Publication date: 1990-02-21
Anticipated expiration: 2008-08-18
Also published as: GB2222024B; GB8819669D0

Abstract

The integrated circuit is programmable by the activation of antifuses. Each antifuse comprises an active device, typically a polysilicon emitter bipolar transistor, in which the emitter is isolated from the substrate by a thin insulator film. The antifuse is activated by the application of a voltage pulse which breaks down the insulator and enables the device. <IMAGE>

Description

IMPROVEMENTS IN INTEGRATED CIRCUITS.

This invention relates to integrated circuits, and in particular to circuits that are programmable to perform a desired function. The invention also relates to a method of providing programmability.

For certain custom circuit applications it is desirable to provide a degree of programmability in an integrated circuit. Conventionally, programmability is provided either by the use of fuse links or by the use of antifuses. An antifuse is a device which is initially in a high resistance condition (open circuit) but which, on the application of a suitable electric field, changes from its high resistance state to low resistance state.

In general this change is irreverisble The principle disadvantage with conventional programming devices is that they represent process steps additional to those used for fabricating the integrated circuit. These additional steps are inconvenient and, in extreme cases, may reduce the yield of functional devices.

The object of the present invention is to minimise this disadvantage.

According to one aspect of the invention there is provided a programmable integrated circuit, including an array of active devices disposed on a silicon substrate, each said device having an electrode body disposed on the substrate, wherein an insulator film is provided beneath the electrode body of at least some of said devices so as to disable those devices, the arrangement being such that, in use, electrical breakdown of the insulator film may be effected to enable selected ones of those devices so as to provide a desired circuit function.

According to another aspect of the invention there is provided a programmable integrated circuit, including an array of polysilicon emitter transistors, those being an insulator film disposed beneath the polysilicon emitter of at least some transistor whereby those transistors are disabled, the arrangement being such that, in use, electrical breakdown of the oxide film of selected ones of said some transistors may be effected to enable those transistors so as to provide a desired circuit function.

According to a further aspect of the invention there is provided a method of fabricating a programmable integrated circuit, the method including providing an array of bipolar polysilicon emitter transistors on a common silicon substrate, and interconnecting said array to provide a circuit pattern, wherein an insulating layer is provided beneath the polysilicon emitter body at least some of said transistors so as to disable those transistors, wherein selected ones of said diasabled transistors are, in use, enabled by the application to their respective emitter bodies of an electric field whereby to break down the insulator film.

As the antifuses comprise active circuit devices, their incorporation in the integrated circuit structure represents at most only a minor departure from the standard fabrication process.

The technique is particularly adapted for use in integrated circuits employing polysilicon emitter technology. There may be wholly bipolar or mixed bipolar/CMOS structures. Such circuits are described for example in our UK patent specification No. 2173638.

Typically the circuit comprises an analogue array.

Embodiments of the invention will now be -described with reference to the accompanying drawings in which Figures 1 to 5 represent process steps in the fabrication of a programmable integrated circuit; Figure 6 illustrates the current/voltage characteristics of the device structure of Figures 1 to 5 after operation of the anti fuse by the application thereto of an electric field; and Figures 7 to 10 illustrate a modified fabrication process.

Referring to Figures 1 to 5 of the drawings, which for clarity illustrate the fabrication only of that portion of a polysilicon emitter transisor necessary for the understanding of the invention, the circuit is disposed on a single crystal silicon substrate and includes an array of polysilicon emitter transistors which form the active devices of the circuit. Either an n-type substrate is employed or, preferably, the devices are disposed in n-type wells formed in the substrate. A single crystal silicon substrate 11 (Figure 1) is masked and provided with field oxide regions 12. The field oxide has a window 13 whereby a p-type layer 14 is implanted into the substrate surface. This p-type layer 14 is covered with a thin oxide layer 15.The structure is provided with a photoresist mask 16 (Figure 2) having a window 17 whereby a portion of the thin oxide layer 15 is removed, e.g. the underlying e.g. by plasma etching on by wet etching, to expose substrate. A thin insulator layer 18 (Figure 3) is then grown on the exposed substrate surface. Typically this layer 18 comprises silicon oxide, silicon nitride, silicon oxynitride, or silicon nitroxide. The layer thickness is chosen to provide a desired breakdown voltage. E.g. ior a breakdown voltage of about 10 volts an insulator layer thickness of Snm is suitable. Typically we use film thickness between 2.5 and lOnm. Advantageously, the layer 18 is grown by pulse heating the structure in an atmosphere of steam, nitrogen or mixtures thereof. Atmospheres of oxygen or ammonia may also be used.

After growth of the insulator layer 18, a layer of polysilicon is deposited and selectively etched to form an emitter body 19 (Figure 4). The structure is then oxidised to grow an oxide film 20 preferentially on the polysilicon body 19. The oxide coated emitter body 19 is then used as a mask for the implantation of p -type regions 21 (Figure 5) which region form the base regions of the transistor structure. An oxide layer 22 in then deposited on the entire structure. The layer 22 is masked and etched to define windows 23 in register one with each polysilicon body 19. Finally a metallisation pattern 24 is applied to the structure to contact each emitter body 19 via the respective windows 23.

As the emitter body of the structure described above is isolated from the substrate by the insulating layer, the transistor structure is inoperative. In use, the structure is activated by the application of a voltage pulse to the emitter body 19 via the metallisation 21. This causes breakdown and dissipation of the oxide layer, the breakdown being irreversible.

The current path between the emitter body and the substrate thus changes from a high resistance to a low resistance condition allowing thr structure to function as a bipolar transistor. The effect is illustrated in Figure 6 of the accompanying drawings in which current voltage characteristics for a typical device are shown after activation of the device (prior to activation of the device the characteristiclies substantially along the horizontal axis).

In a typical circuit structure a plurality of such devices are employed. The circuit is programmed by the manufacture or the user by activating selected devices so as to provide a desired circuit function.

In a modified fabrication process, the substrate 11 (Figure 7) is provided with field oxide, a thin oxide layer and an implanted p-type layer as previously described. A patterned photoresist mask 81 (Figure 8) is applied and the exposed oxide layer is etched away to expose the underlying substrate. The mask 81 is removed and the exposed substrate is coated with an insulator film 82. The entire wafer is then coated with a thin layer 83 (Figure 9) of polysilicon.

Typically this layer is 1 to lOnm in thickness. A further mask (not shown) is applied and the polysilcon 83 is removed, e.g. by plasma or wet etching, from all areas of the wafer with the exception of those device areas that are to become antifuses. A wet etch may then be used to remove the insulator from the non-programmable devices, the polysilicon coating providing a mask on the remaining devices.

Further polysilicon is then deposited and patterned to provide emitter bodies 84 (Figure 10) on both the programmable and non-programmable devices. An oxide layer 85 in then deposited on the entire structure. The layer 85 is masked and etched as before to define windows 86 in register one with each polysilicon body 84. Finally a metallisation pattern 87 is applied to the structure to contact each emitter body 84 via the respective windows 86.

As at previously described, the circuit is programmed by breaking down the insulator layer of selected programmable devices to provide a desired circuit function.

Claims

CLAIMS.

1. A programmable integrated circuit, including a plurality of antifuses whereby, in use, the circuit may be programmed, wherein each said anti fuse is so constructed that, when operated, it becomes an active semiconductor device.

2. A programmable integrated circuit, including an array of active devices disposed on a silicon substrate, each said device having an electrode body disposed on the substrate, wherein an insulator film is provided beneath the electrode body of at leac. some of said devices so as to disable those devices, the arrangement being such that, in use, electrical breakdown of the insulator film may be effected to enable selected ones of those devices so as to provide a desired circuit function.

3. A programmable integrated circuit, including an array of polysilicon emitter transistors, those being an insulator film disposed beneath the polysilicon emitter of at least some transistor whereby those transistors are disabled, the arrangement being such that, in use, electrical breakdown of the oxide film of selected ones of said some transistors may be effected to enable those transistors so as to provide a desired circuit function.

4. A programmable circuit as claimed in claim 2 or 3, wherein said insulator film comprises silicon oxide, silicon nitride, silicon oxynitride or silicon nitroxide.

5. A programmable circuit as claimed in claim 1 wherein said insulator film is between 2.5 and lOnm.

6. A method of fabricating a programmable integrated circuit substantially as described herein with reference to and as shown in Figures 1 to 5 or Figures 7 to 10 of the accompanying drawings.

6. A programmable circuit as claimed in any one of claims 1 to 5, and incorporating both bipolar and field effect devices.

7. A programmable integrated circuit substantially as described herein with reference to and as shown in the accompanying drawings.

8. A programmable integratred circuit as claimed in any one of claims 1 to 6, and comprising an analogue array.

10. A method of fabricating a programmable integrated circuit, the method including providing an array of bipolar polysilicon emitter transistors on a common silicon substrate, and interconnecting said array to provide a circuit pattern, wherein an insulating layer is provided beneath the polysilicon emitter body at least some of said transistors so as to disable those transistors, wherein selected ones of said diasabled transistors are, in use, enabled by the application to their respective emitter bodies of an electric field whereby to break down the insulator film.