KR100205347B1 - Semiconductro and method of fabricating it - Google Patents

Abstract

Disclosed are a semiconductor device for suppressing the LATCH-UP phenomenon by reducing the gain ratio of bipolar operation generated in CMOS by injecting impurities in an energy level of a forbidden band of silicon, and a manufacturing method thereof.

The semiconductor device according to the present invention includes a semiconductor substrate, an isolation layer formed in an island shape on the substrate, a P + region and an N + region formed near the surface of the substrate, and a gate insulating film, polysilicon, and an insulating film on the substrate. A gate electrode surrounded by spacers on both sides thereof, an insulating film for insulating the gate electrode, a metal layer formed on the entire surface of the exposed substrate, and an impurity implantation layer formed by implanting impurity ions into a predetermined region inside the substrate, and fabricating the same. The method comprises channel stop implantation as part of a process of sequentially forming an insulating film and a nitride film on a semiconductor substrate, forming a well on the semiconductor substrate, and a locus process for isolation between NMOS transistors in the semiconductor substrate. The step of carrying out the process of NMOS and PMOS An ion implantation process for adjusting a threshold voltage, an LDD process on a side of a gate electrode formed on the semiconductor substrate, an impurity layer for preventing latch-up in the well region, and an N + region and a P + region The process and the process of forming a metal wiring layer are comprised.

Description

Semiconductor device and manufacturing method thereof

1 is a cross-sectional view showing a semiconductor device according to the prior art.

2A to K are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the prior art.

3 is a cross-sectional view showing a semiconductor device according to the present invention.

4A to K are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

* Explanation of symbols for main parts of the drawings

101, 201: semiconductor substrate 102, 202: first insulating film

102a, 202a: Burj Bek oxide film 103, 203: First nitride film

104, 204: second insulating film 105, 205: second nitride film

106, 206: n well 107, 207: device isolation film

108, 208: third insulating film 109, 209: gate insulating film

110, 210: polysilicon 111, 211: fourth insulating film

112, 212: N-LDD region 113, 213: P-LDD region

114, 214: spacer 115, 215: N + region

116 and 216 P + region 117 and 217 fifth insulating film

118, 218: metal wiring layer 219: impurity injection layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same, capable of suppressing latch-up phenomenon using impurity implantation.

As the degree of integration of semiconductor devices increases, a scaling down process has been performed as a means of increasing the number of devices per unit chip. In particular, the latched-up phenomenon of the scaled down CMOS (Complemently Metal Oxide Semiconductor) circuit has occurred. When it occurs, there is a lot of possession.

There is an inherent self-destructive phenomenon on CMOS circuits, which is called latch up.

Latch up phenomenon resists the phenomenon that a large current flows on the circuit by forming a path having extremely small resistance between the drain terminal and the source terminal. This can cause the circuit to not function properly or even destroy the circuit itself.

Hereinafter, a conventional CMOS semiconductor device and a manufacturing method thereof will be described with reference to the accompanying drawings.

1 is a cross-sectional view showing a semiconductor device according to the prior art.

The semiconductor substrate 101 and the P + region 116 and the N + region 115 are formed in the vicinity of the surface of the substrate 101, and the gate insulating film 109, the polysilicon 110, and the semiconductor substrate 101 are formed on the substrate 101. The cap oxide layer 111 is sequentially stacked, and both side walls form a gate electrode 109, 110, 111 surrounded by a spacer 114, an insulating layer 117 insulating the gate electrode, and a metal layer 118 on the entire surface of the exposed substrate.

2A to K are views showing a conventional method for manufacturing a CMOS semiconductor device.

First, FIG. 2A illustrates a process of sequentially forming the first insulating film 102 and the first nitride film 103 on the semiconductor substrate 101, which is performed by forming a thermal oxide film on the semiconductor substrate 101. The first process of forming the first insulating film 102 and the second process of forming the first nitride film 103 by applying a material such as a silicon nitride film on the first insulating film 102, for example. .

The first insulating film 102 is formed by a thermal oxidation method, and the first nitride film 103 is deposited by, for example, low pressure chemical vapor deposition (LPCVD).

FIG. 2B illustrates a process of forming the N well 106, the first process of forming a photoresist pattern on the first nitride film 103 to expose the nitride film in an isolation region, and the photoresist pattern. The anisotropic etching of the nitride film using the etching mask as an etching mask proceeds to the second process of forming the N well 106.

FIG. 2C shows a step of forming the P well 119 using the buzz beak oxide film 102a as a mask, and is a step of ion implantation using a Group 3 element as an impurity.

The N well region 106 is further diffused under the semiconductor substrate during the process.

FIG. 1d illustrates a process of performing channel stop implantation as a part of a locus process for the purpose of isolation between NMOS transistors, and the process of FIG. A first step of forming the second insulating film 104 and the second nitride film 105 on the semiconductor substrate again, patterning the second insulating film 104 and the second nitride film 105 and performing channel stop ion implantation The process proceeds to the second process.

2e and f illustrate a process of adjusting threshold voltages of NMOS and PMOS, respectively, and inject ions of Groups 5 and 3, respectively.

In the process of FIG. 2E, after the device isolation layer 107 is formed, a photoresist is applied and patterned to perform group 5 ion implantation for controlling the N channel threshold voltage.

The process of FIG. 2F and the process of FIG. 2E are performed, but the group 3 ion implantation is performed.

2g and h illustrate a process of forming a LDD (Ligthly Doped Drain), which forms N-LDD and P-LDD regions, respectively.

In the process of FIG. 2G, after the process of FIG. 2F is completed, the gate insulating layer 109, the polysilicon 110, and the fourth insulating layer 111 are sequentially stacked and then patterned to form the gate electrodes 109, 110, and 111. And a photoresist on all the structures and patterning only the N-LDD region 112 to implant group 5 ions onto the exposed semiconductor substrate 101 after the first process. Proceeds to the second process.

The process of FIG. 2h is similar to the process of FIG. 2g but implants group III ions by patterning the P-LDD region 113.

2i and j show a process for forming an N + region and a P + region.

In the process of FIG. 2i, after the process of FIG. 2h is performed, the first process of forming the spacer 114 made of the high temperature oxide film by anisotropically etching the high temperature oxide film on the sidewall of the gate electrode and the photoresist remain after the first process. After the first process, only the N + region 115 is patterned and implanted with group 5 ions onto the exposed semiconductor substrate.

The process of FIG. 2J follows the process of FIG. 2I but implants group III ions by patterning the P + region 116.

2k is a cross-sectional view showing a CMOS semiconductor device completed after forming a metal layer.

FIG. 2K illustrates a first process of forming and patterning a fifth insulating layer and a second process of depositing / etching a metal.

In the conventional CMOS semiconductor device completed as described above, a path having an extremely small resistance component is formed in the semiconductor substrate, whereby a large current flows on the circuit, thereby preventing the circuit from performing its function properly or severely. The problem of destroying the circuit itself occurs.

Accordingly, the present invention has been proposed to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can suppress a latch up phenomenon by forming an impurity layer through impurity injection. To provide.

The semiconductor device according to the present invention for achieving the above object is a semiconductor substrate, the P + region and the N + region is formed in the vicinity of the surface of the substrate, the gate insulating film, polysilicon and the insulating film is provided on the substrate and both side walls A gate electrode surrounded by the spacer and an insulating film for insulating the gate electrode are formed, and a metal layer is formed on the entire surface of the exposed substrate.

An impurity implantation layer is formed by implanting impurity ions in a predetermined region of the substrate.

In still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: sequentially forming a first insulating film and a first nitride film on a semiconductor substrate; forming a well on the semiconductor substrate; Performing a channel stop implantation as part of a locus process for isolation between NMOS transistors in a substrate, an ion implantation process for adjusting threshold voltages of NMOS and PMOS in the semiconductor substrate, and a semiconductor substrate; Forming an LDD on the side of the gate electrode formed thereon; forming an impurity layer to prevent latch-up in the well region; forming an N + region and a P + region; and forming a metal wiring layer.

When the impurity layer is formed by using ions such as titanium (Ti), the energy level of a material such as titanium is present in the silicon band gap, which is generated during the parasitic transistor operation for the CMOS to enter the latch up state. By acting as a recombination center of electrons and holes, the occurrence of latch-up can be suppressed.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

3 is a cross-sectional view showing a semiconductor device according to the present invention.

Specifically, a buzz beak oxide film 102a defining an active region is formed in the semiconductor substrate 201, for example. The P + region 216 and the N + region 215 are formed near the surface of the substrate 201, and the gate insulating layer 209, the polysilicon 210, and the fourth insulating layer 211 are formed on the substrate 201. A gate electrode is provided and both sidewalls are surrounded by a spacer 214. In addition, a fifth insulating layer 217 that insulates the gate electrode is formed, and a metal layer 218 is formed on the entire surface of the exposed substrate.

The titanium layer 219 is formed by implanting impurity ions into a predetermined region of the substrate 201.

4A to K are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Referring to the drawings, the semiconductor substrate 201, the first insulating film 202, the burj bevy oxide film 202a, the first nitride film 203, the second insulating film 204, the second nitride film 205, and n Well 206, device isolation film 207, third insulating film 208, gate insulating film 209, polysilicon 210, fourth insulating film 211, N-region 212, P-region 213 , The spacer 214, the N + region 215, the P + region 216, the fifth insulating layer 217, the metal wiring layer 218, the titanium layer 219, and the P well 220.

The 4a to h degrees are the same as the processes of the 2a to h degrees described in the prior art.

FIG. 4i illustrates a process of forming a titanium (Ti) layer and an N + region, and FIG. 4h illustrates an example of forming a spacer 214 made of a high temperature oxide film by anisotropically etching a high temperature oxide film on a sidewall of a gate electrode. A second process of coating a first process and a photoresist on the structure remaining after the first process and implanting titanium (Ti) ions on the exposed semiconductor substrate after the first process by patterning only the N + region 215. And a third process of implanting group 5 ions for forming an N + region.

In the second step, ion implantation of about 1.5 MeV is preferably performed using a gas such as titanium tetrachloride (TiCl ₄ ) such that the titanium layer 219 is formed at a depth of about 1 μm from the semiconductor substrate 201.

In addition to the titanium (Ti), tungsten (W), molybdenum (Mo), cobalt (Co), platinum (Pt), nickel (Ni), gold (Au), silver (Ag), copper (Cu), Mercury (Hg) ), Zinc (Zn) and the like can be used.

In the third step, the N + region and the P + region are preferably formed at a depth of about 0.3 μm or less from the semiconductor substrate.

FIG. 4J illustrates a process of forming the titanium layer 219 and the P + region 216. The first process of implanting titanium (Ti) ions onto the exposed semiconductor substrate after patterning the P + region 216. And a second process of implanting group III ions for forming the P + region 216.

The process of FIG. 4j follows the process of FIG. 4i.

Due to the titanium layer 219 formed after the processes 4i and 4j, the latch-up phenomenon generated in the semiconductor substrate may be suppressed.

4K is a cross-sectional view showing the final CMOS semiconductor device according to the embodiment of the present invention.

FIG. 4 (k) illustrates a first process of forming and patterning a fifth insulating layer 217 and a second process of forming a metal wiring layer 218 which is etched in a patterned form after depositing a metal.

According to the present invention described above, the recombination states of electrons and holes generated during the parasitic transistor operation in which the energy level of a material such as Ti is present in the silicon band gap and the CMOS enters the latch-up state. By acting as a center, the gain ratio of the parasitic bipolar transistor operation is lowered, thereby suppressing the latch-up occurrence.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

Claims (5)

Semiconductor substrates; An isolation layer formed in an island shape on the substrate; P ⁺ and N ⁺ regions formed in the surface of the substrate; A gate electrode formed on the active region of the substrate; Source / drain impurity regions formed in the substrate surface on both sides of the gate electrode; And an impurity implantation layer formed in the substrate by impurity ion implantation and formed to sufficiently surround the source / drain impurity region and the channel region. The semiconductor device according to claim 1, wherein the impurity energy level forming the impurity implantation layer uses an impurity existing between the energy band gaps of the substrate. The method of claim 1 or 2, wherein the impurities are titanium (Ti), tungsten (W), molybdenum (Mo), cobalt (Co), platinum (Pt), nickel (Ni), gold (Au), silver ( A semiconductor device characterized by selectively using among Ag), copper (Cu), mercury (Hg), and zinc (Zn). A method for manufacturing a CMOS bipolar transistor, comprising: selectively forming an isolation layer on a semiconductor substrate; Forming a gate electrode of an NMOS transistor and a gate electrode of a PMOS transistor on a substrate in an active region defined by the device isolation film; Forming an impurity layer for preventing latch-up in each of the gate electrodes and the substrate on both sides thereof; And forming source / drain impurity regions in the impurity layers on both sides of the gate electrode, respectively. The method of manufacturing a semiconductor device according to claim 4, wherein the junction position of the impurity layer is positioned between the source / drain impurity region of the NMOS transistor and the source / drain impurity region of the PMOS transistor.