KR970072398A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
KR970072398A
KR970072398A KR1019960010286A KR19960010286A KR970072398A KR 970072398 A KR970072398 A KR 970072398A KR 1019960010286 A KR1019960010286 A KR 1019960010286A KR 19960010286 A KR19960010286 A KR 19960010286A KR 970072398 A KR970072398 A KR 970072398A
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South Korea
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forming
substrate
region
semiconductor substrate
impurity
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KR1019960010286A
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Korean (ko)
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KR100205347B1 (en
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박민화
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문정환
Lg 반도체 주식회사
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222Bipolar technology
    • H01L21/8228Complementary devices, e.g. complementary transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

에너지 준위가 실리콘 포비든 밴드(forbiden band)내에 있는 불순물을 주입하여 CMOS에서 발생되는 바이폴라 동작의 이득율을 저하시킴으로써, LATCH-UP 현상을 억제시키기 위한 반도체 장치 및 그 제조방법을 개시한다. 이와같은 본 발명에 따른 반도체 장치는 반도체 기판, 상기 기판 상에 섬 모양으로 형성된 소자 분리막, 상기 기판의 표면 근방에 형성된 P+ 영역과 N+ 영역, 상기 기판 상에 게이트 절연막과 폴리 실리콘 및 절연막이 구비되고 양측벽이 스페이서로 감싸여진 게이트 전극, 상기 게이트 전극을 절연하는 절연막, 상기 노출된 기판 전면에 형성된 금속층 및, 상기 기판 내부의 소정영역에 불순물 이온 주입으로 형성된 불순물 주입층을 포함하여 이루어지고 그 제조방법은, 반도체 기판 상에 절연막 및 질화막을 순차적으로 형성하는 공정, 상기 반도체 기판 상에 웰을 형성하는 공정, 상기 반도체 기판 내에 NMOS 트랜지스턴간의 격리를 목적으로 하는 로커스 공정의 일부분으로서 채널 스톱 인플란테이션을 실시하는 공정, 상기 반도체 기판 내에 NMOS 및 PMOS의 문턱 전압(Threshold Voitage)을 조절해주는 이온 주입 공정, 상기 반도체 기판 상에 형성된 게이트 전극 측면에 LDD를 형성하는 공정, 상기 웰 영역내에 래치 업 방지를 위한 불순물층 형성 및 N+ 영역 및 P+ 영역을 형성하는 공정 및, 금속 배선층을 형성하는 공정을 포함하여 이루어진다.Disclosed is a semiconductor device and a manufacturing method thereof for suppressing a LATCH-UP phenomenon by lowering a gain rate of a bipolar operation generated in a CMOS by injecting an impurity having an energy level in a silicon forbidden band. The semiconductor device according to the present invention includes a semiconductor substrate, an element isolation film formed in an island shape on the substrate, a P + region and an N + region formed in the vicinity of the surface of the substrate, a gate insulating film, polysilicon and an insulating film on the substrate And an impurity implantation layer formed by implanting impurity ions into a predetermined region in the substrate, wherein the impurity implantation layer is formed by implanting impurities into the semiconductor substrate, The method includes the steps of sequentially forming an insulating film and a nitride film on a semiconductor substrate, forming a well on the semiconductor substrate, and forming a channel stop insulator as a part of a locus process for isolating NMOS transistors in the semiconductor substrate, Performing NMOS and PMOS in the semiconductor substrate; Forming an LDD on the side of the gate electrode formed on the semiconductor substrate; forming an impurity layer for preventing latch-up in the well region and forming an N + region and a P + region in the well region; And a step of forming a metal wiring layer.

Description

반도체 장치 및 그 제조방법Semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도는 본 발명에 의한 반도체 장치를 나타낸 단면도.FIG. 3 is a cross-sectional view showing a semiconductor device according to the present invention. FIG.

Claims (5)

반도체 기판; 상기 기판 상에 섬 모양으로 형성된 소자 분리막; 상기 기판의 표면 근방에 형성된 P+ 영역과 N+ 영역; 상기 기판 상에 게이트 절연막과 폴리 실리콘 및 절연막이 구비되고 양측벽이 스페이서로 감싸여진 게이트 전극; 상기 게이트 전극을 절연하는 절연막; 상기 노출된 기판 전면에 형성된 금속층; 및, 상기 기판 내부의 소정영역에 불순물 이온 주입으로 형성된 불순물 주입층으로 이루어진 것을 특징으로 하는 반도체 장치.A semiconductor substrate; An element isolation layer formed in an island shape on the substrate; A P + region and an N + region formed in the vicinity of the surface of the substrate; A gate electrode having a gate insulating film, polysilicon, and an insulating film on the substrate and having both side walls surrounded by spacers; An insulating film for insulating the gate electrode; A metal layer formed on the exposed surface of the substrate; And an impurity implantation layer formed by implanting impurity ions into a predetermined region in the substrate. 제1항에 있어서, 상기 불순물 주입층을 형성하는 불순물은 에너지 준위가 기판의 에너지 밴드 갭 사이에 존재하는 불순물을 이용하는 것을 특징으로 하는 반도체 장치.The semiconductor device according to claim 1, wherein the impurity forming the impurity implantation layer uses an impurity having an energy level between the energy band gaps of the substrate. 제1항 또는 제2항에 있어서, 상기 불순물은 티타늄(Ti), 텅스텐(W), 몰리브덴(Mo), 코발트(Co), 백금(Pt), 니켈(Ni), 금(Au), 은(Ag), 구리(Cu), 머큐리(Hg), 아연(Zn) 등을 이용하는 것을 특징으로 하는 반도체 장치.The method as claimed in claim 1 or 2, wherein the impurities are selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), cobalt (Co), platinum (Pt), nickel (Ni) (Ag), copper (Cu), mercury (Hg), zinc (Zn), or the like. 반도체 장치의 제조 방법에 있어서, 반도체 기판 상에 절연막 및 질화막을 순차적으로 형성하는 공정; 상기 반도체 기판 상에 웰을 형성하는 공정; 상기 반도체 기판 내에 NMOS 트랜지스터간의 격리를 목적으로 하는 로커스 공정의 일부분으로서 채널 스톱 인플란데이션을 실시하는 공정; 상기 반도체 기판 내에 NMOS 및 PMOS의 문턱 전압(Threshold Voitage)을 조절해주는 이온 주입 공정; 상기 반도체 기판 상에 형성된 게이트 전극 측면에 LDD를 형성하는 공정과; 상기 웰 영역내에 래치 업 방지를 위한 불순물층 형성, N+ 영역 및 P+ 영역을 형성하는 공정; 및, 금속 배선층을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 하는 반도체 장치의 제조 방법A method of manufacturing a semiconductor device, comprising: sequentially forming an insulating film and a nitride film on a semiconductor substrate; Forming a well on the semiconductor substrate; Performing channel stop implantation as part of a locus process aimed at isolation between NMOS transistors in the semiconductor substrate; An ion implantation process for controlling a threshold voltage of NMOS and PMOS in the semiconductor substrate; Forming an LDD on a side surface of the gate electrode formed on the semiconductor substrate; Forming an impurity layer for preventing latch-up in the well region, forming an N + region and a P + region; And a step of forming a metal wiring layer, 제4항에 있어서, 상기 불순물의 정션 위치를 웰 정션과 N+ 또는 P+ 영역 사이에 위치시키는 것을 특징으로 하는 반도체 장치의 제조 방법.5. The method of claim 4, wherein the junction position of the impurity is located between the well junction and the N + or P + region. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960010286A 1996-04-04 1996-04-04 Semiconductro and method of fabricating it KR100205347B1 (en)

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