GB2238658A - Integrated circuits - Google Patents

Integrated circuits Download PDF

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Publication number
GB2238658A
GB2238658A GB8926463A GB8926463A GB2238658A GB 2238658 A GB2238658 A GB 2238658A GB 8926463 A GB8926463 A GB 8926463A GB 8926463 A GB8926463 A GB 8926463A GB 2238658 A GB2238658 A GB 2238658A
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oxide film
nitrided
film
substrate
areas
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GB2238658B (en
GB8926463D0 (en
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P J Rosser
S R Jennings
P B Moynagh
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STC PLC
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STC PLC
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Publication of GB2238658B publication Critical patent/GB2238658B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation

Abstract

In a process for fabricating an integrated circuit, device areas are defined by a nitrided oxide mask. The remaining areas of the substrate are oxidised and the mask is then removed to allow the application of contacts, e.g. polysilicon emitter bodies, to the substrate. The process significantly reduces the extent of oxide incursion or 'bird's beak' at the edge of the mask. The nitriding of the oxide mask is effected by heating it in an ammonia atmosphere. <IMAGE>

Description

IMPROVEMENTS IN INTEGRATED CIRCUITS This invention relates to integrated circuits, and in particular to a process for fabricating integrated circuits.
A key step in the fabrication of an integrated circuit is that of definition of device features in which a conductive material, e.g. polycrystalline silicon contacts the semiconductor substrate. This process is a particular feature e.g. in the fabrication of circuits incorporating polysilicon emitter bipolar transistors.
The polysilicon emitter bipolar transistor is finding increasing use in the integrated circuit field, particularly in view of its compatibility with field effect processing in the manufacture of circuits commonly referred to as merged technology circuits, incorporating both field effect and bipolar devices on a common substrate chip. Circuits of this type are described for example in our published specification number GB-A-2172 744. An important step in the fabrication of a polysilicon emitter transistor is the definition of that region of the device that will receive the polysilicon emitter body. This is a body of polysilicon that contacts the semiconductor surface and forms the emitter of the transistor.
Typically circuit features of this nature may be defined by a nitride mask process. In this process a silicon nitride layer deposited on the semiconductor is patterned so as to mask those areas of the semiconductor that are to be contacted. The exposed semiconductor surface is then oxidised, the nitride mask preventing oxide growth in the masked regions. Subsequent removal of the nitride mask then provides openings exposing those regions to allow contact material, e.g.
polysilicon, to be applied to the semiconductor surface. A significant problem with this process is that of incursion of the grown oxide beneath the edge of the mask. This incursion is commonly known as bird's beak. To allow for the effects of this incursion, the nitride masked areas must be made somewhat larger than the device features that are to be formed. This limits the packing density of the devices. Where an integrated circuit incorporates a large number of devices the unusable semiconductor area resulting from this bird's beak effect becomes significant.
The object of the invention is to minimise this disadvantage.
According to the invention there is provided a process for masking a silicon semiconductor surface in the manufacture of an integrated circuit, the process including providing a first oxide film on said surface, nitriding said first oxide film, patterning said nitrided oxide film to define device areas, oxidising the substrate to grow a second oxide film in those areas unprotected by the patterned nitrided oxide film, and removing said patterned nitrided film to expose the semiconductor substrate in said device areas.
According to the invention there is further provided a process for fabricating a polysilicon emitter transistor on a semiconductor substrate, the process including applying to the substrate an oxide film, nitriding the oxide film, patterning the nitrided oxide film to define an emitter area, oxidising the substrate in a region surrounding said area, removing the patterned nitrided oxide film from said area, and applying a polysilicon emitter body to said area.
We have found that the use of a nitrided oxide mask provides a significant reduction in the extent of the bird's beak when the unmasked areas of the silicon substrate are oxidised. This in turn allows a higher device packing density to be achieved.
Embodiments of the invention will now be described with reference to the accompanying drawings in which: Figs. 1 to 7 illustrate successive stages in the fabrication of an integrated circuit via the nitrided oxide mask process; and Figs. 1 to 3 together with Figs. 8 to 10 and Fig. 7 illustrate a modification of the process of Figs. 1 to 7.
The process is described below with particular reference to the fabrication of a polysilicon emitter bipolar transistor, but it will be appreciated that this is by way of example only and that the process is of more general application in the semiconductor field.
Referring to Figs. 1 to 7 of the drawings, a lightly doped p -type single crystal silicon substrate 11 (Fig. 1) is provided with a heavily doped n -type region 12 . A lightly doped n -type epitaxial layer 13 (Fig. 2) then grown on the substrate 11 so that the n -type region 12 becomes a buried layer below the device area. A heavily doped n -type sinker 14 is provided to contact this buried layer 12 via the epitaxial layer 13. The sinker 14 subsequently forms the collector contact of the device. A lightly doped p -type region 15 is provided, e.g. by implantation in the surface of the epitaxial layer 13 above the buried region.
The surface of the epitaxial layer 13 is next coated with a thin oxide film 16 (Fig.3), e.g. by pulse heating the structure in an oxidisinq atmosphere. Such a process is described in our specification No.
GB-A-2172 746. This oxide film 16 is then nitrided to form a nitrided-oxide film 16a (Fig. 4) e.g. by pulse heating the structure in an ammonia atmosphere.
Typically, nitridation of the oxide film is performed by heating the structure to a temperature of 900 to 13000C for a period of 1 to 300 seconds. The nitrided oxide film has the composition SiOnNy where the values of n and y are determined by the processing conditions A photolithographic mask 18 (Fig. 5) is applied to the nitrided film 16a and the exposed portions of the film 16a are etched to leave a protective nitrided oxide layer 16b in the area of the device to which a polysilicon emitter will later be applied. Further nitrided oxide 16c is left in that area in which a contact to the sinker will subsequently be applied. The patterned nitrided oxide may also provide the gate insulation of one or more field effect devices (not shown) formed on the epitaxial layer simultaneously with the bipolar transistor.
The mask 18 is removed and oxide 19 (Fig.6) is grown on those areas of the epitaxial layer surface unprotected by the nitrided oxide. This oxide film 19 is grown to a thickness significantly greater than that of the nitrided oxide film 16b, 16c so that, when the structure is etched (Fig.7) the nitrided oxide film 16b, 16c is etched away completely to expose the underlying epitaxial layer whilst a significant proportion of the oxide 19 remains. The incursion of oxide growth beneath the edge of the nitrided oxide areas 16b, 16c is relatively small thus providing a significant reduction in 'bird's beak' incursion in comparison with conventional processes.
In a circuit construction involving the provision of field effect transistors, it will be appreciated that nitrided oxide areas providing the gate insulator for those transistors will be masked prior to the etching step.
Removal of the nitrided oxide areas 16b, 16c by the etching process provides a window 61 exposing the bipolar emitter contact area and a further window 62 defining the contact area for the sinker 14.
Polysilicon is deposited on the structure and is patterned to form an emitter body 63 in register with the window provided by removal of the nitrided film and a contact 64 in register with the sinker window 62.
Typically this polysilicon is doped and is of n -type conductivity. The emitter body 63 is then used as an -type alignment mask for the implantation of p -type regions 65 into the epitaxial layer 13. These p -type regions provide the base contact regions of the transistor.
Typically the structure is not coated with an insulating glass layer 70. Windows are opened in this glass layer and a patterned metallisation is applied to provide electrical contact (71, 72, 73) to the polysilicon emitter body 63, the base contact region 65 and the sinker contact 64 respectively.
Further polysilicon areas (not shown) may be provided to form the gate electrodes of field effect transistors where appropriate. These gate electrodes are used as source/drain implantation masks.
Referring now to Figs. 1 to 3 together with Figs. 8 to 10 and Fig. 7 there is illustrated a modification or variant of the process of Figs. 1 to 7.
The substrate 11 is ion implanted and provided with a surface nitrided oxide film 16a as described above with reference to Figs. 1 to 3. The nitrided oxide film 16a is then provided with a surface coating 17 (Fig. 8) of silicon nitride. A patterned photolithographic mask is applied to the surface of the silicon nitride film 17 and the exposed silicon nitride and underlying nitrided oxide are etched away to expose the substrate.
Stripping of the mask leaves the structure shown in Fig.
9 in which first (92a) and second (92b) islands comprising a lower layer of nitrided oxide and an upper layer of nitride are disposed respectively over the p-type layer 15 and the n±type sinker 14. Field oxide 19 (Fig. 10) is grown on the substrate surface regions unprotected by the islands 92a, 92b. The islands 92a and 92b are then removed and polysilicon 63, 64 (see Fig. 7) is applied to the exposed p-type layer 15 and the n -type sinker 14 respectively. The polysilicon body 63 is then used as an alignment mask for implantation of p -type base contact regions 65.
Finally, glass passivation abd metallisation are performed as described above.
It will be appreciated that although the process has been described above with particular reference to the fabrication of a polysilicon transistor, it is of general application to the fabrication of high density integrated circuits where the reduction of 'bird's beak' incursion provides a significant increase in packing density.

Claims (8)

1. A process for masking a silicon semiconductor surface in the manufacture of an integrated circuit, the process including providing a first oxide film on said surface, nitriding said first oxide film, patterning said nitrided film to define device areas, oxidising the substrate to grow a second oxide film in those areas unprotected by the patterned nitrided film, and removing said patterned nitrided film to expose the semiconductor substrate in said device areas.
2. A process for masking a silicon semiconductor surface whereby to define contact windows in the manufacture of an integrated circuit, the process including pulse heating the silicon semiconductor in an oxidising atmosphere to provide a first surface oxide film, pulse heating the oxidised semiconductor in an ammonia atmosphere to effect nitridation of said oxide film, selectively removing the nitrided oxide film to define contact window areas, growing an oxide film significantly thicker than the nitrided oxide film on those areas of the semiconductor surface from which the nitrided film has been removed, and etching the structure with a non-selective etchant to remove the nitrided film and expose the substrate in said contact window areas.
3. A process as claimed in claim 1 or 2, wherein a film of silicon nitride is provided on the nitrided oxide film prior to selective removal of the nitrided oxide film to define the contact window areas.
4. A process as claimed in claim 1, 2 or 3, wherein said first oxide film is nitrided by heating the silicon semiconductor in an ammonia atmosphere to a temperature of 900 to 13000C for a period of 1 to 300 seconds.
5. A process for fabricating a polysilicon emitter transistor on a semiconductor substrate, the process including applying to the substrate an oxide film, nitriding the oxide film, patterning the nitrided film to define an emitter area, oxidising the substrate in a region surrounding said area, removing the patterned nitrided film from said area, and applying a polysilicon emitter body to said area.
6. A process as claimed in Claim 5, wherein the nitrided oxide film provides the gate insulation of one or more field effect transistors formed simultaneously with the bipolar transistor.
7. A process for masking a silicon semiconductor surface substantially as described herein with reference to and as shown in Figs. 1 to 7 or Figs. 1 to 3 together with Figs. 8 to 10 and Fig. 7 of the accompanying drawings.
8. An integrated circuit incorporating polysilicon emitter transistors fabricated by a process as claimed in any one of the preceding claims.
GB8926463A 1989-11-23 1989-11-23 Improvements in integrated circuits Expired - Fee Related GB2238658B (en)

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GB2238658A true GB2238658A (en) 1991-06-05
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19625404B4 (en) * 1995-06-28 2005-12-29 Hyundai Electronics Industries Co., Ltd., Ichon Method for producing a field oxide layer in a semiconductor device

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1457139A (en) * 1973-09-27 1976-12-01 Hitachi Ltd Method of manufacturing semiconductor device
GB1516264A (en) * 1975-05-30 1978-06-28 Ibm Semiconductor devices
EP0001300A1 (en) * 1977-08-25 1979-04-04 Koninklijke Philips Electronics N.V. Method of manufacturing a LOCOS semiconductor device
EP0033495A2 (en) * 1980-02-01 1981-08-12 International Business Machines Corporation Process for fabricating a high speed bipolar transistor
US4580330A (en) * 1984-06-15 1986-04-08 Texas Instruments Incorporated Integrated circuit isolation
EP0208356A1 (en) * 1985-06-14 1987-01-14 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device, in which a silicon slice is locally provided with field oxide with a channel stopper
GB2192093A (en) * 1986-06-17 1987-12-31 Plessey Co Plc A local oxidation of silicon process
GB2198882A (en) * 1986-12-17 1988-06-22 Samsung Semiconductor Tele A method of semiconductor device isolation by lateral separation
EP0284456A1 (en) * 1987-02-24 1988-09-28 STMicroelectronics, Inc. Pad oxide protect sealed interface isolation process

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1457139A (en) * 1973-09-27 1976-12-01 Hitachi Ltd Method of manufacturing semiconductor device
GB1516264A (en) * 1975-05-30 1978-06-28 Ibm Semiconductor devices
EP0001300A1 (en) * 1977-08-25 1979-04-04 Koninklijke Philips Electronics N.V. Method of manufacturing a LOCOS semiconductor device
EP0033495A2 (en) * 1980-02-01 1981-08-12 International Business Machines Corporation Process for fabricating a high speed bipolar transistor
US4580330A (en) * 1984-06-15 1986-04-08 Texas Instruments Incorporated Integrated circuit isolation
EP0208356A1 (en) * 1985-06-14 1987-01-14 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device, in which a silicon slice is locally provided with field oxide with a channel stopper
GB2192093A (en) * 1986-06-17 1987-12-31 Plessey Co Plc A local oxidation of silicon process
GB2198882A (en) * 1986-12-17 1988-06-22 Samsung Semiconductor Tele A method of semiconductor device isolation by lateral separation
EP0284456A1 (en) * 1987-02-24 1988-09-28 STMicroelectronics, Inc. Pad oxide protect sealed interface isolation process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19625404B4 (en) * 1995-06-28 2005-12-29 Hyundai Electronics Industries Co., Ltd., Ichon Method for producing a field oxide layer in a semiconductor device

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GB8926463D0 (en) 1990-01-10

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