GB2192093A - A local oxidation of silicon process - Google Patents

A local oxidation of silicon process Download PDF

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Publication number
GB2192093A
GB2192093A GB08614667A GB8614667A GB2192093A GB 2192093 A GB2192093 A GB 2192093A GB 08614667 A GB08614667 A GB 08614667A GB 8614667 A GB8614667 A GB 8614667A GB 2192093 A GB2192093 A GB 2192093A
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Prior art keywords
oxide
layer
silicon
bird
mesa
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GB08614667A
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GB8614667D0 (en
GB2192093B (en
Inventor
Shane Duncan
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Plessey Co Ltd
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Plessey Co Ltd
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Priority to GB8614667A priority Critical patent/GB2192093B/en
Publication of GB8614667D0 publication Critical patent/GB8614667D0/en
Priority to US07/346,028 priority patent/US4909897A/en
Priority claimed from PCT/GB1987/000575 external-priority patent/WO1989001702A1/en
Publication of GB2192093A publication Critical patent/GB2192093A/en
Application granted granted Critical
Publication of GB2192093B publication Critical patent/GB2192093B/en
Expired legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

A LOCOS process crystal is modified by introducing a layer (11) of passive oxide deposit to cover the substrate (3), mesa and nitride capping layer (7) prior to the thermal growth of further oxide (13). The resulting oxide (13) is then etched back to remove excess material. This head height non-planarity and also in reduced bird's modification results in reduced bird's beak encroachment into the active area of the silicon device (3). Re-entrancy at the base of the bird's head (13) is also eliminated. <IMAGE>

Description

SPECIFICATION A local oxidation of silicon process TECHNICAL FIELD The present invention concerns improvements in or relating to processes which use local oxidation of silicon (LOCOS) to provide oxide isolation for silicon integrated circuit components.
Following the current demand for very large scale integration (VLSI) and therefore high packing densities, there is a need to scale down current feature sizes and thus to reduce the size and extent of isolating oxide structures.
The invention is intended to have application to processes for both bipolar and MOS device isolation.
BACKGROUND ART Local oxidation of silicon (LOCOS) has been the standard method of isolation for large-scale integration (LSI) and very large-scale integration (VLSl) circuits for approximately ten years. See, for example Appels, J.A., et al., Philips Research Reports Vol.25 (1970) pages 118-132 and also United Kingdom Patent No: 1208574.
However, several features of the technique have since been identified as having a detrimental effect on the final device structure. The lateral encroachment of the oxide into the active area (bird's beaking) severely limits the scalability of the device and an attempt to reduce this by decreasing the thickness of the field region will cause an increase in interconnect capacitance.
The standard LOCOS isolation technique currently employed involves recessing a silicon surface to form a mesa, and thermally oxidising the exposed silicon surface in steam. The top of the mesa is typically protected from oxidation by a nitride cap which is deposited on a thin stress relief oxide, to ensure minimal defect generation during oxidation. The topography presented by the isolation oxide can cause problems with photolithography prior to metal deposition, where multiple angle reflections from the bird's beak produces a 'necking' effect in subsequent metal depositions. Furthermore, the profile of the bird's head does not provide a suitable surface for metal coverage primarily due to a re-entrancy of the oxide at the bottom of the bird's head/field oxide region.The coupled effect of a large bird's head and a re-entrant step could present severe problems for metal continuity, where cracking or 'mouse-holing' may be evident.
Recently, several isolation techniques have been investigated in an attempt to minimise bird's beak encroachment and produce an almost planar surface - See for example Kuang, Yi, C., Moll, J.L., Manoliu, J., IEEE Trans, Electron Dev. vol. Ed-29, no. 4 April -1982; Tend, C., IEEE Trans.
Electron Devices vol. Ed-32, no. 2 Feb. 1985 and Hui, J., Voorde, P.V., Moll, J., IEDM 1985 p.392. In general, these methods involve complex processing steps and are often accompanied by a high defect density during oxidation.
DISCLOSURE OF THE INVENTION The present invention is intended to provide an alternative to the foregoing remedial processes, one that does not involve difficult processing operations. The aim of the inventive process, as disclosed below, is to provide a more ideal planar surface for subsequent metal coverage, this by reducing the step height of the bird's head/field oxide.
A further aim of the inventive process herein, is to suppress, or at least reduce, bird's beak encroachment, allowing thus more optimal use of the active areas enclosed within the boundaries of the field oxide isolation structure.
In accordance with the invention thus there is provided a local oxidation of silicon process, a process of the type wherein a capped single crystal silicon mesa is defined and thereafter an isolating structure of local field oxide is grown by thermal oxidation of the silicon; wherein, a layer of passive oxide is deposited upon the surface of the capped silicon prior to said thermal oxidation, and excess oxide removed thereafter by etching.
The inventive process disclosed here, addresses the problem of surface re-entrancy and bird's head height from two standpoints. Firstly, the deposited layer of oxide relies on being nonconformal to the silicon surface, and thus exaggerates the corners at the bottom and top of the mesa. Secondly, an oxide thickness '0.5,am will put oxidation kinetics in the parabolic regime thus effectively reducing any differential oxidation rate between (100) and (111) crystal planes.
The height of the bird's head is significantly reduced primarily due to visco-elastic flow of the oxide around the nitride edge. The presence of an oxide layer on the nitride allows a diffusion path for the expanding surface of oxidizing silicon.
BRIEF INTRODUCTION OF THE DRA WINGS In the drawings accompanying this specification Figs. 1 to 4 show substrate-and-structure cross-sections for successive stages of this inventive process. The stages shown in Figs. 1 and 2 are conventional.
DESCRIPTION OF PREFERRED EMBODIMENTS So that the invention may be better understood preferred embodiments thereof will now be described and reference will be made to the accompanying drawings. The description that follows is given by way of example only.
As in the conventional process, a mesa 1 is defined in a single crystal silicon substrate 3. As shown in Figs. 1 and 2 this is performed by growing a thin first layer 5, a layer of thermal oxide, at the surface of the substrate 3. In a typical process this layer 5 would be approx.
250A thick. This then is followed by the deposition of a second layer 7, a layer of an oxideetch resistance material, typically nitride. This is preferably somewhat thicker, typically approx.
1000 . In the case of nitride this may be performed by a low-pressure chemical vapour depositicn technique, the details of which are well known and not therefore detailed here. A layer 9 of resist is then spun onto the surface of the second layer 7. This then is selectively exposed and devloped and the exposed part of the second layer 7 removed by an anisotropic etch - for example, by a plasma. An illustrative cross-section of the substrate-and-structure at this stage of the process is shown in Fig. 1. The layer 9 of resist is now stripped off eg. by ashing and the remanent part of the second layer 7 is used as a mask during etch removal of the exposed oxide part of the first layer 5. This may be performed using a selective wet etchant - eg. hydrofluoric acid (HF).Exposed silicon material is then removed using an anisotropic wet etchant, for example, potassium hydroxide etchant isopropyl alcohol (KOH/IPA). This step of the process thus defines a mesa 1 with sloping walls. Typically, this etching step is continued until a depth of approx. 0.6#m of silicon is removed, which depth corresponds to the desired height of the mesa 1. This capped mesa 1 is shown in Fig. 2.
Then next step is a departure from the conventional process. At this stage; and thus prior to the growth of local oxide, a passive oxide deposition (POD) is performed. A layer 11 of lowpressure chemical vapour deposition (LP CVD) oxide is blanket deposited over the recessed mesa 1 and substrate 3. This deposited layer 11 typically can be approx. 0.5#m thick and is undoped. - See Fig. 3. In this figure, the labels Dox and HM are used to denote, respectively, the thickness (depth) of the deposited oxide layer 11, and, the height of the mesa 1 above the surrounding surface of the silicon substrate 3.
The final steps of this process then follow in manner similar to the conventional process. At this stage the silicon is oxidized by exposing the oxide covered structure to steam at a raised temperature. This, for example, can be conducted at a temperature of 1 0500C for a period of 8 hours, this allowing oxidation of the silicon to a depth of approx. 0.6,um. This may be compared with the standard process where typically oxidation is conducted at a temperature of 1 0000C and for a period of 721 hours. It will be noted that due to the presence of an initial thickness of oxide, oxide layer 11, either the temperature or the time, or both, are thus increased to allow consumption of the equivalent thickness of silicon.Excess oxide - typically the same in thickness as the thickness of the original deposited oxide layer 11, approx. 0.5cm, may then be removed by wet etching eg. using hydrofluoric acid (HF). Active areas then are exposed by wet etch removal of oxide-etch resistance material, eg. nitride 7, and of oxide material 5.
The bird's head/beak structure 13 is depicted in Fig. 4. In this Fig. an approximation to a profile produced by this process is shown in bold outline. By way of comparison, an approximate profile produced by conventional processing is also shown, but in broken outline. This thickness of the oxide, and, the penetration length of the "bird's beak" (as measured from the edge of the second layer 7) are depicted respectively by symbols T and B. The slope angle 0B of the "bird's head", as measured relative to the normal to the plane silicon surface, is also labelled.
The inventive process is not restricted to the dimensions specified above. In a series of experiments, conducted to characterise this modified process, various combinations of deposited oxide thickness Dox (0.25 and 0.5,am), thickness of the nitride layer 7 (500 and 1000 ) and thickness of the pad oxide 5 (375 and 1000A) were investigated. For these experiments the mesa height HM was in all cases 0.6Am. A measure-of-excellence parameter, B/T, - the ratio of beak length to oxide thickness, is tabulated for these combinations - See Table 1.By way of a guideline, a B/T value of 1.0 should be taken as typical for the conventional process; TABLE 1 Summary of B/T (-+0. 1) values determined by experiment
Dox 0. 25ism Dox = O.511m 3752 pad oxide 0.79 0.77 5002 nitride 37sR pad oxide 0.87 0.92 1000R nitide 1000k pad oxide 0.92 0.92 500R nitride book pad oxide 1.00 1.00 1000R nitride The improvements of reduced "bird's beak" encroachment is evident from these results especially for the lowest thickness of pad oxide and nitride (375A; 500A).
Micrograph examination also shows there to be considerable etch-back smoothing of the profile at the base of the bird's head. The angle 6B is found to be approx. 45 compared to an angle of 15 subtended by the bird's head after conventional processing. The step height of the bird's head is also found to be ~0.5, m, respresenting a 50% reduction compared with that found conventionally, typically ~1Am height.

Claims (4)

CLAIMS What we claim is:
1. A local oxidation of silicon process, a process- of the type wherein a capped single crystal silicon mesa is defined and thereafter an isolating structure of local field oxide is grown by thermal oxidation of the silicon; wherein, a a layer of passive oxide is deposited upon the surface of the capped silicon prior to said thermal oxidation, and excess oxide removed thereafter by etching.
2. A process, as claimed in claim 1, wherein the mesa is capped by a layer of pad oxide and on this a layer of nitride, each layer being of thickness 1000A or less.
3. A process, as claimed in claim 1, wherein the pad oxide and nitride layers are of thickness 375A or less and 500A or less, respectively.
4. A local oxidation of silicon process, when performed substantially as described hereinbefore with reference to and as shown in the accompanying drawings.
GB8614667A 1986-06-17 1986-06-17 A local oxidation of silicon process Expired GB2192093B (en)

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GB8614667A GB2192093B (en) 1986-06-17 1986-06-17 A local oxidation of silicon process
US07/346,028 US4909897A (en) 1986-06-17 1987-08-17 Local oxidation of silicon process

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GB8614667A GB2192093B (en) 1986-06-17 1986-06-17 A local oxidation of silicon process
PCT/GB1987/000575 WO1989001702A1 (en) 1987-08-17 1987-08-17 A local oxidation of silicon process

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GB2192093A true GB2192093A (en) 1987-12-31
GB2192093B GB2192093B (en) 1989-12-13

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989001702A1 (en) * 1987-08-17 1989-02-23 Plessey Overseas Limited A local oxidation of silicon process
US4909897A (en) * 1986-06-17 1990-03-20 Plessey Overseas Limited Local oxidation of silicon process
GB2238658A (en) * 1989-11-23 1991-06-05 Stc Plc Integrated circuits

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1300186A (en) * 1970-07-22 1972-12-20 Motorola Inc Method for passivating mesa pn junction structures
EP0137192A2 (en) * 1983-08-11 1985-04-17 Siemens Aktiengesellschaft Prevention of the diffusion of oxidation means during the manufacturing of semiconductor devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1300186A (en) * 1970-07-22 1972-12-20 Motorola Inc Method for passivating mesa pn junction structures
EP0137192A2 (en) * 1983-08-11 1985-04-17 Siemens Aktiengesellschaft Prevention of the diffusion of oxidation means during the manufacturing of semiconductor devices

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4909897A (en) * 1986-06-17 1990-03-20 Plessey Overseas Limited Local oxidation of silicon process
WO1989001702A1 (en) * 1987-08-17 1989-02-23 Plessey Overseas Limited A local oxidation of silicon process
GB2238658A (en) * 1989-11-23 1991-06-05 Stc Plc Integrated circuits
GB2238658B (en) * 1989-11-23 1993-02-17 Stc Plc Improvements in integrated circuits

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Publication number Publication date
GB8614667D0 (en) 1986-07-23
GB2192093B (en) 1989-12-13

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732 Registration of transactions, instruments or events in the register (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19970617