GB2215098A

GB2215098A - Memory mapping device

Info

Publication number: GB2215098A
Application number: GB8803382A
Authority: GB
Inventors: Allan Mcintosh
Original assignee: Individual
Current assignee: Individual
Priority date: 1988-02-13
Filing date: 1988-02-13
Publication date: 1989-09-13
Anticipated expiration: 2008-02-13
Also published as: GB2215098B; GB8803382D0

Abstract

A memory mapping device has a cell arrangement 15 which facilitates data mapping between memory cells 12, 14. The arrangement is of particular use in a data transfer application such as in a video processor and screen display. A first group of data is stored in an array in the first memeory area. When storage is completed the data in the stored area is copied, all at the same time, to a second storage area at a time when data is not being accessed from the second storage area. The data bits are transferred via tri-state switches 20, 26. The transfer may be unidirectional or bidirectional. <IMAGE>

Description

MEMORY MAPPING DEVICE The present invention relates to a memory mapping device and particularly, but not exclusively, to a memory mapping cell arrangement which facilitates data mapping between memory cells for use in a data transfer application such as in a video processor and screen display.

The central processor of a computer produces data to set up a screen to be displayed by a video processor.

The image to be displayed is stored in a common random access memory (RAM) area and the central processor writes the image data into this RAM. The video processor reads the data from this common RAM area and sets up the "screen" display.

A computer display system should satisfy a number of desirable criteria in addition to being efficient and relatively inexpensive. For example, update flickering or "flashing" of the image on the screen should be minimised.

Existing computer display systems use certain types of update methods, by, for example, synchronising the display RAM with the vertical refresh. However, the refresh rate must be faster than the frame or screen update cycle to prevent "flickering" caused by the new image interfering with the old image. To prevent flickering the old image must be cleared, and the new image drawn when the screen is not being refreshed i.e.

vertical retrace. Thus the software must be synchronised with the refresh rate (video display hardware). Such video processors thus require complex hardware chips which are expensive and require considerable software overheads.

Attempts to overcome these disadvantages have been made. For example, updating the RAM when the screen is not being updated, however, this technique is very slow.

Another proposed solution was to use two screen images and to swap between the images. This stopped the flickering of the image but used up the processor memory map and also it was necessary to update two memory areas instead of one.

An object of the present invention is to obviate or mitigate at least one of the aforementioned disadvantages.

This is achieved by providing a memory mapping device in which a first group of data is stored in an array in a first memory area, and when storage is completed the data in the stored area is copied, all at the same time, to a second storage area at a time when the data is not being accessed from the second storage area.

In a preferred embodiment the device is used with an image display system such as a VDU. A main processor is coupled to a first memory array and a video processor is coupled to a second memory array. The first and second arrays are disposed in the same device. The first array consists of a plurality of memory cells each of which contains one bit of information and each of which has a corresponding memory cell in the other array. The second memory cell array stores the information for the video processor to display on the VDU screen. In use, the main processor updates first memory cell array until it completes the new image to be displayed.Once this is achieved all the stored image information is then copied simultaneously to the second memory cell array of the video processor, at a time when it is not being accessed, for example, during vertical retrace, thus instantly updating the whole screen.

The image is copied in a very small period of time and so the image is displayed flicker free.

According to a first aspect of the present invention there is provided a memory mapping element for ase with a memory mapping device, said element comprising a first cell of a first array for storing a bit of data, a second cell of a second array coupled to said first cell, said second cell being adapted to store a bit of data therein and data transfer means coupled between said first and second cells for controlling the transfer of data between said first cell and said second cell in response to a control signal applied thereto.

Preferably, said data transfer means is provided by two parallel unidirectional switches which receive said control signals.

conveniently, said unidirectional switches are tri-state logic elements and said control signals are provided on enable lines of said tri-state logic elements.

Alternatively, one switch is provided for unidirectional data mapping between said first and said second cells.

Preferably also, said first and second cells are static memory cells.

Alternatively, said first and second cells are dynamic memory cells.

Preferably also, each cell in each array is coupled to common input and output data lines through respective switches, said switches being controllable to provide means by which the memory cells are coupled to a common data bus to permit data to be transferred to or from each cell.

Preferably also, said logic switches are tri-state logic elements.

According to a second aspect of the present invention there is provided a memory mapping device comprising a first array of memory cells, each of said memory cells being adapted to store a bit of data, and a second array of memory cells, each of said memory cells being adapted to store a bit of data, each of said memory cells in said first array being coupled to a corresponding memory cell in said second array, each pair of said corresponding cells forming a memory mapping element, data transfer means coupled between the first and second cells of each memory mapping element for controlling the transfer of data between cells of the respective arrays in response to a control signal applied to said transfer means, said control signal actuating the data transfer means when the second array is not being accessed by an external processor so that all the data is transferred between each memory element substantially simultaneously.

Preferably, data transfer from all cells in said first or second array is unidirectional.

Preferably also, said data transfer means is provided by a plurality of data transfer elements, each data transfer element being coupled to respective memory cells, each of said data transfer elements being actuated simultaneously by a control signal to provide simultaneous data transfer of data stored in one array to the other array.

According to a third aspect of the present invention there is provided a method of mapping data from a first memory area to a second memory area comprising the steps of; storing data in said first area; monitoring the operation of the second processor until a desirable data transfer time occurs; transfer data from the first area to the second area simultaneously at said desirable time; preventing access to said first memory area and the second memory area, until all data is stored in the second area.

Preferably, data flow is bidirectional between said first and second memory areas.

Alternatively, data flow is unidirectional between said first and second memory areas.

Alternatively also, data may be exchanged between said first and second memory areas by switching data buses in the device.

Preferably also, said data is transferred simultaneously from a plurality of first cells to corresponding second cells.

Preferably also, signals are applied to each switch coupling cells in an array to input and output buses to permit data to be transferred to or from each cell.

Preferably also, the first array of memory cells is coupled to a main processor and the second array of memory cells is coupled to a video processor for providing instantaneous update of a video screen by simultaneous transfer of data from the first array to the second array.

These and other aspects of the present invention will become apparent from the following description when taken in combination with the accompanying drawings in which: Fig. 1 is a schematic view of an embodiment of a memory mapping device in accordance with the present invention; Fig. 2 is a schematic view of a memory mapping element used with the device shown in Fig. 1; Fig. 3 is a schematic view of various logic controls associated with the memory element shown in Fig. 2; Fig. 4 is a schematic view similar to Fig. 1 of another embodiment of a memory mapping device in accordance with the present invention, and Fig. 5 is a schematic view similar to Fig. 1 of a third embodiment of a memory mapping device in accordance with the present invention.

Reference is first made to Fig. 1 of the drawings which is a schematic view of an embodiment of a memory mapping device used in a visual display system such as a visual display unit. A memory mapping device generally indicated by reference numeral 10 comprises a first array of memory cells AF and a second array of memory cells B.

The array A is connected to and controlled by a main processor tl and the array B is connected to and controlled by a video processor +2. Arrays A and B contain a large number of memory cells and each cell can store one bit of information. As shown schematically in Fig. 1 data can be transferred between arrays A and B as will be later described in detail.

Reference is now made to Fig. 2 which illustrates that each memory cell 12 in array A has a corresponding memory cell 14 in array B forming a memory mapping element 15. Processor tl can input and output data to array A and also processor t2 can input and output data to array B.

The cells of each element are connected through tri-state buffers 16 to an input data bus 19 and to an output data bus 21 which are external to the element which transfer data to and from each cell in the buses in accordance with control signals (addresses) applied to the switches 16. The output 18 of first cell 12 is connected through a transfer device in the form of a tri-state buffer 20 to the input 22 of the second cell 14. Similarly the output 24 of the second cell 14 is connected through a similar buffer 26 to the input 28 of first cell 12. These tri-state buffers 20 and 26 have control lines TAB and TBA respectively. When a logic enable is applied to the control lines, data transfer is permitted along the data lines on which buffers 20 and 26 are connected.

Several logic controls to each memory cell are shown which connect the memory cell to its associated processor. These logic controls are an enable control line, E, a Read/Write control line, R/W, and a clock control line, C. Lines E, R/W, C and TAB, TBA carry control signals which control data transfer between the cells 12,14 to perform a memory mapping operation as will be described with reference to Fig. 3.

Referring now to Figs. 2 and 3, each cell can store one bit of data which can be written into the cell via data bus 19 and the address control line of switch 16.

Fig. 3 shows the coupling between the logic controls external to the memory element and internal logic controls of the circuit shown in Fig. 2.

It should be understood that arrays A and B operate independently and the logic controls shown in Fig. 3 for A and B are also independent. However, the operation for one cell 12 will be described although it will be appreciated that the operations are identical for the other cell 14. Cell 12 is enabled 'E12'if a high signal is present on AddrA, TAB, or TBA. The cell 12 can then be written to or read from on line R/W12 if a high signal is received on line R/WA or on TAB. The R/w12 signal causes data to be read from cell 12 or written to cell 14 depending on the logic configuration. For example, a 'hi' signals means 'read from' and a 'lo' signal means 'write to'. However all data in the separate cells 12 is written to cells 14 when an active 'hi' clock signal is provided on clock input C of each cell 14.

The entire data content of either array can be transferred to the other array in a single clock cycle.

In this application of the system to the video processor +2, the data for a complete screen to be refreshed is transferred from the memory array A to the memory area B for use by the video processor in one clock cycle. The data for the new image to be displayed is updated by main processor #1 and stored in array A and then transferred to array B instantaneously, but only when desirable, i.e.

during vertical retrace.

Reference is now made to Figs. 4 and 5 of the drawings which show other embodiments of the memory mapping device in accordance with the present invention.

In Fig. 4 a unidirectional data mapping system is depicted where array A can only transfer data to array B. This is also sufficient for the video processor application as described above. In Fig. 5 a dual-mapping or data exchange system is depicted where data stored in array A is transferred to array B while the data stored in array B is simultaneously transferred to array A.

This is readily implemented exchanging the address buses.

Various modifications can be made to the embodiments described without departing from the scope of the invention. For example, two or more arrays of memory cells may be provided to allow mappings from an array(s) to other array(s) within the same device to allow for multi-tasking operations to be performed. The tri-state buffers used to connect corresponding memory cells in each mapping element may be replaced by an appropriate switching mechanism such as a transistor.

Advantages associated with the embodiments hereinbefore described are that, for a video application, the whole screen is updated simultaneously thus preventing update flickering. The main processor speed is maintained in the system to prevent "flashing" and software overheads are considerably reduced due to the simplicity of the system.

Claims

1. A memory mapping element for use with a memory mapping device, said element comprising a first cell of a first array for storing a bit of data, a second cell of a second array coupled to said first cell, said second cell being adapted to store a bit of data therein and data transfer means coupled between said first and second cells for controlling the transfer of data between said first cell and said second cell in response to a control signal applied thereto.

2. An element as claimed in claim 1 wherein said data transfer means is provided by two parallel unidirectional switches which receive said control signals.

3. An element as claimed in claim 2 wherein said unidirectional switches are tri-state logic elements and said control signals are provided on enable lines of said tri-state logic elements.

4. An element as claimed in claim 2 wherein one switch is provided for unidirectional data mapping between said first and said second cells.

5. An element as claimed in any preceding claim wherein said first and second cells are static memory cells.

6. An element as claimed in any one of claims 1-5 wherein said first and second cells are dynamic memory cells.

7. An element as claimed in any preceding claim wherein each cell in each array is coupled to common input and output data lines through respective switches, said switches being controllable to provide means by which the memory cells are coupled to a common data bus to permit data to be transferred to or from each cell.

8. An element as claimed in claim 7 wherein said logic switches are tri-state logic elements.

9. A memory mapping device comprising a first array of memory cells, each of said memory cells being adapted to store a bit of data, and a second array means coupled between the first and second cells of each memory mapping element for controlling the transfer of data between cells of the respective arrays in response to a control signal applied to said transfer means, said control signal actuating the data transfer means when the second array is not being accessed by an external processor so that all the data is transferred between each memory element substantially simultaneously.

10. A memory mapping device as claimed in claim 9 wherein data transfer from all cells in said first or second array is unidirectional.

11. A memory mapping device as claimed in claim 9 or claim 10 wherein said data transfer means is provided by a plurality of data transfer elements, each data transfer element being coupled to respective memory cells, each of said data transfer elements being actuated simultaneously by a control signal to provide simultaneous data transfer of data stored in one array to the other array.

12. A method of mapping data from a first memory area to a second memory area comprising the steps of a method of mapping data from a first memory area to a second memory area comprising the steps of; storing data in said first area; monitoring the operation of the second processor until a desirable data transfer time occurs; transfer data from the first area to the second area simultaneously at said desirable time; preventing access to said first memory area and the second memory area, until all data is stored in the second area.

13. A method as claimed in claim 12 wherein data flow is bidirectional between said first and second memory areas.

14. A method as claimed in claim 12 wherein data flow is unidirectional between said first and second memory areas.

15. A method as claimed in claim 12 wherein data may be exchanged between said first and second memory areas by switching data buses in the device.

16. A method as claimed in any one of claims 12-15 wherein said data is transferred simultaneously from a plurality of first cells to corresponding second cells.

17. A method as claimed in any one of claims 12-16 wherein signals are applied to each switch coupling cells in an array to input and output buses to permit data to be transferred to or from each cell.

18. A method as claimed in any one of claims 12-17 wherein the first array of memory cells is coupled to a main processor and the second array of memory cells is coupled to a video processor for providing instantaneous update of a video screen by simultaneous transfer of data from the first array to the second array.

19. A memory mapping device substantially as hereinbefore described with reference to Figs. 1 to 3 or to Figs. 4 or to Fig. 5 of the accompanying drawings.

20. A method of mapping data substantially as hereinbefore described.

21. A memory mapping element substantially as hereinbefore described with reference to Figs. 1 to 3 or to Fig. 4 or to Fig. 5 of the accompanying drawings