GB2131581A

GB2131581A - Dual processor arrangement

Info

Publication number: GB2131581A
Application number: GB08329805A
Authority: GB
Inventors: Richard John Ogden
Original assignee: Fujitsu Services Ltd
Current assignee: Fujitsu Services Ltd
Priority date: 1982-11-20
Filing date: 1983-11-08
Publication date: 1984-06-20
Also published as: GB2131581B; GB8329805D0

Abstract

A data processing system includes microprocessors 10 and 11. The microprocessor 10 normally accesses a bus 12 but sometimes needs to access a bus 13. The microprocessor 11 only accesses the bus 13. When it wishes to do so it issues a request signal REQ on a line 18 and proceeds with the access when it receives an acknowledgement signal ACK on a line 19. During the times when the microprocessor 10 does not wish to access the bus 13 it sets a bistable 20 and subsequent request signals from the microprocessor 11 are switched straight back as the acknowledgement signal by a gate 21 which connects the line 18 to the 19. When the microprocessor 10 wishes to access the bus 13 it tests for the presence of a request signal from the microprocessor 11 (which is maintained during an access) and only if it is absent clears the bistable 20, prevent subsequent requests being acknowledged and allowing the microprocessor 10 to access the bus 11. <IMAGE>

Description

SPECIFICATION Data processing system Background to the invention This invention relates to data processing systems. The invention is particularly con cerned with a system comprising two proces sors which share some resource (e.g. a bus or a a memory).

In such an arrangement, some means must usually be provided for controlling access to the shared resource, so as to ensure that only one of the processors can access it at any given time.

One way of achieving this would be for one of the processors to act as a master and the other as a slave in the following manner.

Normally, only the master is allowed to access the shared resource. When the slave requires to access the resource, it sends a request signal to the master. If the master does not currently require to use the resource, it responds with an acknowledgement signal, permitting the slave to go ahead and access the resource. However, a disadvantage of such an arrangement is that operation of the master may continually be interrupted by the slave, and the slave is delayed while waiting for the master to process the interrupt and determine if it may grant the request.

One object of the present invention is to avoid this disadvantage.

Summary of the invention According to the invention there is provided a data processing system comprising first and second processors connected to a shared resource, the second processor having a request output for producing a request signal when it wishes to access the resource and an acknowledgement input for receiving an acknowledgement signal permitting it to access the resource, a bistable element which is set by the first processor whenever it does not require to use the resource, and switching means controlled by the bistable element in such a manner that, when the bistable element is set, the switching means connects the request output of the second processor to its acknowledgement input.

Thus, it can be seen that when the bistable element is set, the switching means feeds each request signal without delay back to the second processor as an acknowledgement, permitting the second processor to access the resource without interrupting the first processor.

In a preferred embodiment of the invention, one or each processor may compose a microprocessor.

Preferably a request signal produced when the second processor wishes to access the resource continues to be produced until after the requested access has been completed and the first processor has means for inspecting the request output of the second processor to determine whether a request signal is present.

This permits the first processor to check whether the second processor is currently ac cessing the resource, before resetting the bis table element, so as to avoid interrupting the second processor in the middle of some oper ation.

Brief description of the drawing One embodiment of the invention will now be described by way of example with refer ence to the accompanying drawing which is a block diagram of a data processing system in accordance with the invention.

Description of the embodiment of the inven tion Referring to the drawing, the data process ing system comprises first and second micro processors 10 and 11, connected to respec tive busses 12 and 13. The busses are coup led together by means of a buffer 14, permit ting the inicroprocessor 10 to access the bus 13 by way of the bus 12. Other devices 15, 16 are connected to the busses as shown; these devices may for example be memories, communications controllers or peripheral de vice controllers.

The internal structure of the microproces sors 10, 11 and the devices 15, 16 forms no part of the present invention and in any case such units are well known in the art, and so it is not necessary to describe any of these units in detail herein.

In operation, the first microprocessor 10 normally uses only the first bus 12, but may from time to time require to access the second bus 13, to enable it to communicate with one of the devices 16 connected to that bus. The second microprocessor 11 may only access the second bus 13. The bus 13 is thus a resource which is shared between the two microprocessors.

When the second microprocessor 11 re quires to use the bus 13, it issues a request signal REQ from a request output 18. This microprocessor is permitted to use the bus 13 only when it receives an acknowledgement signal ACK at an input 19.

When the first microprocessor 10 does not require to use the bus 13, it sets a bistable 20. This enables an AND gate 21, which connects the request output 18 of the second microprocessor to its acknowledgement input 19. Thus whenever the second microproces sor issues a request signal REQ, it immedi ately receives an acknowledgement signal ACK, permitting it to go ahead and access the bus 13, without interrupting the first micro processor. The request signal is maintained until the bus access has been completed.

When the first microprocessor 10 requires to use the bus 13, it first produces a test signal TEST. This enables an AND gate 22, connecting the request output 18 of the second microprocessor to a line 23 which leads back to the first microprocessor. Thus, the first microprocessor can inspect the state of the request output 18, to find out whether the second microprocessor is currently using the bus 13. If it is, the first microprocessor waits until the request signal is no longer produced at the request output 18. Microprocessor 10 then resets the bistable 20 (by a line not shown), preventing the reception of any acknowledgement signals at the input 19, and then proceeds to access the bus 13 as required.

When the first microprocessor is finished with using the bus 13, it sets the bistable 20 again and, as before, the second microprocessor can now access the bus 13 whenever it produces a request signal.

As the system has been described so far, it has been assumed that the microprocessors 10 and 11 have been provided with specialpurpose output terminals. However, if such terminals are not provided the appropriate signals may be obtained by providing logic to decode address signals produced by the microprocessor concerned. This approach is especially convenient in the case of the microprocessor 10, because it allows the bistable 20 to be set (and cleared in a similar manner) without the need to dedicate terminals for the purpose.

The lines 19 and 23 may on many microprocessors be applied to a READY input provided to allow a memory or peripheral to indicate that it is ready to receive or send data.

Claims

1. A data processing system comprising first and second processors connected to a shared resource, the second processor having a request output for producing a request signal when it wishes to access the resource and an acknowledgement input for receiving an acknowledgement signal permitting it to access the resource, a bistable element which is set by the first processor when ever it does not require to use the resource, and switching means controlled by the bistable element in such a manner that, when the bistable element is set, the switching means connects the request output of the second processor to its acknowledgement input.

2. A system as claimed in Claim 1, in which one or each processor comprises a microprocessor.

3. A system as claimed in Claim 1 or Claim 2, in which a request signal produced when the second processor wishes to access the resource continues to be produced until after the requested access has been com pleted and the first processor has means for inspecting the request output to determine whether a request signal is present.

4. A data processing systemsubstantially as hereinbefore described with reference to and as shown in the accompanying drawing.