JPH05204841A - Bus for information processor - Google Patents

Abstract

PURPOSE:To optimize the use efficiency of an address bus and a data bus while executing one bus transaction separately as an address transfer phase and a data transfer phase by employing a specific system. CONSTITUTION:The bus consisting of signal lines 101-111 employs the system wherein the address bus and data bus are not multiplexed, and the bus use right and arbitration of the address bus and the bus use right and arbitration of the data bus and arbitration are independent. A bus connection device 11 when performing split transfer does not obtain the right to use the data bus in the data transfer phase. For nonsplit transfer, a request to obtain both the right to use the address bus and the right to use the data bus at the same time is made through a simultaneous bus request line 109 and a bus arbiter 12 gives two kinds of bus use right at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus used in an information processing device such as a personal computer, a workstation or an office computer.

[0002]

2. Description of the Related Art A conventional information processing device bus having a so-called split transfer means for dividing a bus transaction into an address transfer phase and a data transfer phase, each of which is completed independently, is, for example, EE EE, Draft Standard P
896.1R / D8.2: Future Bus Plus Logical Layer Specifications (1990)
Year) Page 49 to page 75 (IEEE Draft S
standard P896.1R / D8.2: Futu
rebus + Logical Layer Spec
informations, IEEE Computer
Society Press (1990) PP49-7
The future bus plus described in 5) is known.

[0003]

With the recent increase in the speed of information processing devices, there has been a great challenge to increase the speed of the information processing device bus as well as the bus utilization rate. This means is drawing attention as an effective means for improving the bus usage rate.

The above-mentioned prior art is a bus of a system in which an address bus and a data bus are multiplexed. In the address transfer phase, an address is output on the multiplexed bus, and in the data transfer phase, the address is first written on the multiplexed bus. Is output, and then the data is output. In this case, the correspondence between the address transfer phase and the data transfer phase of one bus transaction can be known by the coincidence of the addresses output in both phases.

Conventionally, there is no known bus that does not multiplex the address bus and the data bus, and has a means for dividing a bus transaction into an address transfer phase and a data transfer phase that complete independently. Many commercial LSIs such as CPUs have an external bus that does not multiplex the address bus and the data bus, and are buses that do not multiplex the address bus and the data bus. There is a demand for a bus having means for performing the address transfer phase and the data transfer phase which are completed.

[0006] The above-mentioned conventional split transfer means is used for a bus of a system in which an address bus and a data bus are not multiplexed.
That is, if the means for dividing the bus transaction into the address transfer phase and the data transfer phase, which are independently completed, is applied as it is, the data bus is not used in the address transfer phase, and the address bus and the data bus are simultaneously used in the data transfer phase. Is not used, there is a problem that the bus is not used efficiently.

An object of the present invention is to improve the efficiency of use of the bus by dividing the bus transaction into an address transfer phase and a data transfer phase, each of which independently completes a bus transaction, in a bus in which the address bus and the data bus are not multiplexed. Is to be given in an optimized form.

[0008]

In order to achieve the above object, the present invention provides an address transfer phase and a data transfer phase in which bus transactions are independently completed in a bus in which an address bus and a data bus are not multiplexed. In addition to providing means for performing division, the bus use right and arbitration of the address bus and the bus use right and arbitration of the data bus are independent.

Further, in order to eliminate the need to output the address in the data transfer phase, a means for knowing the correspondence between the address transfer phase and the data transfer phase of one bus transaction is provided by information other than the address. The means is provided, for example, by adding a control line for outputting a code for identifying a bus transaction to each of the address bus and the data bus.

Further, in the case where both means for dividing the bus transaction into an address transfer phase and a data transfer phase, which are completed independently of each other, and a means for collectively executing the division without the division are provided, the bus transaction is performed. A device that uses a device is provided with a means to acquire the bus usage right of the address bus and the bus usage right of the data bus at the same time or with a specific time difference, and collectively acquires the bus usage right of the address bus and the bus usage right of the data bus. I was able to do it.

[0011]

In a bus of a method in which the address bus and the data bus are not multiplexed, by making the bus use right and arbitration of the address bus independent from the bus use right and arbitration of the data bus, an address that completes each bus transaction independently. When divided into a transfer phase and a data transfer phase, the address transfer phase acquires the bus use right of the address bus,
The data transfer phase can be performed by acquiring the bus use right of the data bus. At this time, by providing a means for knowing the correspondence between the address transfer phase and the data transfer phase of one bus transaction by information other than the address, it is not necessary to output the address in the data transfer phase, and the address transfer phase does not need to output the data. The bus can be used and the data transfer phase can be performed without using the address bus. This allows
A so-called pipeline operation can be performed in which the address transfer phase of a certain bus transaction and the data transfer phase of another bus transaction are performed in parallel at the same time, so that each bus transaction can be made independent to optimize bus usage efficiency. It can be divided into an address transfer phase and a data transfer phase which are completed.

If it is necessary to divide the bus transaction into an address transfer phase and a data transfer phase that are completed independently of each other, and to collectively perform the bus transaction without performing the division, the bus transaction is required. In addition to the means for the device that uses the address bus to acquire the bus usage right for the address bus and the bus usage right for the data bus independently, the bus usage right for the address bus And to be able to acquire the bus usage right of the data bus all at once.
As a result, it is possible to interrupt a bus transaction that collectively performs the address transfer phase and the data transfer phase during the pipeline operation.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block configuration diagram showing an example of a system configuration of an information processing apparatus using a bus according to the present invention, FIG.
Is a timing chart showing an example of timing specifications of a bus transaction of split transfer on the bus according to the present invention, FIG. 3 is a timing chart showing an example of timing specifications of a bus transaction of non-split transfer on the bus according to the present invention, and FIG. It is a circuit block diagram which shows the example of the bus arbiter circuit of the bus by this invention.

In FIG. 1, reference numeral 11 denotes N bus connection devices connected to a bus according to the present invention, examples of which include a CPU interface unit, a main memory control unit, an I / O control unit and the like. Reference numeral 12 is a bus arbiter of the bus according to the present invention. 1
Reference numerals 01 to 111 denote signal lines of the bus according to the present invention, 101 is an address bus (ADR), and 102 is a control code bus (A_COD) attached to the address bus.
E), 103 are timing control lines (A_TMG) attached to the address bus, 104 is a data bus (DATA),
Reference numeral 105 denotes a control code bus (D_C) attached to the data bus.
ODE), 106 is a timing control line (D_TMG) associated with the data bus, 107 is N address bus request lines (A_REQ), 108 is N data bus request lines (D_REQ), and 109 is N lines. Simultaneous bus request line (S_REQ), 110 is N address bus acknowledge lines (A_ACK), 111 is N data.
It is the Tabus acknowledge line (D_ACK).

In FIG. 1, N bus connection devices are connected to an address bus consisting of 101, 102 and 103 and a data bus consisting of 104, 105 and 106, respectively, and three types of 107, 108 and 109. The bus request line and the two types of bus acknowledge lines 110 and 111 are connected one by one. The bus arbiter 12 includes N bus connection devices and 107 and 108.
And 109 bus request lines and 110 and 1
Two types of 11 bus acknowledge lines are connected in a one-to-one manner by N lines, and two types of timing control lines 102 and 106 are connected. In the case of this figure, the bus arbiter 12 is a device independent of the N bus connection devices, but it is also conceivable that any one of the N bus connection devices has the bus arbiter 12 built therein.

The bus according to the present invention constituted by signal lines 101 to 111 in FIG. 1 is a system in which the address bus and the data bus are not multiplexed, and the bus use right of the address bus and the bus use of the arbitration and the data bus are used. Rights and arbitration are independent. When a bus connection device performs a split transfer that divides a bus transaction into an address transfer phase and a data transfer phase that complete independently, the address transfer phase acquires the bus use right of the address bus, and the data transfer phase performs data transfer. Acquire the right to use the bus. When performing non-split transfer that does not divide the bus transaction into an address transfer phase and a data transfer phase that are completed independently of each other,
The simultaneous bus request line 109 requests acquisition of the bus use right of the address bus and the bus use right of the data bus at the same time, and the bus arbiter 12 gives two types of bus use rights at the same time so that the address bus and the data bus are simultaneously provided. Use for non-split transfers.

The operations of split transfer and non-split transfer in this embodiment will be described below with reference to FIGS. 2 and 3. In FIG. 2 and FIG. 3, the timing control line 103 associated with the address bus and the timing control line 106 associated with the data bus are respectively the address output display signal (A_).
OUT) and an address receipt confirmation signal (A_IN), a data output display signal (D_OUT), and a data receipt confirmation signal (D_IN). Further, in FIGS. 2 and 3, all the control signals are shown as positive.

FIG. 2 is a timing chart showing an example of timing specifications of a bus transaction for split transfer on the bus according to the present invention.

In FIG. 2, the bus connection device 1 first outputs the address bus request signal A_REQ1 to request the right to use the address bus, and the bus arbiter outputs the address bus acknowledge signal A_ACK1 to acquire the right to use the address bus. The address (ADR), the control code (A_CODE) associated with the address bus, and the address output display signal (A_OUT) are output to execute the address transfer phase. At this time, in FIG.
The ADR (1) indicates that the bus connection device 1 is outputting the address, and the A_CODE code value (11
1) indicates that the transaction is a write transaction (1st in 100s), that it is the bus connection device 1 that outputs the address (1st in 10th), and the identification number of the transaction by the bus connection device 1. (1st place) is shown. The slave device specified by the address value receives the address receipt confirmation signal (A_I
N) is output to end the address transfer phase.

Subsequently, the bus connection device 1 outputs the data bus request signal D_REQ1 to request the right to use the data bus, and the bus arbiter outputs the data bus acknowledge signal D_ACK1 to acquire the right to use the data bus and obtain the data (DATA ), A control code (D_CODE) associated with the data bus, and a data output display signal (D_OUT) are output to execute the data transfer phase. At this time, in FIG. 2, since (1) of DATA is a write transaction, data is transferred to the bus connection device 1
Is output, and the code value (111) of D_CODE indicates the same value as the code value of A_CODE at the address transfer phase of the transaction.
The slave device designated by the value of the address in the address transfer phase of the transaction is D_CO
The correspondence between the address transfer phase and the data transfer phase is known from the code value of DE, write data is received, and a data reception confirmation signal (D_IN) is output to end the data transfer phase.

On the other hand, the bus arbiter has a value 11 of A_CODE.
When the address transfer phase of 1 is completed, the address bus request signal A_REQ2 is output to the bus connection device 2 which has requested the right to use the address bus, and the address bus acknowledge signal A_ACK2 is output to the right to use the address bus. Is giving. Bus connection device 2
Outputs ADR, A_CODE, and A_OUT to execute the address transfer phase. At this time, in FIG. 2, ADR (2) indicates that the bus connection device 2 is outputting the address, and the A_CODE code value (2
21) indicates that the transaction is a read transaction (hundreds of two), that it is the bus connection device 2 that outputs the address (tenths of two), and the transaction identification number by the bus connection device 2. (1st place) is shown.

The bus connection device 3 designated as the slave device by the value of the address first outputs the address receipt confirmation signal (A_IN) to end the address transfer phase, prepares the read data, and then sends the data bus request signal D_REQ3. It outputs the data bus to request the right to use the data bus, acquires the right to use the data bus by outputting the data bus acknowledge signal D_ACK3 by the bus arbiter, outputs DATA, D_CODE, and D_OUT to execute the data transfer phase. At this time, in FIG. 2, (3) of DATA indicates that the bus connection device 3 is outputting data because it is a read transaction, and the code value (221) of D_CODE is A_CODE at the address transfer phase of the transaction.
It shows the same value as the code value of. The bus connection device 2 that has generated the read transaction is D_CODE
The correspondence between the address transfer phase and the data transfer phase is known from the code value of 1, the read data is received, and the data reception confirmation signal (D_IN) is output to end the data transfer phase.

Further, the bus connection device 2 is D_CODE.
Before the data transfer phase of the code value 221 of the above is executed, the address transfer phase of another read transaction is started, and A_C in the address transfer phase is started.
The code value of ODE is 222. In this case, the correspondence number between the address transfer phase and the data transfer phase can be maintained one-to-one by changing the transaction identification number (2nd place) by the bus connection device 2.

Further, in the address transfer phase of the code value 222 of A_CODE, the bus connection device 1 designated as the slave device by the value of the address is D_C.
At the same time as executing the data transfer phase of the ODE code value 222, the address transfer phase of another read transaction is started.

As described above, in the present embodiment, the so-called pipeline operation, in which the address transfer phase of one bus transaction and the data transfer phase of another bus transaction are simultaneously performed in parallel, can be performed, so that the bus usage efficiency is improved. By optimizing the above, split transfer can be performed in which the bus transaction is divided into an address transfer phase and a data transfer phase that complete independently.

FIG. 3 is a timing chart showing an example of timing specifications of a bus transaction for non-split transfer on the bus according to the present invention. FIG. 3 shows a case in which split transfer and non-split transfer are mixed.

In FIG. 3, the bus connection device 2 is first shown in FIG.
The address transfer phase of split transfer is executed by the same procedure as. During execution of the address transfer phase, the bus connection device 1 outputs the simultaneous bus request signal S_REQ1 to perform the bus transaction of the non-split transfer, and simultaneously acquires the bus use right of the address bus and the bus use right of the data bus. Requesting that. In response to the request, the bus arbiter outputs the address bus acknowledge signal A_ACK1 and the data bus acknowledge signal D_ACK1 at the same time, thereby giving the bus connection device 1 the bus use right of the address bus and the bus use right of the data bus at the same time. ..

When the bus connection device 1 acquires the bus use right of the address bus and the bus use right of the data bus at the same time, the write transaction of the non-split transfer is AD.
R, A_CODE, and A_OUT and DATA, D_C
ODE and D_OUT are output at the same time. The hundred digit 3 of the code value means a non-split transfer write transaction. The slave device specified by the value of the address of the transaction is
First, A_IN is output to open the address bus, and then D_IN is output to open the data bus. A_I
The output of N and the output of D_IN may be simultaneous. A_
The output of both IN and D_IN completes the non-split transfer bus transaction. After releasing the address bus and the data bus, the bus arbiter gives the right to use the address bus to the bus connection device 2 and the right to use the data bus to the bus connection device 3. Bus connection device 3
Executes the data transfer phase corresponding to the address transfer phase executed by the bus connection device 2 before the bus transaction of the non-split transfer.

As described above, in the present embodiment, during the pipeline operation of the address transfer phase and the data transfer phase by the split transfer, the bus transaction of the non-split transfer which collectively performs the address transfer phase and the data transfer phase is interrupted. be able to.

FIG. 4 is a circuit diagram showing an example of a bus arbiter circuit of the bus according to the present invention, which is shown as the bus arbiter 12 in FIG. In FIG. 4, 40
1, 402, and 403 are priority encoders,
404 and 405 are comparators, 406, 407 and 408 are decoders, 409 and 410 are NOT gates, 411, 412 and 413 are N AND gates, respectively, 414, 415 and 416 are timing control circuits, and 417 and 418 are There are N OR gates each.
The operation of the bus arbiter 12 will be described below.

The bus arbiter 12 has N address bus request lines A_REQ, N data bus request lines D_REQ, and N simultaneous bus request lines S_RE.
Q, timing control line A_TM associated with the address bus
G, and timing control line D_T associated with the data bus
MG as an input signal, N address bus acknowledge lines A_ACK and N data bus acknowledge lines D_
Output ACK.

N output from N bus connection devices
The address bus request lines A_REQ, the N data bus request lines D_REQ, and the N simultaneous bus request lines S_REQ are input to the priority encoders 401, 402, and 403, respectively, and the request with the highest priority among the requests. Is output as a code. The output codes of the priority encoders 401 and 403 are compared by a comparator 404, and the output codes of the priority encoders 402 and 403 are compared by a comparator 405. When the output code of each priority encoder 403 has a higher priority, true is output. .. Priority encoder 4
The output codes of 01, 402, and 403 are input to decoders 406, 407, and 408, respectively, and N decoding results are output. Decode result corresponds to the highest priority request only if there is a request 1
True is output only to books.

409 and 410 are NOT gates 409 and 410, and N AND gates 411, 412, and 413 are logic filter circuits, respectively.
If the priority of the address bus request or the data bus request is higher than the priority of the simultaneous bus request from the N decoded results of 06, 407, and 408 and the comparison results of the comparators 404 and 405, respectively, the address bus request and the data are requested. The decode result is passed for the bus request with a higher priority than the simultaneous bus request, and if the priority of the simultaneous bus request is higher than the priority of the address bus request and the data bus request, the decode result is passed for the simultaneous bus request. It is designed to let you.

Timing control circuits 414, 415 and 4
16 and N OR gates 417 and 418, respectively,
When TMG and D_TMG are monitored and the address bus and the data bus become idle, N A_A each
Control is performed to change the states of CK and D_ACK.

The timing control circuit 414 monitors A_TMG and when the address bus becomes idle,
The N outputs for the address bus request are output from the output state up to that point, and the N AND gates 411 at that point are output.
To N decoding results input from.
The timing control circuit 415 monitors D_TMG, and when the data bus enters an idle state, inputs N outputs for the data bus request from the output state up to that point and inputs from the N AND gates 412 at that time. It is changed to the N decoded results. The timing control circuit 416 monitors A_TMG and D_TMG, and when both the address bus and the data bus are in an idle state, outputs N outputs for the simultaneous bus request from the output state up to that point until N times. AND gates 412
To N decoding results input from.
As a result, N acknowledge signals are generated for each of the address bus request, the data bus request, and the simultaneous bus request.

N OR gates 417 and 418, respectively
Are N outputs of the timing control circuit 414 and N outputs of the timing control circuit 416, and N outputs of the timing control circuit 415 and the timing control circuit 416, respectively.
Of the N output signals of the N bus signals, the N bus signals of the address bus request, the data bus request, and the simultaneous bus request, respectively.
Is generated and output.

As described above, the bus arbiter 12 receives the N address bus request lines A_REQ, the N data bus request lines D_REQ, and the N simultaneous bus request lines S_REQ from the N address bus acknowledge lines A_ACK and Arbitration control shown in FIGS. 2 and 3 can be performed by generating N data bus acknowledge lines D_ACK.

[0038]

According to the present invention, in a bus of a system in which an address bus and a data bus are not multiplexed, one bus transaction is separately executed into an address transfer phase and a data transfer phase which are independently completed. ,
It is possible to optimize the use efficiency of the address bus and the data bus.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an example of a system configuration of an information processing apparatus using a bus according to the present invention.

FIG. 2 is a timing chart showing an example of timing specifications of a bus transaction of split transfer on a bus according to the present invention.

FIG. 3 is a timing chart showing an example of timing specifications of a bus transaction of non-split transfer on a bus according to the present invention.

FIG. 4 is a circuit configuration diagram showing an example of a bus arbiter circuit of a bus according to the present invention.

[Explanation of symbols]

 11 ... N bus connection devices, 12 ... Bus arbiter, 101 ... Address bus, 102 ... Control code bus associated with address bus, 103 ... Timing control line associated with address bus, 104 ... Data bus, 105 ... Data bus Associated control code bus, 106 ... Timing control line associated with data bus, 107 ... N address bus request lines, 108 ... N data bus request lines, 109 ... N simultaneous bus request lines, 110 ... N address bus acknowledge lines, 111 ... N data bus acknowledge lines.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masatsugu Shinozaki 810 Shimoimazumi, Ebina City, Kanagawa Hitachi, Ltd. Office System Design and Development Center

Claims (6)

[Claims] 1. A bus for an information processing apparatus, which is a system in which an address bus and a data bus are not multiplexed, and a bus use right of an address bus and its arbitration means and a bus use right of a data bus and its arbitration means are independent. A bus for an information processing device characterized in that 2. The information processing device bus according to claim 1,
An information processing device bus characterized in that all bus transactions are divided into an independently completed address transfer phase and data transfer phase. 3. A bus for an information processing apparatus according to claim 1, wherein
A bus for an information processing apparatus, wherein a device using the bus has means for acquiring the bus use right of the address bus and the bus use right of the data bus at the same time or with a specific time difference. 4. The bus for an information processing device according to claim 3,
An information processing bus, comprising: means for separately performing an address transfer phase and a data transfer phase, each of which is independently completed, and means for collectively performing the bus transaction without performing the division. 5. The bus according to claim 1, 2, 3 or 4,
A bus for an information processing device, comprising means for knowing correspondence between an address transfer phase and a data transfer phase of one bus transaction by information other than an address. 6. An information processing apparatus having one or more buses according to claim 1, 2, 3, 4 or 5.