GB2098397A

GB2098397A - Semiconductor memory device

Info

Publication number: GB2098397A
Application number: GB8212113A
Authority: GB
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1981-05-13
Filing date: 1982-04-27
Publication date: 1982-11-17
Also published as: FR2506058B1; KR840000082A; FR2506058A1; IT1152129B; DE3217896A1; IT8221211A0; JPS57186354A

Abstract

The device comprises a memory cell (M-CEL) and a reference level generating cell (D-CEL), each cell including a responsive capacitor (Cs; Cds). The dielectric layer 3a which determines the capacitance of the capacitor Cs is made of a material different from that of the dielectric of capacitor Cds. The materials are preferably silicon nitride and silicon oxide. <IMAGE>

Description

SPECIFICATION Semiconductor memory device and fabrication method therefor The present invention relates to a semiconductor memory device, especially, a dynamic random access memory (which will be shortly referred to as "D-RAM"), which is composed of insulated gate type field effect transistors (which will be shortly referred to as "MISFET") and to a method of fabricating the same.

First of all, a D-RAM circuit, to which the present invention is applied, will be reviewed with reference to Fig. 1.

This D-RAM circuit is generally constructed, as shown in Fig. 1, to include a sense amplifier SA1, a memory array M-ARY, a dummy array D-ARY, a column switch C-SW1, a row and column decoder R and CDCR, an address buffer ADB, a data output buffer DOB, a data input buffer DIB and a main amplifier MA. Specifically, the memory cell M-CEL in the M-ARY is constructed to include a memory capacitor Cs for storing a charge correspond to the logic value of a logic signal, and a transfer MISFET QM having its gate made receptive of a word signal.On the other hand, a dummy cell (i.e., a reference level generating cell) D-CEL for providing a reference for level comparison with the M-CEL of the D-ARY is constructed to include a capacitor Cds having a half capacity as high as that of the aforementioned Cs, a transfer MISFET QD1 having its gate made receptive of a dummy word signal, and an MISFET QD2 to be used for discharging the aforementioned Cds.

Incidentally, the MISFETs asterisked in Fig. 1, e.g., Qs2 and Q53 are so designed that they have lower threshold voltages than the other MISFETs, e.g., Qs8 and 099. Thus, when in a precharging operation (i.e., when a precharge control signal sssPc at a predetermined level is impressed), the MISFETs 092 and Q53 have their conduction currents increased so that the voltage differences between their gates and sources are reduced.As a result, the MISFETs 092 and Q53 having lower threshold voltages are allowed to enjoy higher driving abilities for a floating capacitor CO acting as a load so that they can shorten the precharge time period the more than the case in which the MISFETs having higher threshold voltages, e.g., Qs8 and S99 are used as those for precharging the aforementioned floating capacitor CO.

Now, in order that the M-CEL and DCEL have their respective capacitors Cs and Cds related, as has been described hereinbefore, such that the capacity of the Cs: the capacity of the C#s=.2:l, their dielectric layers are made of an identical material such as an SiO2 film according to the prior art so that their area ratio may be expressed by the following Equation, i.e., the area S of the capacitor C5: the area Sd of the capacitor C#s=.2#l However, in case the area occupied by the M-CEL is intended to be reduced in accordance with the increase in the capacity of the D-RAM, the aforementioned means for changing the area ratio has the following problem.

Specifically, the area occupied by the M-ARY in one semiconductor substrate (i.e., a semiconductor chip) is at a remarkably high ratio.

In that M-ARY, moreover, the area, which is occupied by the capacitor C9 constructing the M CEL is also at a remarkably high ratio.

Consequently, if the area S of the capacitor C9 especially of the M-CEL is to be reduced in accordance with the increase in the capacity of the D-RAM, the area Sd of the capacitor Cds of the D-CEL has to be reduced the more from the requirement for the aforementioned setting the Equation of C,:D,,#2:1. Due to the dispersion in the fabrication such as the etching step, however, the fluctuation percentage of the area Sd of the capacitor Cds having about a half of the area S of the capacitor C9 becomes far higher than that of the area S of the capacitor C9 thereby to make it impossible to provide the capacitor Cds having about a half capacity of that of the capacitor Cs.

Therefore, there has been a limit to the reduction in the area of the capacitor C9.

According to a first aspect of the present invention there is provided a semiconductor memory device including; a memory cell including an MIS type FET and a capacitor both formed in the surface of a semiconductor substrate at a first predetermined region; and a reference level generating cell including a MIS type FET and a capacitor both formed in the substrate of said semiconductor substrate at a second predetermined region; wherein each of the capacitors, which are formed in said first and second predetermined regions, includes a dielectric film formed over a portion of the surface of said semiconductor substrate, and a conductor layer formed over said dielectric film; and wherein the dielectric film of said capacitor formed in said first predetermined region is made of a material different from that of the dielectric film of said capacitor formed in said second predetermined region.

According to a second aspect of the present invention there is provided a method of manufacturing a semiconductor device, including the steps of: forming a first insulating film in the surface of a semiconductor substrate in a manner to enclose both first and second predetermined regions of said semiconductor substrate; forming a silicon nitride film on said first predetermined region in order to determine the capacity of a first capacitor; forming a silicon oxide film on said second predetermined region simultaneously with the oxidization of the surface of said silicon nitride film in order to determine the capacity of a second capacitor, and forming both a first conductor layer on said silicon nitride film to provide the electrode of said first capacitor and a second conductor layer on said silicon oxide film to provide the electrode of said second capacitor.

The present invention will now be described in greater detail by way of example with reference to the accompanying drawings, wherein:~ Fig. 1 is a circuit diagram showing a dynamic random access memory, to which the present invention is applied; Fig. 2 is a perspective section showing the construction of one memory cell M-CEL according to an embodiment of the present invention; Fig. 3 is a perspective section showing the construction of one dummy cell D-CEL according to the embodiment of the present invention:: Fig. 4 is a perspective section showing the construction of a portion of a peripheral circuit according to the embodiment of the present invention; Fig. 5 is a top plan view showing a memory array and a dummy array according to the embodiment of the present invention; Figs. 6A and 6B are top plan views showing the pattern of a portion of a field insulating film and the pattern of a portion of a first polycrystalline silicon layer both in Fig. 5, respectively: Fig. 7 is a top plan view showing a portion of the peripheral circuit according to the present invention; and Figs. 8A to 8Z are sectional views showing the respective steps of the process of fabricating the dynamic random accress memory according to the embodiment of the present invention.

In Figs. 9A to 1 2A and Figs. 9B to 1 2B partially showing in top plan views the process of Figs. 8A to 8Z: Figs. 9A to 1 2A are top plan views showing the memory array portion and the dummy array portion; and Figs. 9B to 12B are top plan views showing the peripheral circuit portion.

For changing the capacity ratio, it is conceivable to change the thickness of the of a dielectric layer (i.e., an insulating film), which determines the capacity, or to use insulating films having different dielectric constants in addition to the change in the areas of the insulating films.

Specifically, the present invention is characterized in that, although the areas of the insulating films for determining the capacities are made substantially equal to each other, the insulating films are made of materials ensuring the ratio of their dielectric constants of 2:1. More specifically, the insulating film of the capacitor Cs of the M CEL is made of Si3N4 (i.e., silicon nitride) having a dielectric constant of 7 to 8, and the insulating film of the capacitor Cds of the D-CEL is made of SiO2 (i.e., silicon oxide) having a dielectric constant of 3.7 to 4.

The structure of one of the M-CELs which constitute a part of the dynamic random access memory shown in Figure 1, is shown in detail in Figure 2. The M-CEL includes: a P-type semiconductor substrate 1; a relatively thick insulating film 2 (which will be called "a field insulating film") having a thickness of about 9500A; a relatively thin insulating film 3 (which will be called "a gate insulating film") having a thickness of about 50A; a dielectric layer 3a having a thickness of about 400 to 500A; N+type semiconductor regions 4 and 5; first polycrystalline silicon layer 6; and N±type semiconductor region 7 (or an N-type surface inversion layer); a second polycrystalline silicon layer 8; a PSG (phosphor silicate glass) layer 9; having a thickness of about 8000 ; and an aluminium layer 10.

The MISFET QM of one of the M-CELs has its substrate, source region, drain region, gate insulating film and gate electrode made of the aforementioned P-type semiconductor substrate 1, N±type semiconductor region 5, gate insulating film 3 of a semiconductor oxide, and second polycrystalline layer 8, respectively. The second polycrystalline silicon layer 8 is used, for example, as a word line WL,~2 shown in Fig. 1.

The aluminium layer 10 connected with the N+type semiconductor region 5 is used, for example, as a data line DL~, shown in Fig. 1. On the other hand, the memory capacitor C, in the M-CEL has its one electrode, dielectric layer and other electrode made of the first polycrystalline silicon layer 6, the insulating film (or the semiconductor oxide film 3, i.e., the two-iayered insulating film which is composed of the SiOz film and the semiconductor nitride 3a, i.e., the Si 3N4 film) and the N±type semiconductor region (or an N--type surface inversion layer) 7, respectively.In the case where the lower side (i.e., the substrate surface) of that capacitor Cs is made of the N±type semiconductor region, the upper side electrode (i.e., the first polycrystalline silicon layer 6) is connected with a voltage V99 (at earth potential).

On the contrary, in the case where the N±type semiconductor region is not formed at the lower side (i.e., the substrate surface) of the capacitor Cs, the first polycrystalline silicon layer 6 is connected with the Vcc (i.e., the power source). In this case, it is necessary to impress the power voltage upon the aforementioned first polycrystalline silicon layer 6. By the electric field effect (i.e., the electric field effect through the insulating films 3 and 3a) based upon that power source voltage Vcc, there is induced the N-type surface inversion layer 7 on the surface of the Ptype semiconductor substrate 1.

The structure of one of the D-CELs which constitute a part of the dynamic random access memory shown in Figure 1, is shown in detail in Figure 3. The D-CEL includes N±type semiconductor regions 1 1 to 14; a first polycrystalline silicon layer 15; an N±type semiconductor region 16 (or an N-type surface inversion layer); second polycrystalline silicon layers 17 and 18; and an aluminium layer 19.

The MISFET Ociof the D-CEL has its substrate, drain region, source region, gate insulating film and gate electrode made of the P-type semiconductor substrate 1 , the N±type semiconductor region 11, the N±type semiconductor region 12, the gate insulating film 3 and the second polycrystalline silicon layer 17, respectively. The gate insulating film 3 is made of a semiconductor oxide film, e.g., an SiO2 film.

Moreover, that second polycrystalline silicon layer 17 extends on the P-type semiconductor substrate 1, for example, as a dummy word line DWLR 2 shown in Fig. 1. The aluminium layer 19 connected with the N±type semiconductor region extends on the P-type semiconductor substrate 1 , for example, as a dummy data line DL~1 shown in Fig. 1.

The MISFET QD2 in the D-CEL has its substrate, drain region, source region, gate insulating film and gate electrode made of the P-type semiconductor substrate 1, the N±type semiconductor region 13, the N±type semiconductor region 14, the gate insulating film 3 and the second polycrystalline silicon layer 18, respectively. Moreover, this polycrystalline silicon layer 1 8 is fed with the discharge signal fds which is shown in the D-CEL of Fig. 1, for example.

The capacitor Cdl in the D-CEL has its one electrode, dielectric layer and other electrode made of the first polycrystalline silicon layer 1 5, the gate insulating film 3 having a thickness of about 400A and the N±type semiconductor region (or the N-type surface inversion layer) 16, respectively. In the case where the lower side (i.e., the substrate surface) of that capacitor Cds is made of the N±type semiconductor region, the upper side electrode (i.e., the first polycrystalline silicon layer 15) is connected with the V99 (at earth potential).On the contrary, in the case where the N±type semiconductor region is not formed on the surface of the lower side (i.e., the substrate) of the capacitor Cdl, the power source voltage Vcc is impressed upon the first polycrystalline silicon layer 15. By the electric field effect based on that power source voltage Vcc through the gate insulating film 3, there is induced the N-type surface inversion layer 16 on the surface of the P-type semiconductor substrate 1.

In the capacitor Cs in the M-CEL, as has been described hereinbefore, the Si3N4 film 3a and the SiO2 film 3 are used as the dielectric layers and are laminated. Moreover, the SiO2 film 3 is far thinner than the Si3N4 film 3a. As a result, the capacity of the aforementioned capacitor Cs is substantially determined by the Si3N4 film 3a. On the other hand, the capacitor Cds in the D-CEL uses the SiO2 film 3 as its dielectric layer so that its capacity is substantially determined by the SiO2 film 3. Moreover, the aforementioned capacitors C9 and Cds are so designed that their areas are substantially equal to each other. As has been described hereinbefore, still moreover, the dielectric constant of the Si3N4 is about two times as high as that of the SiO2 film.As a result, the ratio of the capacity of the capacitor Cs to the capacity of the capacitor Cdl can be substantially made 2:1.

Figure 4 is a partially perspective section showing a portion of the element construction in the peripheral circuit, which is formed in the periphery of the memory array M-ARY, e.g., an active restore AR1 shown in Fig. 1. The peripheral circuit includes: N±type semiconductor regions 20 to 23; second polycrystalline silicon layers 24 to 27; and an aluminium layer 28.

The MISFET O,, in the active restore AR, shown in Figure 1 has its substrate, source region, drain region, gate insulating film and gate electrode made of the P-type semiconductor substrate 1 , the N±type semiconductor region 20, the N±type semiconductor region 21, the gate insulating film 3 and the second polycrystalline silicon layer 24, respectively.

The MISFET Qs4 in the active restore AR, has its substrate, source region, drain region, gate insulating film and gate electrode made of the Ptype semiconductor substrate 1, N±type semiconductor region 22, the N±type semiconductor region 23, the gate insulating film 3 and the second polycrystalline silicon layer 27, respectively. This second polycrystalline silicon layer 27 is fed with an active restore control signal ,g shown in Figure 1.

The capacitor Cub11 in the active restore AR, has its one electrode and dielectric layer made of the second polycrystalline silicon layer 25 and the gate insulating film 3, respectively. That second polycrystalline silicon layer 25 is continuously connected with the second polycrystalline silicon layer 24 which is used as the gate electrode of the MISFET 099. On the other hand, that second polycrystalline silicon layer 25 has its portion 25a directly connected with the N±type semiconductor region 22.This is because, if the second polycrystalline silicon layer 24 is connected through the aluminium wiring layer with the N±type semiconductor region 22, there becomes necessary the contact area between the second polycrystalline silicon layer 24 and its aluminium wiring layer thereby to make it impossible to improve the wiring density.

Therefore, the aformentioned connecting means is adopted so as to improve the wiring density.

The other electrode of the aforementioned capacitor Cub11 is made, for example, of the N+type semiconductor region or the N-type inversion layer, which is formed on the surface of the semiconductor substrate 1. That N-type inversion layer is formed by the voltage which is fed to the second polycrystalline silicon layer 25. Although not shown in Fig. 4, moreover, that inversion layer merges into the N±type semiconductor region which is formed in the semiconductor substrate 1 and which is to be fed with the active restore control signal 0,5 of Fig. 1.

The second polycrystalline silicon layer 26 provides one of the electrodes of a capacitor Cub12 shown in Fig. 11 and has its portion directly connected similarly to the capacitor Cub11 with the source region of an MISFET 099 shown in Fig. 1 and its other portion continuously connected with the gate electrode of an MISFET 097.

Next, the layout patterns of the memory array M-ARY and the dummy array D-ARY will be described in the following with reference to Fig. 5.

The memory array M-ARY shown in Fig. 5 is composed of a plurality of memory cells M-CELs shown in Fig. 2, which are arranged in the semiconductor substrate 1. On the other hand, the dummy array D-ARY shown in Fig. 5 is composed of a plurality of dummy cells D-CELs shown in Fig. 3, which are arranged in the semiconductor substrate 1.

First of all, the memory array M-ARY shown in Fig. 5 is so constructed as will be described in the following.

In order that the plural memory cells M-CELs composed of the MISFETs 0M and the memory capacitors C9 on the surface of the semiconductor substrate 1 may be separated from one another, the field insulating film 2 is formed on the basis of the pattern (which is indicated by broken lines in Fig. 5) shown in Fig. 6A. As is different from that basic pattern rule, a field insulating film 2a is arranged below a contact hole CHo for impressing the voltage V55 upon the first polycrystalline silicon layer 6.As a result, it is possible to prevent an accident that the aluminium-silicon alloy, which is produced by the mutual reaction in the vicinity of that contact hole CHO between the aluminium layer and the polycrystalline silicon layer, extends through the insulating film just below the contact hole CHO until it undesirably reaches the surface of the semiconductor substrate 1.

Likewise, a dummy word line DWL1-2 and a control signal line fdc-L2 extend in parallel with a dummy word line DWL1#1 and a control signal line tbdr:-L1- Moreover, the data lines DL1-1, DL1#1, DL,~2 and DL,~2 extend from the memory array (M-ARY), as shown in Fig. 5. The data line DL,~, is connected through a contact hole CH3 with the drain region of the MISFET QD in the D-CEL, and the data line DL,~2 is likewise connected through a contact hole CH4 with the drain region of the MISFET QD1 in another D-CEL.

On those field insulating film 2 and gate insulating film 3, there is formed on the basis of the pattern shown in Fig. 6B the first polycrystalline silicon layer 6 which is used as one electrode of the memory capacitor C, in the M-CEL.

On the first polycrystalline silicon layer 6, moreover, there extend in the longitudinal direction of Fig. 5 word lines WL,~, to WL,, which are formed in the second polycrystalline silicon layer 8 of Fig. 8. In the transverse direction of Fig. 5, moreover, there extends the power supply line Vss-L for supplying the voltage Vss through the aforementioned contact hole CHO to the polycrystalline silicon layer 6 acting as one electrode of the aforementioned memory capacitor C".

On the other hand, the data lines DL,~, and DL1#1, which are formed of the aluminium layer 10 of Fig. 2, extend substantially in parallel with the aforementioned power supply line Vss#L, as shown in Fig. 5. The data line DL,~, is connected through the contact hole CH, with the drain region of the MISFET QM in the M-CEL, and the data line DL1-1 is connected through a contact hole CH2 with the drain region of the MISFET QM of the other M-CEL.On the other hand, the data lines DL,~2 and DL,~2 extend transversely of Fig. 5 similarly to the data lines DL,~, and DL,~, and are connected at a predetermined portion through the contact hole with the drain region of the MISFET QM in the M CEL.

Next, the dummy array D-ARY shown in Fig. 5 is so constructed as will be described in the following.

The surface of the semiconductor substrate 1 has its one portion formed with the field insulating film and its other portion formed with the gate insulating film 3.

First polycrystalline silicon layers 1 5a and 1 5b extend at a spacing from each other in the direction shown in Fig. 5 on those field insulating film 2 and gate insulating film 3. The width of those first polycrystalline silicon layers 1 5a and 1 5b plays an important role to determine the capacity of the capacitor Cds of the D-CEL.

Between those first polycrystalline silicon layers 15a and 1 Sb, there is interposed the N±type semiconductor region 14 which is shown in Fig.

3. This N±type semiconductor region 14 is used as the common power source line of the plural dummy cells D-CEL.

On the first polycrystalline silicon layer 1 spa, moreover, there extends the dummy word line DWL,~, which is formed by the second polycrystalline silicon layer 17 in Fig. 3. That dummy word line DWL,~, constructs the gate electrode of the MISFET QD1 in the D-CEL. On the other hand, the control signal line Xdc-L1r which is formed by the second polycrystalline silicon layer 18 of Fig. 3 so as to impress the discharge control signal lpdc shown in Fig.1, extends at a spacing from the dummy word line DWL,~, and in parallel thereto. The other control signal line fdc-L2 constructs the gate electrode of the MISFET QD2 in the D-CEL.

As to the peripheral circuit, for example, the layout pattern of a portion of the sense amplifier SA, shown in Fig. 1 is illustrated in Fig. 7 In Fig.

7, reference letters AR indicate an active restore portion, and letters PC indicate a data line precharging circuit portion. In that active restore portion AR, there are arranged two active restores AR, which are shown in Fig. 1. Specifically, one active restore is constructed at the side of arrow A shown in Fig. 7, and the other active restore is constructed at the side of arrow B. In that active restore portion AR, moreover, active restore control signal lines sb,9~L and 0"~, shared between those respective active restores, and a power source voltage line Vc~, are arranged, as shown in Fig. 7.

In the precharging circuit portion PC, on the other hand, there are arranged two data line precharging circuits which correspond to the aforementioned two active restores. In that precharging circuit portion PC, moreover, there are arranged a potential line V Di'-L' a precharge control signal line#@c-L, and the data lines DL1-1, D#1, DL,~2 and DL,~2 extending to the memory array M-ARY of Fig. 5, as shown in Fig. 7. the MISFETs Usi to Q67 and the capacitors Cub11 and Cub12 in Fig. 1A are arranged, as shown in Fig. 7.

Next, the fabrication process of the D-RAM of the present invention will be described in detail with reference to Figs. 8A to 8Z. In these respective Figures: letter X, is a sectional view showing the steps of fabricating the memory array M-ARY and taken along line X,~X, of Fig. 5: letter X2 is a sectional view showing the steps of fabricating the dummy array D-ARY and taken along line X2-X2 of Fig. 5; letter X3 is a sectional view showing the steps of fabricating the active restore AR and taken along line X3-X3 of Fig. 7; and letterX4 is a sectional view showing the steps of fabricating the active restore AR and taken along line X4-X4 of Fig. 7.

(A) The step of forming an oxide film and an oxidization resisting film As shown in Fig. 8A, a semiconductor substrate 101 is formed on its surface with an oxide film 102 and an insulating film, which is impermeable to oxygen, i.e., an oxidization resisting film 103. A P-type single-crystalline silicon (Si) substrate having a (100) crystal, a silicon dioxide (SiO2) film and a silicon nitride (Si3N4) film are used, respectively, as the preferred concrete materials of the semiconductor substrate 101, the oxide film 102 and the oxidization resisting film 103.

The aforementioned SiO2 film 102 is formed to have a thickness of about 500 by the surface oxidization of the Si substrate 101 for the following reason. Specifically, in case the Si3N4 film 103 is formed directly on the surface of the Si substrate 101, thermal strain is imparted to the surface of the Si substrate 101 due to the difference in the coefficients of thermal expansion between the Si substrate 101 and the Si3 N4 film 103. This results in a crystal defect in the surface of the Si substrate 101. In order to prevent this, the SiO2 film 102 is formed on the surface of the Si substrate 101 before the Si3N4 film 103 is formed.On the other hand, the Si3N4 film 103 is formed, as will be described in more detail, to have a thickness of about 1 400A by the CVD (Chemical Vapour Deposition) process, for example, so that it may be used as a mask for selective oxidization of the Si substrate 101.

(B) The step of selectively removing and ion implanting the oxidization resisting film In order to selectively removing the Si3N4 film from that surface of the Si substrate 101, which is to be formed with the relatively thick insulating film, i.e., the field insulating film, a photoresist film 104 is first formed selectively as ths etching mask on the surface of the Si3N4 film 103. At this state, the Si3N4 film 103 at the exposed portion is removed, for example, by the plasma-etching process which allows a precise etching operation.

In order that a layer having a conduction type opposite to that of the Si substrate 101, i.e., the inversion layer may not be formed on that portion of the substrate, which is to be formed with the field insulating film, an impurity having the same conduction type as that of the substrate, i.e., a P-type impurity is then introduced into the Si substrate 101 through the SiO2 film 102, which is exposed while leaving the photoresist film 104, as shown in Fig. 8B. As this introduction of the P type impurity, an ion implantation is preferred. For example, boron (B) ions, i.e., the P-type impurity are implanted with an implanting energy of 75 KeV into the Si substrate 1 01. The dose of the ions at this time is 3x 1012 atoms/cm2.

(C) The step of forming a field insulating film A field insulating film 105 is selectively formed on the surface of the Si substrate 101. As shown in Fig. 8C, specifically, after the photoresist film 104 is removed, the surface of the Si substrate 101 is thermally oxidized in a selective manner by using the Si3n4 film 103 as a mask thereby to form the SiO2 film 105 (which will be called "the field SiO2 film) having a thickness of about 9500 . The boron ions, which have been implanted during the formation of that field Si02 film 105, migrate and diffuse into the Si substrate 101 so that a P-type inversion-preventing layer (although not shown) having a predetermined thickness is formed just below the field Six, film 105.

(D) The step of removing the oxidization resisting film and the oxide film In order to expose that surface of the Si substrate 101, which is not formed with the field SiO2 film 105, to the outside, the Si3N4 film 103 is removed, for example, by the use of a hot solution of phosphoric acid (H3PO4). Next, the SiO2 film 102 is removed, for example, by the use of a hydrofluoric acid (HF) thereby to selectively expose the surface of the Si substrate 101, as shown in Fig. 8D.

The memory array and the dummy array having their Si3N4 film 103 and SiO2 film 102 removed are shown in a top plan view in Fig. 9A, and the peripheral circuit is shown in a top plan view in Fig. 9B. More specifically, the sections of the substrate taken along lines 51D and X20 of Fig. 9A are shown at the portions Xt and X2 of Fig. 8D, respectively, and the sections of the substrate taken along lines X3D and X4D of Fig. 9B are shown at the portions X3 and X4 of Fig. 8D.

As shown in Fig. 9A, the area of the capacitor C9 in the M-CEL is made, although having a different shape, as small as that of the capacitor Cds in the D-CEL.

(E) The step of forming a first gate insulating film In order to obtain a surface insulating film of the dielectric layer of the capacitor Cs in the M CEL, a first gate insulating film 130 is formed on the exposed surface of the Si substrate 101, as shown in Fig. 8E. Specifically, the exposed surface of the Si substrate 101 is thermally oxidized to form a thin oxide film having a thickness of about on onthat surface.

(F) The step of forming a nitride film In order to obtain the dielectric layer of the capacitor Cs in the M-CEL, as shown in Fig. 8F, a Si3N4 film 131 is formed all over the surface to have a thickness of 400 to 500A. This Si3N4 film acting as the dielectric layer is formed to make the dielectric constant different from that of the dielectric layer (i.e., SiO2 layer) of the capacitor Cd9 in the dummy cell.

(G) The step of forming an N±type semiconductor region The following steps are followed in case an type semiconductor region is formed as the substrate side electrodes of the capacitor in the memory cell and the capacitor in the dummy cell.

A photoresist film 132 is formed all over the surface, and the photoresist at the portions to provide the capacitor Cs of the memory cell and the capacitor portion of the dummy cell are removed by the photo-etching treatment. By subsequently ion-implanting an N±type impurity, e.g., arsenic while using the remaining photoresist as a mask, as shown in Fig. 8G, an N±type semiconductor region 133 is formed on the surface of the Si substrate at both the capacitor portion of the memory cell and the capacitor portion of the dummy cell. On the contrary, in case the N±type semiconductor region is not formed as the substrate side electrodes of the capacitors of both the memory and dummy cells, the step (G) thus far described can be omitted.

(H) The step of removing the nitride film of the dummy cell The photoresist film 132, which was used in the preceding step (G), is removed, and the Si3 N4 131 at the portion (X2), which is to be formed with the dummy cell, is selectively etched and removed by using the photoresist film, which has been newly applied (although not shown) and then subjected to a photographic treatment, as a mask. By subsequently removing the underlying SiO2 film 130, as shown in Fig. 8H, both the Si substrate at the portion X2 and the field insulating film 105 in the vicinity therebf are exposed to the outside.

(I) The step of forming a second gate insulating film A second gate insulating film 109 is formed to obtain the dielectric layer of the capacitor Cds in the D-CEL on the surface of the Si substrate 101, in which the portion (X2) to form the D-CEL is exposed to the outside. As shown in Fig. 81, specifically, the oxide film (109) having a thickness of about 400A is formed by the thermal oxidization on the exposed surface of the Si substrate. By this thermal oxidization, as shown in Fig. 81, the Si3N4 surface at both the portion (X,) to be formed with the M-CEL and the portions (X3 and X4) to be formed with the peripheral circuits is simultaneously oxidized to form a thin oxide film 135 having a thickness as small as 40A.

(J) The step of covering with a first conductor layer In order to obtain one electrode of the capacitors of the M-CEL and D-CEL, a polycrystalline silicon layer as a first conductor layer 107 is formed by the CVD process, as shown in Fig. 8J, all over the surface of the Si substrate 101. The thickness of the polycrystalline silicon layer is as large as 4000A.

The Si N film 131 is covered through the thin oxide film 135 with the polycrystalline silicon layer 107 which is formed on the M-CEL. In order to reduce the resistance of the polycrystalline silicon layer 107, an N-type impurity, e.g., phosphor is introduced thereinto by the diffusion process. As a result, the polycrystalline silicon layer 107 has a resistance of about 16 ohms/El.

On this polycrystalline silicon layer, there is formed as an inter-layer insulating film a SiO2 film 136 which is prepared by the CVD process to have a thickness of 4000 to 5000A.

(K) The step of selectively removing the first conductor layer In order to form the first conductor layer, i.e., the first polycrystalline silicon layer 107, as shown in Fig. 8K, the first polycrystalline silicon layer 107 including the insulating film 136 is selectively removed to leave electrodes 108 for the capacitors of the M-CEL and D-CEL. As the selective removing process of the first polycrystalline silicon layer 107, the plasma etching process allowing a precise etching operation is preferred.

(L) The step of oxidizing the surface of the polycrystalline silicon layer The polycrystalline silicon layers 108, which are exposed while bearing the SiO2 film 136 prepared by the CVD process of the preceding step (J), (i.e., the sides of the polycrystalline silicon layers 108) are subjected to surface oxidization, as shown in Fig. 8L, thereby to form a SiO2 film 137 acting as the interlayer insulating film of the capacitor portions.

(M) The step of removing the nitride film The SjO2 films 109, 130 and 135 and the Si3NA film 131 at the portion to be formed with the MISFET QM in the M-CEL, at the portion to be formed with the MISFET QD1 in the D-CEL and at the portions to be formed with the MISFETs Q54 and Qsff of the peripheral circuit are selective etched and removed to expose the Si substrate 101 at those portions to the outside, as shown in Fig. 8M.

The M-ARY and the D-ARY, in which the SiO2 film 130 and the Si3N4 film 131 are removed from the substrate surface, are shown in top plan views in Fig. 1 OA, and the peripheral circuit is shown in a top plan view in Fig. 1 0B. Specifically, sectional views showing the substrate and taken along lines XlM and X2M of Fig. 1 OA are located at the portions X, and X2 in Fig. SM, and sectional views showing the substrate and taken along lines X3M and X4M of Fig. 1 OB are located at the portions X3 and X4 in Fig.8M.

(N) The step of forming a third gate insulating film A third gate insulating film 110 is formed, as shown in Fig. SN, on that surface of the Si substrate 101, which is exposed to obtain the gate insulating films of the MISFETs of the M CEL, D-CEL and the peripheral circuit. Specifically, the exposed surface of the Si substrate 101 is thermally oxidized to form thereon the third gate insulating film 110 having a thickness of about 530A. As a result, the third gate insulating film is made of SiO2.

(O) The step of implanting ions for controlling a low threshold voltage In order to regulate the threshold voltages of the MISFETs Qs1 toO53, Qs6 and Q57 (at the substrate region X4) shown in Fig. 1 and having low threshold voltages, as shown in Fig.80, a Ptype impurity is ion-implanted into the substrate surface through the third gate SiO2 film 110. The P-type impurity used is boron (B), for example.

The implanting energy and the dose of the ions are preferred to be 75 KeV and 2.4x 1011 atoms/cm2, respectively. Since the ion implantation at this time uses no selecting mask, boron is also introduced into the surface portion of the substrate regions (X1, X2 and X3) to be formed with the MISFETs QMT QD1 0D2' Q54 and Qs5.

(P) The step of implanting ions for controlling high threshold voltages In order to regulate the threshold voltages of the MISFETs, which have higher threshold voltages than the MISFETs Qs1 to Q53, Qs6 and Qs7 shown in Fig. 1, for example, the MISFET QM in the M-CEL, the MISFETs QD1 and 0D2 in the D CEL or the MISFETs 054 and Qs5 in the active restore, as shown in Fig. 8P and Fig. 11, an ion implanting mask, i.e., a photoresist film 111 is formed on the third gate SiO2 film 110 at the portions of the channel regions of the MISFETs 1 toO93, Qss and 097 but not on the channel regions of the MISFETs QMT QD1 QD2 Q54 and Qss- At this state, boron is implanted. The implanting energy and the dose of the ions are preferred to be 75 KeV and 1.0x 10" atoms/cm2, respectively.

As a result, the impurity concentration in the substrate at the portions to be formed with the MlSFETSOM,QDI, QD2Z ass and Qss is further increased so that these MISFETs have high threshold values. The M-ARY and the D-ARY at their ion-implanted states are shown in top plan views in Fig. 11A, and the peripheral circuit is shown in a top plan view in Fig. 11 B. Specifically, sections showing the substrate and taken along lines X,p and X2p of Fig. 1 1A are located at the portions X, and X2 in Fig. 8P, and sections 1 showing the substrate and taken along lines X3p and X4p of Fig. 11 B are located at the portions X3 and X4 in Fig. SP.

(Q) The step of forming a direct contact hole As has been described hereinbefore with reference to Fig. 4, a contact hole, which is used for directly connecting one electrode 25 of the capacitor CB11 with the N±type semiconductor region 22, i.e., the so-called "direct contact hole" CH1oo is formed, as shown in Fig. 80, by selectively etching the second gate Si02 film while using a photoresist film 112 as a mask. As shown in the same Figure, that direct contact hole CH100 is located between the portion to provide an MISFET Q4 and the portion to provide the capacitor C911.

(R) The step of covering with a second conductor layer In order to use as the gate electrodes and wiring layers of all the MISFETs, a second conductor layer 113 is formed on all the surface of the Si substrate 101. As shown in Fig. SR, specifically, a polycrystalline silicon layer is formed, for example, as the second conductor layer 113 on all over the Si substrate 113 by the CVD process. The thickness of the polycrystalline silicon layer 11 3 thus formed is as large as about 3500 . In order to reduce the resistance, an Ntype impurity such as phosphor is subsequently introduced into that polycrystalline silicon layer by the diffusion process. As a result, the resistance of the polycrystalline silicon layer 113 is reduced to about 10 ohms/cm2.During this treatment with phosphor, the impurity or phosphor is introduced through the direct contact hole CH100into the Si substrate 101.

(S) The step of selectively removing the second conductor layer The second conductor layer, i.e., the second polycrystalline silicon layer 113 is selectively removed by the photoetching process to have a predetermined electrode or wiring shape. As shown in Fig. 8S, more specifically, the silicon layer 113 after the photoetching process forms the word lines WL,~, to WL1-6, the dummy word lines DWL,~1 and DWL1-2 and the control signal lines ~dc-L1 and #dc-L2' which are shown in Fig. 5, the active restore control signal line ~rg-Lt which is shown in Fig. 7, and electrodes 11 4 of the capacitors CB11 and CB12 or the misFETs Qs1 to 053.

As shown in Fig. 8S, the M-ARY and the D ARY at that state are shown in top plan views in Fig. 1 2A, and the peripheral circuit portion is shown in a top plan view in Fig. 1 2B. Specifically, sections showing the substrate and taken along lines XIS and X25 of Fig. 1 2A are located at the portions X1 and X2 of Fig. 8S, and sections showing the substrate and taken along lines X39 and X45 of Fig. 128 are located at the portions X3 and X4 of Fig. SS.

(T) The step of oxidizing the surface In order to prevent the surface to be formed with the source and drain regions of the MISFETs from being contaminated, as shown in Fig. ST, the exposed surface of the Si substrate 101 is thermally oxidized to form a SiO2 film 11 5 having a thickness of about 100 . Simultaneously with the formation of the SiO2 film 11 5, the word lines WL,~, to WL1-6, the dummy word lines DWL,~, and DWL,,, the control signal lines sbdc-Ll Xdt::-L2' and the electrodes of the capacitors CB11 and Cub12, or the gate electrodes of the MISFETs Osi to Qs3, all of which are made of the second polycrystalline silicon layer, have their surfaces oxidized to form thereon a SiO2 film 116 having a thickness of about 300A, as shown in Fig. 8T.

(U) The step of form the source and drain regions In order to selectively form the source and drain regions of the MISFETs in the Si substrate 101, as shown in Fig. 8U, an N-type impurity, e.g., arsenic (As) is introduced through the SiO2 film 11 5 into the Si substrate 101. As this introduction of the N-type impurity, the ion implantation is preferred. For example, the arsenic ions are implanted with an implanting energy of 80 KeV into the Si substrate 101. The dose of the ions at this time is 1 xl 019 atoms/cm2.

(V) The step (1) of forming a contact hole A contact hole for connecting the first conductor layer, i.e., the first polycrystalline silicon layer 108 and a later-described third conductor layer is formed in the S [ O2 layer 116.

As shown in Fig. 8V, specifically, a contact hole CH101 is selectively formed in the SZO2 film 11 6 by using a photoresist 11 7 as a mask. Incidentally, that contact hole CH101 corresponds to the contact hole CHo shown in Fig. 5.

The reason for forming only the contact hole CH10, for connecting the first polycrystalline silicon layer 101 and the third conductor layer will be described in the following.

As has been described hereinbefore, specifically, the thickness of the SiO2 film 137 formed on the surface of the first polycrystalline silicon layer 108 is about 300A. On the other hand, the thickness of the 5102 film 115 formed on the surface of the Si substrate 101 is about 1 ooA. If those two SiO2 films are simultaneously etched, therefore, there arises a danger that the 5102 film 11 5 may be overetched before the first polycrystalline silicon layer 108 is completely exposed. In order to prevent this, the contact hole CH10, is independently formed, as has been described hereinbefore.

(W) The step (2) of forming contact holes Contact holes for connecting the source and drain regions and the third conductor layer are formed in the SWO2 film 115. By selectively etching the S~O2 film 11 5 with the use of a predetermined mask, specifically, contact holes CH,02 to CH,04 are formed, as shown in Fig. 8W.

The aforementioned mask is also opened in the portion corresponding to the contact hole CH101, but the overetch of the Six, film 137 at the contact hole Cm101 raises no practical problem.

Incidentally, the contact hole CH102 corresponds to the contact hole CH, of Fig. 5.

(X) The step of forming an inter-layer insulating film An inter-layer insulating film is formed all over the Si substrate 101. As shown in Fig.8X, specifically, the inter-layer insulating film 118, e.g., a phosphor silicate glass (PSG) film having a thickness of about 8000A is formed on all the surface of the Si substrate 101. The PSG film 118 thus formed also acts as a getter of the sodium (Na) ions which might otherwise adversely affect the characteristics of the MISFETs.

(Y) The step (3) of forming the contact holes Contact holes are formed in the PSG film 11 8 so as to provide connections between the second polycrystalline silicon layer and the third conductor layer and between the source and drain region and the third conductor layer. As shown in Fig. 8Y, specifically, the PSG film 11 8 is selectively etched to form the contact holes CH,0, to CH104. The mask, which is used upon the formations of those contact holes CH101 to CH104, is the same as that which was used for forming the contact holes CH01 to CH,04 at the preceding contact hole forming step (2).

In order to flatten the PSG film 11 8, this film 11 8 is subsequently subjected to a heat treatment at a temperature of about 10000 C. By this heat treatment at this time, the arsenic impurity, which has been ion-implanted at the preceding step (U), is made to migrate and diffuse thereby to form N±type semiconductor regions 119 to 126 having predetermined depths. These N±type semiconductor regions 119 to 126 provide the source and drain regions.

Here, the formation of the contact holes in the SiO2film 115 at the preceding contact hole forming step (2) may be accomplished simultaneously with the formation of the contact holes in the PSG film 118. However, this PSG film 11 8 is etched while the contact holes are being finished in the SZO2 film 11 5. In other words, the PSG film 118 is overetched. In order to prevent this overetch, therefore, as has been described in the above, the formations of the contact holes in the PSG film 118 is preferably conducted separately of the formation of the contact holes in the SiO2 film 11 5.

(Z) The step of forming a third conductor layer In order to form the power supply line V5XL-L and the data lines DL1-1, DL1#1, DL,, and DL,,, which are shown in Fig. 5, a third conductor layer, e.g., an aluminium layer having a thickness of 1 2000A is first formed on all the surface of the Si substrate 101. Then, the aluminium layer thus formed is selectively etched to form the power supply line Vss-L the data line DL,~, and a wiring layer 127, as shown in Fig, 82.

The dynamic random access memory of the present invention is completed by the steps thus far described.

Since the area S of the capacitor C9 in the memory cell M-CEL is made substantially equal to the area Sd of the capacitor Cds in the dummy cell D-CEL, the area fluctuating coefficients become substantially equal to each other even if there arise dispersions when the selective oxidizing mask (i.e., the Si3N4 film 103) and the capacitor electrode (i.e., the polycrystalline silicon layer 108), which are related to the fluctuating coefficients of the areas of the capacitors, are to be formed by the etching processes. As a result, the occupied area of the M-CEL can be reduced to about one half of the conventional one so that a dynamic random access memory having a high capacity can be obtained.

Moreover, since the area of the capacitor C9 is reduced, it is possible to eliminate the malfunction in the memory, which might otherwise be caused by a particles emitted from a ceramic package or the like.

Since the respective capacitors Cs and Cds are formed with the N±type semiconductor regions 7 and 1 6, as in the embodiment of the present invention (which should be referred to Figs. 2 and 3), it is possible to further obviate the disadvantage that the malfunction in the memory is caused by the a particles emitted from the ceramic package or the like.

Still moreover, since the electrodes (i.e., the polycrystalline silicon layers) 6 and 15 of the respective capacitors Cs and Cds are connected to earth, as in the embodiment of the present invention, it is possible to hold more stably data than those which are held by the method of applying the power source voltage Vcc (at 5V) to those electrodes. According to this method of applying the power source voltage Vcc, the change in the capacity is caused by the fluctuations in the power source voltage so that the data stored in the capacitors Cs and Cds become unstable.

Furthermore, so that the polycrystalline silicon layer may be prevented from directly covering the Si3N4 film of the capacitor Cs, i.e., so that the thermal strain resulting from the difference in the coefficients of thermal expansion between the polycrystalline silicon layer and the Si3N4 film may be reduced, the Si3N4 film is thermally oxidized to simultaneously form thereon the Si02 film and the SiO2 film which provides the dielectric layer of the capacitor Cds in the D-CEL. As a result, the independent step of forming the dielectric layer of the capacitor Cds is not required so that the number of the steps can be reduced.

In an alternate form, a P-channel type MISFET may be used as the MISFET constructing the dynamic random access memory. Moreover, a portion of the conductor layer, especially, the word line may be made of refractory metal such as an alloy of silicon and aluminium, molybdenum, tungsten, chromium or tantalum, or their silicides.

Claims

1. A semiconductor memory device including: a memory cell including an MIS type FET and a capacitor both formed in the surface of a semiconductor substrate at a first predetermined region; and a reference level generating cell including a MIS type FET and a capacitor both formed in the substrate of said semiconductor substrate at a second predetermined region; wherein each of the capacitors, which are formed in said first and second predetermined regions, includes a dielectric film formed over a portion of the surface of said semiconductor substrate, and a conductor layer formed over said dielectric film; and wherein the dielectric film of said capacitor formed in said first predetermined region is made of a material different from that of the dielectric film of said capacitor formed in said second predetermined region.

2. A semiconductor memory device including: a plurality of memory cells and a plurality of reference level generating cells all formed in a semiconductor substrate and each including a MIS type FET and a capacitor at such a region of said semiconductor substrate as is enclosed with a thick field oxide layer; wherein each of the capacitors of said memory cells and said reference level generating cells includes a dielectric film formed over a portion of said region and made thinner than said field oxide layer, and a conductor layer formed over said dielectric film; and wherein the dielectric film of each of the capacitors of said memory cells is made of a material different from that of the dielectric film of each of the capacitors of said reference level generating cells.

3. A semiconductor memory device according to Claim 2, wherein the area, which is occupied by the capacitors of said memory cells in said region enclosed with said field oxide layer, is substantially equal to that occupied by the capacitors of said reference level generating cells.

4. A semiconductor memory device according to Claim 2, wherein the dielectric constant of the dielectric film, which substantially determines the capacity of each of the capacitors of said memory cells, is about two times as high as that of the dielectric film which substantially determines the capacity of each of the capacitors of said reference level generating cells.

5. A semiconductor memory device according to Claim 4, wherein the dielectric film which substantially determines the capacity of each of the capacitors of said memory cells, is made of a silicon nitride film and wherein the dielectric film which substantially determines the capacity of each of the capacitors of said reference level generating cells, is made of a silicon oxide film.

6. A semiconductor memory device according to Claim 2, wherein the dielectric film of each of the capacitors of said memory cells includes upper and lower layers of silicon oxide, and a middle layer of silicon nitride, and wherein the dielectric film of each of the capacitors of said reference level generating cells is made of a silicon oxide film.

7. A semiconductor memory device according to Claim 2, wherein said semiconductor substrate is made of silicon, wherein the thick field oxide layer is made of a silicon oxide film and wherein said conductor layer is made of polycrystalline silicon.

8. A method of manufacturing a semiconductor device, including the steps of: forming a first insulating film in the surface of a semiconductor substrate in a manner to enclose both first and second predetermined regions of said semiconductor substrate; forming a silicon nitride film on said first predetermined region in order to determine the capacity of a first capacitor; forming a silicon oxide film on said second predetermined region simultaneously with the oxidization of the surface of said silicon nitride film in order to determine the capacity of a second capacitor, and forming both a first conductor layer on said silicon nitride film to provide the electrode of said first capacitor and a second conductor layer on said silicon oxide film to provide the electrode of said second capacitor.

9. A method of manufacturing a semiconductor memory device, comprising the steps of: forming a silicon nitride film, in order to determine the capacity of a capacitor of a memory cell, on a region of a semiconductor substrate as is formed with said memory cell; and forming a silicon oxide film, in order to determine the capacity of a capacitor of a reference level generating cell, on another region of said semiconductor substrate simultaneously with the oxidation of the surface of said silicon nitride film as is formed with said reference level generating cell.

10. A method of manufacturing a semiconductor memory device, including the steps of: forming a silicon nitride film all over one major surface of a semiconductor substrate through a first gate insulating film; selectively removing said silicon nitride film and said first gate insulating film over and on a region of said semiconductor substrate as is formed with a reference level generating cell; forming a silicon oxide film as a second gate insulating film on the region, which is formed with said reference level generating cell, simultaneously with the oxidization of the surface of said silicon nitride film on another region of said semiconductor substrate as is formed with a memory cell; forming a polycrystalline semiconductor layer as a first conductor layer on both the region, which is formed with said memory cell, and the region which is formed with said reference level generating cell; removing said polycrystalline semiconductor layer whilst leaving it as a capacitor portion of said memory cell and a capacitor portion of said reference level generating cell; oxidizing the surface of said polycrystalline semiconductor layer; exposing the surface of said semiconductor substrate to the outside other than the capacitor portion of said memory cell and the capacitor portion of said reference level generating cell; forming a silicon oxide film as a third gate insulating film on the exposed surface of said semiconductor substrate; forming a polycrystalline semiconductor layer as a second conductor layer on said third gate insulating film; and forming a semiconductor region by introducing an impurity having a conduction type different from that of said semiconductor substrate into said substrate whilst using said first and second conductor layers as a mask.

11. A semiconductor memory device constructed substantially as herein described with reference to and as illustrated in Figures 2 to 7, and Figures 9A to 12A and Figures 9B to 12B of the accompanying drawings.

12. A method of manufacturing a semiconductor memory device substantially as herein described with reference to Figures 8A to 8Z of the accompanying drawings.