GB2091035A - Integrated circuit device and subassembly - Google Patents

Integrated circuit device and subassembly Download PDF

Info

Publication number
GB2091035A
GB2091035A GB8118481A GB8118481A GB2091035A GB 2091035 A GB2091035 A GB 2091035A GB 8118481 A GB8118481 A GB 8118481A GB 8118481 A GB8118481 A GB 8118481A GB 2091035 A GB2091035 A GB 2091035A
Authority
GB
United Kingdom
Prior art keywords
capacitor
leg
portions
plane
mounting portions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB8118481A
Other versions
GB2091035B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Avx Components Corp
Original Assignee
AVX Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AVX Corp filed Critical AVX Corp
Publication of GB2091035A publication Critical patent/GB2091035A/en
Application granted granted Critical
Publication of GB2091035B publication Critical patent/GB2091035B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49589—Capacitor integral with or on the leadframe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

In a decoupling arrangement for an integrated circuit device incorporating a lead frame of the sort which includes an elongate metallic web the lead frame provides an integral seat or platform (23, 24) whereon is mounted a decoupling capacitor (C) which is connected in shunting relation of the power supply inputs to the integrated circuit device, the capacitor (C) providing a convenient mounting platform for the integrated circuit chip 12 and also assuring minimal lead lengths between the capacitor and the power supply inputs of the integrated circuit chip. Due to the shortness of such lead lengths and consequent reduction of the inductance reactance of the power supply circuit, efficient dampening of switching transients is achieved with the use of capacitors of much smaller values, in less area than heretofore required in external dampening applications. <IMAGE>

Description

SPECIFICATION Integrated circuit device and subassembly The invention relates to integrated circuit (IC) devices and particularly to IC devices utilised as memory circuits.
Still more particularly, the present invention relates to an IC device and lead frame subassembly therefor having improved decoupling characteristics and enabling the formation of more compact memory assemblies.
The use of IC devices, particularly as components of memory circuits, is widespread.
When one or more of the switching circuit elements of an IC are activated, current and voltage transients are generated, which transients are injected into the power supply circuit which is in turn linked to other elements of the memory system. Where the transient energy of the pulses approaches the characteristics of a functional signal, it is possible to obtain a false reading or transmission of false information, resulting in what is known in the industry as "soft error".
In order to reduce the instances of soft error, it is conventional to employ decoupling or bypassing capacitors bridging the power supply inputs of the IC, whereby transient energy (noise) is absorbed rather than being transmitted to the rest of the IC circuits through the power supply connections.
Heretofore, in circuits employing ICs of the lead frame type, the decoupling has been effected by mounting a capacitor on the printed circuit (PC) board adjacent to and externally of each IC, the leads of the capacitor being connected via the PC wiring across the power supply terminals of the IC.
The series combination of lead length and wiring increases the effective impedance of the capacitor, rendering it less effective, especially for shunting high frequency current transients such as are typically produced by dynamic IC memory circuits. Yet, these circuits require that the power supply be maintained + 10% to correctly maintain data stored within the memory. The value of the capacitors heretofore required to be employed has been successful, on the order of 0.1 to 2 mfd.
Capacitors having such relatively high electrical values, in addition to being expensive, are bulky, whereby the desired goal of circuit compactness is frustrated.
The present invention may be summarised as directed to an improved lead frame subassembly of the type which is fabricated from a punched-out or etched elongate metal band or web and is characterised in that the metal frame components of the lead frame are constructed and arranged mechanica'ly to support a capacitor which is electrically shunted across the power supply conductors of the lead frame, the capacitor serving as the support for an IC die or chip, the power supply terminals of said IC die are conventionally connected to the power supply conductors of the lead frame through short lead sections or jumpers or wire bond thread.
It has been established that the lead length in decoupling circuits heretofore known is a significant factor in adversely increasing the magnitude of the unwanted power supply pules or transients generated due to the inductive reactance created by the long leads, and that by juxtaposing the capacitor intimately adjacent the power supply terminals of the IC chip, with consequent reduced lead length in the decoupling circuit, small capacitance values are able to effect pulse dampening. By way of example and without limitation, a capacitance value of 0.05 mf inserted next to the IC chip and shunted internally across the power supply terminals thereof, is capable of effectively dampening current pulses which theretofore required between 0.1 and 2 mfd. of external capacitance depending on the frequency of the current pulse.
The invention more specifically is directed to a lead frame of the type comprising a web punched to define a latticework of spaced metal components which will ultimately act as conductors, at least one of the components of the lead frame being deflected from the plane of the metal web and defining a seat for the mounting of a capacitor which is both electrically and mechanically supported thereon. The capacitor provides a mounting platform for an IC die or chip, the power supply terminals of which are electrically connected to components of the lead frame, which are in electrical connection with and provide physical support for the terminals of the capacitor.Under such circumstances, the lead length between the decoupling capacitor and the power supply terminals of the chip is rendered extremely short, whereby the inductance reactance normally added by conventional leads and PC wiring is minimised.
Accordingly, it is an object of the present invention to provide an improved lead frame subassembly adapted, by the addition of an appropriate circuit bearing silicon die or chip, to be formed into an IC device characterised in that the capacitor is interrelated with the metallic components of the lead frame in such manner that the capacitor forms a physical support for the chip, and the leads between power supply input of the IC chip and the capacitor are maintained at a minimum length.
Still a further object of the invention is the provision of an IC device fabricated from a lead frame subassembly of the type described.
A further object of the invention is the provision of an IC device of the lead frame type, i.e. a device fabricated from skeletal components of a stamped metal web and, in addition, including an internal capacitor component which effectively decouples the power supply circuit against the transmission of switching transients, the value of the capacitance being only a small fraction of the value of the capacitance required where external decoupling is employed.
Still a further object of the invention is the provision of a lead frame subassembly of the type described and comprising a multiplicity of interconnected lead frame components adapted to be handled by automatic processing machinery, each of the noted components incorporating an internal decoupling capacitor which also functions as a mechanical support for a silicon chip or the like.
According to one aspect of the present invention there is provided an integrated circuit device comprising, in combination, a mass of polymeric insulating material, a latticework of metal formed from an integral web embedded in said mass, said latticework including a plurality of conductor members having portions disposed in coplanar alignment within said mass, said conductor members including contact portions extending outwardly of said mass, a pair of said conductor members within said mass having spaced inner terminal ends defining a support platform, said platform including a pair of spaced mounting portions displaced from the plane of said conductor portions, a capacitor having a pair of electrode terminations, each said termination being electrically and mechanically connected to one of said spaced mounting portions, said capacitor having an upper surface defining a mounting area, a silicon chip member supported by said upper'surface portion, said chip member including a plurality of circuit means and a pair of power supply contacts, circuit conductor means respectively connecting said power supply contacts with a respective one of said spaced mounting portions, within said mass, whereby said power supply contacts are electrically shunted by said capacitor, and and circuit conductor means connecting said circuit means of said chip member with others of said conductor members.
According to another aspect of the invention there is provided a lead frame subassembly for the formation of integrated circuit components comprising, in combination, a elongate metal web defining a multiplicity of lead frames, each said lead frame including an open latticework of metal defining a plurality of conductive paths including portions arrayed in a plane, a central platform structure formed on said lead frames, said platform structure including a spaced pair of mounting portions formed integrally of said web, each of said mounting portions having a depending leg member extending perpendicularly to the plane of said latticework and a second leg member extending from the free end of said first leg parallel to said plane to define spaced mounting portions, a capacitor member having a contact portion at each end, each said contact portion being secured to one of said leg mounting portions in mechanical and electrical contact therewith, each of said leg mounting portions being in electrical contact with a different one of said conductive paths.
The invention will now be described by way of example only with particular reference to the accompanying drawings wherein:~ Figure 1 is a plan view of a short section of an elongate web defining a series of IC lead frames; Figure 2 is a vertical section taken on the line 2-2 of Figure 1; Figure 3 is a fragmentary plan view of the lead frame subassembly after the capacitor has been integrated thereinto; Figure 4 is a vertical section taken on the line 4-4 of Figure 3; Figure 5 is a magnified perspective view of the lead frame with an IC silicon chip applied thereto showing connections extending to the chip; Figure 6 is a plan view of a completed IC device of the invention; and Figure 7 is a plan view of a completed IC device according to the prior art.
There is shown in Figure 1, an elongate web of metal 10 which has been etched or punched, in a manner known peruse, to provide a multiplicity of blanked out areas, the metal component M remaining between the blanked out portions B.
being employed to form conductors for attachment internally to an IC chip 12 and externally between the IC device and a PC board or the like.
The lead frame web 10 may include a plurality of drive apertures or sprocket openings 13 adapted to be engaged with automatic processing equipment for the carrying out of the various subsequent steps necessary for the conversion of the metallic lattice work to a finished IC device.
The lead frame includes a series of conductor portions 1 4a, 1 4b, 1 4c, etc. and 1 5a, 1 sub, 1 sic, etc., which, in the finished IC device depicted in Figure 6, are substantially embedded within a mass of polymeric material 36.
It will be understood, as is conventional, that the conductor portions 1 4a, 1 4b, 1 4c etc., and 1 5a, 1 sub, 1 5c, etc. have inner terminal portions 14'a, 14'b, 14'c,etc. and 15'a, 15'b, 15'c, etc. to which the terminals of the IC chip 12 will be connected in the manner hereinafter described.
The conductor portion also have intermediate terminal portion 1 4"a, 1 4"b, 1 4"c, etc. and 1 5"a, 1 5dub, 15inc, etc., which lead to the external terminal portions 1 4"'a, 1 4"'b, and 1 5"'a, 1 5"'b, etc. that protrude from the finished IC device as shown in Figure 6 for connection to the external circuit.
As thus far described, the lead frame per sue is essentially conventional.
In the invention, the conductor portions 1 4a, 1 Sa, which will ultimately define the inputs to the power supply circuit have their inner terminal ends 1 4'a, 1 S'a, initially linked by a central bridge 16.
The next step in the manufacture of the lead frame subassembly of the invention, resides in severing the central bridge 16, substantially along with a central severance region 17, Figure 1, to define two discrete metal components 18, 19. By the use of a suitable forming tool, the components 18, 19 are then bent to define vertical legs 21, 22 and horizontal legs 23, 24.
As best seen in Figures 4 and 5, horizontal legs 23, 24, define support platforms for a capacitor C, which is preferably of the multi-layer ceramic type.
The end terminations 25, 26 of the capacitor are electrically and mechanically connected, as by soldering to the vertical legs 21,22 and horizontal legs 23, 24.
The capacitor C incorporates an upper surface portion 27, which provides a bed or support for the IC chip 12. Optionally, but preferably, the chip 12 is seated on an epoxy or like adhesive layer 28 mounted atop the upper surface 27 of the capacitor C. Thereupon, the inner terminal ends 14'a, and 15'a, are connected to the respective power terminals P of chip 12 in conventional manner by leads 30.
From the foregoing description, it will be evident that the outer terminal portion 14"'a, through conductor portion 14a is now electrically connected to end termination 26 of the capacitor C. In similar manner, the outer terminal portions 15"'a, through conductor portion 15a, is electrically connected to the end termination 25 of the capacitor, whereby the capacitor will be disposed in bridging relation of the power supply terminals P of the IC chip.
Thereupon, the other terminals T of the chip 1 2 are connected in conventional manner by leads 30' to the respective inner terminal ends 14' and 1 5' of the lead frame 10, and the lattice-work is severed to remove shunting portions S between the conductors (Figure 1).
After completion of the subassembly, including the lead frame, capacitor and IC chip 12, the subassembly is then embedded in the polymeric mass 36 thereby defining a block. The polymeric block hermetically seals the components and retains the conductor portions in fixed position.
Each unit is then severed along lines 31,31, shown in Figure 1 so that the conductor portion 14a, 14b, 15a, 15b, etc. will be separated from the remaining portions of the web and only the ends 14"a,15"a, etc. of the conductor portions and the leads 14"'a and 1 spa etc. protrude from the polymeric block 16. Then the leads 14"'a and 1 5"' etc. are bent to enable insertion in the PC board mounting holes.
As will be recognised by those skilled in the art, a lead frame subassembly comprising one or a series of interconnected lead frames, each with a capacitor mounted thereon, may be supplied to manufacturers of integrated circuit devices as a useful article of manufacture. The manufacturer may process the lead frame subassemblies in a manner similar to the prior conventional procedures. However, instead of mounting the IC chip on a metal portion of the lead frame as in the prior conventional procedure, the IC chip is mounted on an epoxy layer 28 which may be applied to the surface 27 of the capacitor C just prior to implacement of the IC chip thereon, the epoxy affording a means of securing the IC chip in fixed position. Subsequent processing steps as carried out by the manufacturer are identical to those now practiced in respective conventional IC devices manufactured.That is to say, after implacement and fastening of the IC chip the various connections as by leads 30 and 30' are made between appropriate ones of the inner terminals 1 4'a, 1 4'b, 1 4'c, etc. and 1 S'a, 1 S'b, 1 S'c, etc. of the metal lead frame and the respective terminals P and T of the IC chip 12. The unit is then inbedded in a polymeric mass to form a block and the unit is then severed from the remainder portion of the web and the leads formed.
From the foregoing description, it will be appreciated that there is disclosed a lead frame subassembly adapted for the mounting of an an IC chip characterised in that a capacitor is incorporated in intimate juxtaposition to the IC chip and the power supply terminals thereof.
Since the connection between the capacitor and the power supply terminals P of the chip is limited merely to the length of the short leads 30 rather than the relatively long leads 32, 33 of the prior art device, Figure 7, the inductive components of the circuit are reduced to a minimum, whereby the capacitance necessary for dampening switching pulses generated is reduced substantially compared to externally placed decoupling capacitors.
It will further be observed that there is disclosed an improved IC device carrying an internal dampening capacitor, the external dimensions of the IC being no greater than those of a conventionally fabricated IC device. The use of an external decoupling capacitor may be entirely dispensed with, with resultant space and cost savings.
As will be understood by those skilled in the art and familiarised with the instant disclosure, numerous variations and modifications may be made to the invention which is considered to reside in the concept of employing in a conventional metallic lead frame device, a capacitor member which at once defines a structural support for the circuit bearing components of the device, i.e. the IC chip and functions as a decoupling capacitor.

Claims (13)

1. An integrated circuit device comprising, in combination, a mass of polymeric insulating material, a latticework of metal formed from an integral web embedded in said mass, said latticework including a plurality of conductor members having portions disposed in coplanar alignment within said mass, said conductor members including contact portions extending outwardly of said mass, a pair of said conductor members within said mass having spaced inner terminal ends defining a support platform, said platform including a pair of spaced mounting portions displaced from the plane of said conductor portions, a capacitor having a pair of electrode terminations, each said termination being electrically and mechanically connected to one of said spaced mounting portions, said capacitor having an upper surface defining a mounting area, a silicon chip member supported by said upper surface portion, said chip member including a plurality of circuit means and a pair of power supply contacts, circuit conductor means respectively connecting said power supply contacts with a respective one of said spaced mounting portions, within said mass, whereby said power supply contacts are electrically shunted by said capacitor, and circuit conductor means connecting said circuit means of said chip member with others of said conductor members.
2. A device as claimed in Claim 1 wherein said upper surface of said capacitor is displaced at a level below the plane of said latticework, the combination including an adhesive layer disposed atop said surface, said layer having a surface portion in coplanar alignment with said plane of said latticework, said silicon chip being mounted on said upper surface of said adhesive layer.
3. A device as claimed in Claim 1 wherein said mounting portions each including a leg member extending perpendicularly away from said plane of said conductor portions and a leg member extending from the free end of said first leg substantially parallel to said plane of said conductor portions, said second leg members being in mutually opposed relation and said capacitor being seated on said second leg members.
4. A lead frame subassembly for the formation of integrated circuit components comprising, in combination, an elongate metal web defining a multiplicity of lead frames, each said lead frame including an open latticework of metal defining a plurality of conductive paths including portions arrayed in a plane, a central platform structure formed on said lead frames, said platform structure including a spaced pair of mounting portions formed integrally of said web, each of said mounting portions having a depending leg member extending perpendicularly to the plane of said latticework and a second leg member extending from the free end of said first leg parallel to said plane to define spaced mounting portions, a capacitor member having a contact portion at each end, each said contact portion being secured to one of said leg mounting portions in mechanical and electrical contact therewith, each of said leg mounting portions being in electrical contact with a different one of said conductive paths.
5. A subassembly as claimed in Claim 4 wherein the capacitor has an upper surface and a silicon chip is secured to said upper surface, said chip having a pair of power supply terminals and means electrically connecting said power supply terminals of said chip to the leg mounting portions for said capacitor.
6. A subassembly as claimed in Claim 5 in which an adhesive layer is secured to the upper surface of said capacitor, the upper surface of said adhesive layer being in coplanar alignment with the plane of said latticework.
7. A lead frame device adapted for the reception of a silicon chip or the like having multiple circuit members thereon comprising, in combination, an integral metal web having a latticework defining a plurality of conductor members having portions arrayed in a plane, a central platform structure formed on said web, said platform structure including a spaced pair of support mounting portions formed integrally of said web, each said mounting portions having a depending leg portion displaced from said plane, a capacitor member having a contact portion at each end, said contact portion being secured to one of said leg portions in mechanical and electrical contact therewith, each said leg being in electrical contact with a different one of said conductor members, said capacitor having a generally planar surface portion providing a mounting platform for the support of such silicon chip.
8. A subassembly as claimed in Claim 7 wherein said legs are disposed substantially normal to said plane, said leg portions include opposed spaced support legs disposed in parallel alignment with said plane said capacitor being supported on said support legs.
9. A lead frame including a web having a latticework of metal defining a plurality of conductor paths including portions arrayed in a plane, a central platform structure formed on said web, said platform structure including a spaced pair of mounting portions formed integrally of said web, each of said mounting portions having a depending leg member extending perpendicularly to the plane of said latticework and the second leg member extending from the free end of said first leg parallel to said plane to define spaced mounting portions.
10. A lead frame device as claimed in Claim 9 in which a capacitor member is provided having a contact portion at each end, said contact portions being secured to one of said leg mounting portions respectively in mechanical and electrical contact therewith.
11. A lead frame device as claimed in Claim 10 in which each of said leg mounting portions is in electrical contact with a different one of said conductive paths.
12. A lead frame device as claimed in Claim 11 in which said capacitor has an upper surface, a silicon chip is secured to said upper surface, said silicon chip having a pair of power supply contacts and means electrically connecting said power supply contacts of said chip respectively to each of said leg mounting portions.
13. An integrated circuit device substantially as hereinbefore described and as shown in Figures 1 to 6 of the accompanying drawings.
GB8118481A 1981-01-12 1981-06-16 Integrated circuit device and sub-assembly Expired GB2091035B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US22412781A 1981-01-12 1981-01-12

Publications (2)

Publication Number Publication Date
GB2091035A true GB2091035A (en) 1982-07-21
GB2091035B GB2091035B (en) 1985-01-09

Family

ID=22839370

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8118481A Expired GB2091035B (en) 1981-01-12 1981-06-16 Integrated circuit device and sub-assembly

Country Status (5)

Country Link
JP (1) JPS57126157A (en)
CA (1) CA1156771A (en)
DE (1) DE3130072A1 (en)
FR (1) FR2499768B1 (en)
GB (1) GB2091035B (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0104051A2 (en) * 1982-09-22 1984-03-28 Fujitsu Limited Noise protection for a packaged semiconductor device
EP0108502A2 (en) * 1982-10-08 1984-05-16 Fujitsu Limited A plastics moulded semiconductor device and a method of producing it
FR2550009A1 (en) * 1983-07-29 1985-02-01 Inf Milit Spatiale Aeronaut ELECTRONIC COMPONENT HOUSING PROVIDED WITH A CAPACITOR
US4534105A (en) * 1983-08-10 1985-08-13 Rca Corporation Method for grounding a pellet support pad in an integrated circuit device
WO1985005735A1 (en) * 1984-06-04 1985-12-19 American Telephone & Telegraph Company Integrated circuit package
FR2584865A1 (en) * 1985-07-12 1987-01-16 Inf Milit Spatiale Aeronaut Electronic component containing a capacitor
EP0459442A1 (en) * 1990-05-29 1991-12-04 Texas Instruments Deutschland Gmbh Electronic component including a lead frame with built-in capacitor
US5281846A (en) * 1990-05-29 1994-01-25 Texas Instruments Deutschland Gmbh Electronic device having a discrete capacitor adherently mounted to a lead frame
EP0493967B1 (en) * 1991-01-02 1997-05-14 Samsung Electronics Co., Ltd. Direct microcircuit decoupling

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0828447B2 (en) * 1983-10-05 1996-03-21 富士通株式会社 Method for manufacturing semiconductor device
DE3410196A1 (en) * 1984-03-20 1985-09-26 Siemens AG, 1000 Berlin und 8000 München Conductor strip for the mounting of integrated circuits
JPS61151349U (en) * 1985-03-11 1986-09-18

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3802069A (en) * 1972-05-04 1974-04-09 Gte Sylvania Inc Fabricating packages for use in integrated circuits
US3880493A (en) * 1973-12-28 1975-04-29 Burroughs Corp Capacitor socket for a dual-in-line package
JPS558286Y2 (en) * 1974-11-20 1980-02-23
FR2456388A1 (en) * 1979-05-10 1980-12-05 Thomson Brandt ELECTRONIC CIRCUIT MICROBOX, AND HYBRID CIRCUIT HAVING SUCH A MICROBOX
JPS55179055U (en) * 1979-06-07 1980-12-23

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0104051A3 (en) * 1982-09-22 1985-09-18 Fujitsu Limited Noise protection for a packaged semiconductor device
US4598307A (en) * 1982-09-22 1986-07-01 Fujitsu Limited Integrated circuit device having package with bypass capacitor
EP0104051A2 (en) * 1982-09-22 1984-03-28 Fujitsu Limited Noise protection for a packaged semiconductor device
EP0108502A2 (en) * 1982-10-08 1984-05-16 Fujitsu Limited A plastics moulded semiconductor device and a method of producing it
EP0108502A3 (en) * 1982-10-08 1985-08-07 Fujitsu Limited A plastics moulded semiconductor device and a method of producing it
EP0133125A1 (en) * 1983-07-29 1985-02-13 Cimsa Sintra Electronic component housing with a capacitor
FR2550009A1 (en) * 1983-07-29 1985-02-01 Inf Milit Spatiale Aeronaut ELECTRONIC COMPONENT HOUSING PROVIDED WITH A CAPACITOR
US4654694A (en) * 1983-07-29 1987-03-31 Compagnie D'informatique Militaire Spatiale Et Aeronautique Electronic component box supplied with a capacitor
US4534105A (en) * 1983-08-10 1985-08-13 Rca Corporation Method for grounding a pellet support pad in an integrated circuit device
WO1985005735A1 (en) * 1984-06-04 1985-12-19 American Telephone & Telegraph Company Integrated circuit package
FR2584865A1 (en) * 1985-07-12 1987-01-16 Inf Milit Spatiale Aeronaut Electronic component containing a capacitor
EP0459442A1 (en) * 1990-05-29 1991-12-04 Texas Instruments Deutschland Gmbh Electronic component including a lead frame with built-in capacitor
US5281846A (en) * 1990-05-29 1994-01-25 Texas Instruments Deutschland Gmbh Electronic device having a discrete capacitor adherently mounted to a lead frame
EP0493967B1 (en) * 1991-01-02 1997-05-14 Samsung Electronics Co., Ltd. Direct microcircuit decoupling

Also Published As

Publication number Publication date
CA1156771A (en) 1983-11-08
FR2499768B1 (en) 1985-12-20
JPS57126157A (en) 1982-08-05
GB2091035B (en) 1985-01-09
DE3130072A1 (en) 1982-08-05
JPS6316906B2 (en) 1988-04-11
FR2499768A1 (en) 1982-08-13

Similar Documents

Publication Publication Date Title
CA1180824A (en) Integrated circuit device having internal dampening for a plurality of power supplies
US5089878A (en) Low impedance packaging
US4527185A (en) Integrated circuit device and subassembly
KR19990029974A (en) Single leadframe package having a combined induction coil and an integrated circuit semiconductor chip, and a method of manufacturing the same
GB2091035A (en) Integrated circuit device and subassembly
WO2000004584A3 (en) Semiconductor component in a chip format and method for the production thereof
EP1708346A2 (en) Active primary side circuit for a switch mode power supply
KR100287243B1 (en) Semiconductor device having loc structure and manufacturing method therefor
US5286999A (en) Folded bus bar leadframe
US4617708A (en) Component module for piggyback mounting on a circuit package having dual-in-line leads, and methods of fabricating same
US20010006457A1 (en) Printed-circuit board and method of mounting electric components thereon
JP2638758B2 (en) Stacked semiconductor package and stacked package socket
EP0384586A3 (en) High reliability plastic package for integrated circuits
US4945190A (en) Circuit board device for magnetics circuit and method of manufacturing same
US6784780B2 (en) Coupling adjusting structure for double-tuned circuit
JP2798108B2 (en) Hybrid integrated circuit device
JPH02134890A (en) Circuit element mounting board
JPH09190923A (en) Printed inductor
JPH11163250A (en) Composite component
JPH0749802Y2 (en) Semiconductor device
KR200159720Y1 (en) Semiconductor package
JPH0318110A (en) Fitting structure for noise filter
JPH0263111A (en) Manufacture of chip electronic component
WO1998024279A1 (en) An apparatus for mounting electronics and a method of manufacturing such an apparatus
JPS60206055A (en) Lead terminal wire

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee