KR200159720Y1 - Semiconductor package - Google Patents

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Publication number
KR200159720Y1
KR200159720Y1 KR2019940026407U KR19940026407U KR200159720Y1 KR 200159720 Y1 KR200159720 Y1 KR 200159720Y1 KR 2019940026407 U KR2019940026407 U KR 2019940026407U KR 19940026407 U KR19940026407 U KR 19940026407U KR 200159720 Y1 KR200159720 Y1 KR 200159720Y1
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KR
South Korea
Prior art keywords
inner lead
bus bar
height
tape
semiconductor package
Prior art date
Application number
KR2019940026407U
Other languages
Korean (ko)
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KR960015629U (en
Inventor
홍성학
Original Assignee
김영환
현대전자산업주식회사
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Priority to KR2019940026407U priority Critical patent/KR200159720Y1/en
Publication of KR960015629U publication Critical patent/KR960015629U/en
Application granted granted Critical
Publication of KR200159720Y1 publication Critical patent/KR200159720Y1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Abstract

본 고안은 리드온칩(Lead On Chip : LOC) 반도체 패키지의 버스바와 내부리드의 높이를 달리하여 신뢰성을 향상시킨 반도체 패키지에 관한 것으로, 중앙부에 본딩패드(7)가 형성되어 있는 칩(1)과, 상기 칩의 양측부에 부착되고 버스바(2) 및 내부리드(3)를 부착하기 위한 제 1 테이프(5)와, 버스바(2')의 높이가 내부리드(3')의 높이보다 낮도록 하기 위하여 상기 버스바(2')와 최외곽에 있는 내부리드(3')와의 연결부위를 절곡시켜 형성한 버스바(2') 및 내부리드(3')와, 상기 내부리드(3')의 밑면에 접착되고 또한 제 1 테0l프(5)와 접착되는 제 2 테이프(6)와, 그리고 상기 내부리드(3') 및 버스바(2')를 칩(1)에 형성되어 있는 각 본딩패드(7)와 전기적으로 연결하는 와이어(6)를 포함하여 구성한 것을 특징으로하여, 와이어 본딩을 했을때 와이어의 높이를 낮추어도 버스바와 내부리드사이에 높이차가 있으므로 버스바와 와이어의 단락 위험 및 상호 인덕턴스를 방지하여 반도체 패키지의 신뢰성을 향상시킬 수 있다.The present invention relates to a semiconductor package having improved reliability by varying the height of a bus bar and an internal lead of a lead on chip (LOC) semiconductor package, and includes a chip 1 having a bonding pad 7 formed in a central portion thereof. The first tape 5 is attached to both sides of the chip and attaches the bus bar 2 and the inner lead 3, and the height of the bus bar 2 'is greater than the height of the inner lead 3'. The bus bar 2 'and the inner lead 3' formed by bending the connection portion between the bus bar 2 'and the inner lead 3' at the outermost part to be low, and the inner lead 3 A second tape 6 bonded to the underside of the ') and bonded to the first tape 5, and the inner lead 3' and the busbar 2 'are formed on the chip 1 It characterized in that it comprises a wire (6) electrically connected to each bonding pad (7) that is present, even when the wire bonding lowers the height of the wire and the busbar Since the beak Desailly difference in height may be possible to prevent the short-circuit danger, and the mutual inductance of the bus bar and wire to improve the reliability of the semiconductor package.

Description

반도체 패키지Semiconductor package

제1a도는 종래의 리드온칩 반도체 패키지에서 와이어 본딩이 완료된 상태도,1A is a state diagram in which wire bonding is completed in a conventional lead-on-chip semiconductor package.

제1b도는 제1a도의 A-A 선 단면도,Figure 1b is a cross-sectional view taken along the line A-A of Figure 1a,

제2도는 본 고안 리드온칩 반도체 패키지의 개략 사시도,2 is a schematic perspective view of a lead-on-chip semiconductor package of the present invention,

제3도는 제2도의 B-B 선 단면도이다.3 is a cross-sectional view taken along the line B-B in FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 칩 2, 2' : 버스바1: Chip 2, 2 ': Busbar

3, 3' : 내부리드 4 : 와이어3, 3 ': Internal lead 4: Wire

5 : 제 1 테이프 6 : 제 2 테이프5: first tape 6: second tape

7 : 본딩패드7: bonding pad

본 고안은 반도체 패키지에 관한 것으로, 특히 리드온칩(Lead On Chip : LOC) 반도체 패키지의 버스바와 내부리드의 높이를 달리하여 신뢰성을 향상시킨 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a semiconductor package having improved reliability by varying the heights of bus bars and internal leads of a lead on chip (LOC) semiconductor package.

일반적으로 리드온칩 반도체 패키지는 제품의 특성을 좋게하고자 내부리드와 버스바라는 전원 리드를 사용하고 있다. 즉, 제1a도 및 제1b도에 도시한 바와 같이 종래의 리드온칩 반도체 패키지는 중앙부에 본딩패드(7)가 형성되어 있는 칩(1)의 양측부에 제 1 테이프(5)를 이용하여 내부리드(3) 및 버스바(2)를 접착한 후, 상기 내부리드(3) 및 버스바(2)를 칩(1)에 형성되어 있는 각 본딩매드(7)와 와이어(6)로 본딩하여 전기적 연결을 한다. 이때, 제1b도에 도시한 바와 같이 내부리드(3)와 본딩패드(7) 사이를 와이어(4)로 본딩할시에 상기 외이어(4)가 버스바(2)위를 지나서 본딩되기 때문에, 버스바(2)와 와이어(4)의 사이에 상호 인덕턴스(INDUCTANCE)가 발생하여 노이즈(NOISE) 또는 와이어(4)와 버스바(2)와의 단락현상 등이 발생하는 문제점이 있었다. 또한 이와 같은 문제점을 개선하고자 상기 버스바(2)의 표면에 절연코팅을 하는 방법이 제시되었으나, 이는 제조 원가가 높고 버스바를 부분코팅하는 것이므로 큰 효과를 거두지 못하고 있는 실정이다.In general, lead-on chip semiconductor packages use power leads such as internal leads and busbars to improve product characteristics. That is, as shown in FIGS. 1A and 1B, the conventional lead-on chip semiconductor package uses the first tape 5 at both sides of the chip 1 in which the bonding pads 7 are formed at the center thereof. After adhering the leads 3 and the busbars 2, the inner leads 3 and the busbars 2 are bonded with the bonding mats 7 and the wires 6 formed on the chip 1. Make electrical connections. In this case, as shown in FIG. 1B, when the wire 4 is bonded between the inner lead 3 and the bonding pad 7 by the wire 4, the outer wire 4 is bonded past the bus bar 2. In addition, mutual inductance (INDUCTANCE) is generated between the bus bar 2 and the wire 4, and there is a problem in that noise or a short circuit between the wire 4 and the bus bar 2 occurs. In addition, the method of insulating coating on the surface of the bus bar (2) has been proposed to improve such a problem, but this is a situation that does not have a great effect since the manufacturing cost is high and the partial coating of the bus bar.

본 고안은 상기의 문제점을 감안하여 이를 해결하고자 안출한 것으로, 리드온칩 반도체 패키지에 헝성되어 있는 버스바(BUS BAR)와 내부리드의 높이를 다르게 헝성함을 특징으로 하여, 와이어 본딩시 와이어와 버스바간의 거리가 멀어지도록 하므로 와이어의 단락 및 노이즈 현상물 방지할 수 있다.The present invention has been made in view of the above problems, and is characterized in that the bus bars formed on the lead-on-chip semiconductor package and the heights of the inner leads are differently formed. The distance between the bars can be increased to prevent short circuits and noise artifacts.

이하 도면을 참조하여 본 고안의 일실시예를 상세히 설명하기로 하며, 종래와 동일한 구성은 동일 부호를 부가하여 설명하기로 한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings, and the same components as in the prior art will be described with the same reference numerals.

제2도는 본 고안 리드온칩 반도체 패키지의 개략 사시도로, 중앙부에 본딩패드(7)가 형성되어 있는 칩(1)과, 상기 칩의 양측부에 부착되고 버스바(2) 및 내부리드(3)를 부착하기 위한 제1테이프(5)와, 버스바(2')의 높이가 내부리드(3')의 높이보다 낮도록 하기 위하여 상기 버스바(2')와 최외곽에 있는 내부리드(3')와의 연결부위를 절곡시켜 형성한 버스바(2') 및 내부리드(3')와, 일면이 상기 내부리드(3')의 밑면에 부착되고 다른 이면은 제 1 테이프(5)와 부착되는 제 2 테이프(6)와, 그리고 상기 내부리드(3') 및 버스바(2')를 칩(1)에 형성되어 있는 각 본딩패드(7)와 전기적으로 연결하는 와이어(6)를 포함하여 구성한다.2 is a schematic perspective view of a lead-on-chip semiconductor package of the present invention, wherein a chip 1 having a bonding pad 7 formed in a central portion thereof, and a bus bar 2 and an inner lead 3 attached to both sides of the chip. The first tape 5 for attaching the bus bar and the inner lead 3 at the outermost side with the bus bar 2 'so that the height of the bus bar 2' is lower than the height of the inner lead 3 '. Bus bar 2 'and inner lead 3' formed by bending a connection portion with '), and one surface is attached to the bottom surface of the inner lead 3' and the other surface is attached to the first tape 5 A second tape 6 and a wire 6 electrically connecting the inner lead 3 'and the busbar 2' to respective bonding pads 7 formed on the chip 1, respectively. To configure.

제3도는 제2도의 B-B선 단면도로, 여기에는 제 2 도에서 나타난 바와 같이 버스바(2')와 내부리드(3')의 연결부위를 절곡하여 형성한 버스바(2')와 내부리드(3')와의 높이차가 잘 도시되어 있으며, 이 높이차는 내부리드(3')의 밑면에 접착되는 제 2 테이프(6)의 두께와 같도록 형성하거나, 또는 상기 제 2 테이프(6)의 두께를 버스바(2')및 내부리드(3')와의 높이차와 같도록 형성하여야 한다.FIG. 3 is a cross-sectional view taken along the line BB of FIG. 2, wherein the bus bar 2 'and the inner lead formed by bending the connection portion of the bus bar 2' and the inner lead 3 'as shown in FIG. The height difference with 3 'is well shown, which is formed to be equal to the thickness of the second tape 6 adhered to the underside of the inner lead 3', or the thickness of the second tape 6 Should be equal to the height difference from the busbar 2 'and the inner lead 3'.

따라서, 이상과 같이 본 고안은 버스바와 최외곽 내부리드의 연결부위를 절곡하여 버스바와 내부리드의 높이를 달리 함으로써, 와이어 본딩을 했을때 와이어의 높이물 낮추어도 버스바와 내부리드사이에 높이차가 있으므로 버스바와 와이어의 단락 위험 및 상호 인덕턴스를 방지하여 반도체 패키지의 신뢰성을 향상시킬 수 있다.Therefore, the present invention as described above by bending the connection between the busbar and the outermost inner lead to change the height of the busbar and the inner lead, there is a difference in height between the busbar and the inner lead even when the wire height is lowered when wire bonding The reliability of semiconductor packages can be improved by preventing short circuit risk and mutual inductance of busbars and wires.

Claims (3)

중앙부에 본딩패드(7)가 형성되어 있는 칩(1)의 양측부에 제 1 테이프(5)를 이용하여 내부리드(3) 및 버스바(2)를 접작한후, 상기 내부리드(3) 및 버스바(2)를 칩(1)에 형성되어 있는 각 본딩패드(7)와 와이어(6)로 본딩하여 이루어진 반도체 패키지에 있어서, 버스바(2')의 높이가 내부리드(3')의 높이보다 낮도록 하기 위하여 상기 버스바(2')와 최외곽에 있는 내부리드(3')와의 연결부위를 절곡시켜 형성한 버스바(2') 및 내부리드(3')와, 그리고 일면이 상기 내부리드(3')익 밑면에 접착되고 다른 이면은 제 1 테이프(5)와 접착되는 제 2 테이프(6)를 포함하여 구성한 것을 특징으로 반도체 패키지.After contacting the inner lead 3 and the bus bar 2 by using the first tape 5 on both sides of the chip 1 having the bonding pad 7 formed in the center, the inner lead 3 And a semiconductor package formed by bonding the bus bars 2 to the bonding pads 7 and the wires 6 formed on the chip 1, wherein the height of the bus bars 2 'is greater than that of the inner leads 3'. A bus bar 2 'and an inner lead 3' formed by bending a connection portion between the bus bar 2 'and the inner lead 3' at the outermost portion so as to be lower than the height of And a second tape (6) bonded to the bottom of the inner lead (3 ') blade and the other back surface bonded to the first tape (5). 제1항에 있어서, 상기 제 2 테이프(6)의 두께가 버스바(2')및 내부리드(2')간의 높이차와 같도록 하는 것을 특징으로 하는 반도체 패키지.The semiconductor package according to claim 1, wherein the thickness of the second tape (6) is equal to the height difference between the busbar (2 ') and the inner lead (2'). 제2항에 있어서, 상기 제 2 테이프(6)는 1 개이상 사용한 것을 특징으로 하는 반도체 패키지.3. A semiconductor package according to claim 2, wherein at least one second tape (6) is used.
KR2019940026407U 1994-10-10 1994-10-10 Semiconductor package KR200159720Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019940026407U KR200159720Y1 (en) 1994-10-10 1994-10-10 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019940026407U KR200159720Y1 (en) 1994-10-10 1994-10-10 Semiconductor package

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KR960015629U KR960015629U (en) 1996-05-17
KR200159720Y1 true KR200159720Y1 (en) 1999-11-01

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