JPH0263111A - Manufacture of chip electronic component - Google Patents

Manufacture of chip electronic component

Info

Publication number
JPH0263111A
JPH0263111A JP1150359A JP15035989A JPH0263111A JP H0263111 A JPH0263111 A JP H0263111A JP 1150359 A JP1150359 A JP 1150359A JP 15035989 A JP15035989 A JP 15035989A JP H0263111 A JPH0263111 A JP H0263111A
Authority
JP
Japan
Prior art keywords
chip
lead terminal
parallel
circuit board
end parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1150359A
Other languages
Japanese (ja)
Other versions
JPH061799B2 (en
Inventor
Noritaka Koshiba
小柴 則隆
Kazuo Nomura
野村 和雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wako Sangyo KK
Hokuriku Electric Industry Co Ltd
Original Assignee
Wako Sangyo KK
Hokuriku Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wako Sangyo KK, Hokuriku Electric Industry Co Ltd filed Critical Wako Sangyo KK
Priority to JP1150359A priority Critical patent/JPH061799B2/en
Publication of JPH0263111A publication Critical patent/JPH0263111A/en
Publication of JPH061799B2 publication Critical patent/JPH061799B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enhance an installation strength against a thermal expansion and a vibration and to enhance a mounting density by a method wherein both end parts of lead terminal wires connected to a printed-circuit board and a chip are bent and formed so as to be nearly parallel and to have a desired height and the parts are connected by a face mounting operation. CONSTITUTION:A part where a chip is installed is cut near the center; one-end parts 3 to be connected to a printed-circuit board face in parallel are formed on connection terminals on a printed-circuit board; other-end parts 4 are formed in parallel with the one-end parts 3 at an arbitrary height (h). Then, many electronic circuit elements are mounted at the chip 5; the other-end parts 4 of lead terminal wires are connected to connection terminals at the rear surface of the chip 5.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、抵抗、トランジスタ等の電子回路素子か集
積化して実装されたチップと回路配線されたプリント基
板をリート端子線で接続するチップ電子部品の製造方法
に関する。
Detailed Description of the Invention (Field of Industrial Application) This invention relates to a chip electronic device that connects a chip mounted with integrated electronic circuit elements such as resistors and transistors and a printed circuit board with circuit wiring using a lead terminal wire. Concerning a method for manufacturing parts.

〔従来の技術〕[Conventional technology]

近年、トランジスタ、その他電子回路素子をつのセラミ
ック基板等のチップに集積化して実装する技術が進歩し
、各電子機器の小形で且つ大容量のものが広く利用され
ている。このような電子回路素子が多数実装されたチッ
プには、そのマイクロボンディング工程によって、回路
パターンが印刷されたプリント基板と電気的に接続する
ためのリード端子線が取り付けられている。このリード
端子線は、一般にリードフレームと称される帯状体に形
成されたものをチップ形状に合わせて切断し、またボン
ディングを行ってチップに取り付けられるものである。
2. Description of the Related Art In recent years, technology for integrating and mounting transistors and other electronic circuit elements on a single chip such as a ceramic substrate has progressed, and electronic devices that are small and have a large capacity are now widely used. Lead terminal wires for electrical connection to a printed circuit board on which a circuit pattern is printed are attached to a chip on which a large number of such electronic circuit elements are mounted through a microbonding process. This lead terminal wire is attached to the chip by cutting a band-like body generally called a lead frame to match the shape of the chip, and bonding the lead terminal wire.

従来、この種のリード端子線を有するチップ電子部品を
製造する場合、例えばリード端子線の一端をチップ上の
接続端子に接続するか、あるいはチップを挟持するよう
にして接続することが知られているが、これらは何れも
プリント基板に穿設された貫通孔にリード端子線の他端
部を嵌め込み、半田付等により取り付けるようになって
いるため、実際にチップに接続するリード端子線の実装
密度は低いものになってしまう。即ち、プリント基板に
リード端子線の貫通孔を穿設しなければならないが、そ
の間隔には限度があり、特に抵抗素子を多数実装したチ
ップではリード端子線の数が短いチップ長に対し多数必
要となるため不都合が生じる。そこで、チップの幅方向
に対して隣接するリード端子線を交差させることにより
リード端子線間の間隔を倍にすることが提案されている
が、この場合、チップの片側にしかリード端子線を接続
することができず、大容量の電子回路素子を実装したチ
ップには通用することができない。
Conventionally, when manufacturing chip electronic components having this type of lead terminal wire, it has been known that, for example, one end of the lead terminal wire is connected to a connection terminal on the chip, or the chip is connected by sandwiching the wire. However, in all of these, the other end of the lead terminal wire is fitted into a through hole drilled in the printed circuit board and attached by soldering, etc., so it is difficult to actually mount the lead terminal wire to be connected to the chip. The density will be low. In other words, through-holes for lead terminal wires must be drilled in the printed circuit board, but there is a limit to the spacing between them, and in particular, for chips with a large number of resistance elements mounted, a large number of lead terminal wires are required for a short chip length. This causes inconvenience. Therefore, it has been proposed to double the spacing between lead terminal lines by crossing adjacent lead terminal lines in the width direction of the chip, but in this case, the lead terminal lines are only connected to one side of the chip. Therefore, it cannot be used for chips mounted with large-capacity electronic circuit elements.

また、プリント基板にリード端子線用の貫通孔を設けず
にチップ面に接続するようにした所謂面付けを行うこと
により、リード端子線の実装密度を高めたものも利用さ
れているが、リード端子線とチップの熱膨張係数の相異
、あるいは外部の振動等に起因して接続箇所が破壊され
たり断線したりする場合がある。
In addition, the mounting density of the lead terminal wires is increased by performing so-called surface mounting, which connects the lead terminal wires to the chip surface without providing through holes for the lead terminal wires on the printed circuit board. Connection points may be damaged or disconnected due to differences in thermal expansion coefficients between the terminal wire and the chip, external vibrations, or the like.

(発明が解決しようとする3題) 従来のリード端子線を有するチップ電子部品の製造方法
にあっては、上記のように抵抗素子など多数の電子回路
が集積化されたチップに対してリード端子線の実装密度
が低く、また熱膨張あるいは振動に対するリード端子線
の強度が低いという問題点があった。
(Three Problems to be Solved by the Invention) In the conventional manufacturing method of chip electronic components having lead terminal wires, as described above, lead terminals are not required for chips in which many electronic circuits such as resistive elements are integrated. There were problems in that the packaging density of the wires was low and the strength of the lead terminal wires against thermal expansion or vibration was low.

この発明は、上記のような従来の問題点に着目してなさ
れたもので、チップに対するリード端子線の実装密度が
高く、シかも製品の製造中及び基板に取付は後も熱膨張
、振動に対する強度が高いチップ電子部品の製造方法を
提供することを目的としている。
This invention was made by focusing on the above-mentioned conventional problems, and the mounting density of the lead terminal wires on the chip is high, and it is difficult to prevent thermal expansion and vibration during the manufacturing of the product and after it is attached to the board. The purpose of this invention is to provide a method for manufacturing chip electronic components with high strength.

(課題を解決するための手段) この発明のチップ電子部品の製造方法は、多数の電子回
路素子が実装されたチップと、回路配線されたプリント
基板とを電気的に接続するリード端子線を有するチップ
電子部品の製造方法であって、前記リード端子線にあら
かじめプリント基板上の接続端子に該基板面と平行に接
続する一端部を形成し、この一端部と任意の高さを持っ
て平行で且つチップ上の接続端子に゛該チップ面と平行
して接続する他端部を、平行に配置されたピッチ基準孔
を有するリードフレームと垂直に折り曲げて体形成し、
そのリード端子線の他端部の前記垂直に折り曲げた側に
前記電子回路素子が実装されたチップを取り付けるよう
にしたものである。
(Means for Solving the Problems) The method for manufacturing a chip electronic component of the present invention has lead terminal wires that electrically connect a chip on which a large number of electronic circuit elements are mounted and a printed circuit board on which a circuit is wired. A method for manufacturing a chip electronic component, wherein one end is formed in advance on the lead terminal wire to be connected to a connecting terminal on a printed circuit board parallel to the surface of the printed circuit board, and the lead terminal wire is parallel to the one end at an arbitrary height. and forming a body with the connecting terminal on the chip by bending the other end connected parallel to the chip surface perpendicularly to a lead frame having pitch reference holes arranged in parallel;
The chip on which the electronic circuit element is mounted is attached to the vertically bent side of the other end of the lead terminal wire.

(作用) この発明のチップ電子部品の製造方法においては、リー
ド端子線の−i4部からチップ面に平行に接続する他端
部を折り曲げて一体形成して取り付けるようにしている
ので、チップに対するリード端子線の実装密度を高くす
ることができ、また上記折り曲げ部分がダンパーとして
作用する。
(Function) In the method for manufacturing a chip electronic component of the present invention, the other end of the lead terminal wire connected parallel to the chip surface is bent from the -i4 part to be integrally formed and attached. The mounting density of the terminal wires can be increased, and the bent portion acts as a damper.

(実施例) 以下、この発明の一実施例を図面について説明する。(Example) An embodiment of the present invention will be described below with reference to the drawings.

第1図は、この発明に係るリード端子線を示す平面図で
、多数のリード端子線を帯状体に形成したリードフレー
ムを示しである。また、第2図はその側面図を示す。こ
のリードフレーム1は、両側に所定のピッチで基準孔2
が設けられており、図外のフレーム搬送装置により送給
され、切断。
FIG. 1 is a plan view showing a lead terminal wire according to the present invention, and shows a lead frame in which a large number of lead terminal wires are formed into a band-like body. Moreover, FIG. 2 shows its side view. This lead frame 1 has reference holes 2 at a predetermined pitch on both sides.
It is fed and cut by a frame conveying device (not shown).

チップ取付、ボンディング等の作業が行われる。Work such as chip installation and bonding is performed.

チップを取り付ける部分は中央付近が切断され、プリン
ト基板(図示せず)上の接続端子にその基板面と平行に
接続するための一端部3が形成され、この一端部3と任
意の高さhを持って平行に他端部4が形成されている。
The part to which the chip is attached is cut near the center, and one end 3 is formed for connection to a connection terminal on a printed circuit board (not shown) parallel to the board surface. The other end portion 4 is formed in parallel with.

第3図は、上記リードフレーム1にチップ5を取り付け
た図を示す。また第4図は、その側面図である。チップ
5には多数の電子回路素子が実装されており、前記リー
ド端子線の他端部4がチップ5の下面の接続端子にそれ
ぞれ接続される。そして、以後の工程でリードフレーム
1の両側部分が切り離され、両側にリード端子線を接続
したチップ電子部品として供される。
FIG. 3 shows a diagram in which the chip 5 is attached to the lead frame 1. Further, FIG. 4 is a side view thereof. A large number of electronic circuit elements are mounted on the chip 5, and the other end portions 4 of the lead terminal wires are respectively connected to connection terminals on the bottom surface of the chip 5. Then, in a subsequent process, both sides of the lead frame 1 are separated, and a chip electronic component with lead terminal wires connected to both sides is provided.

上記のように形成されたチップ5は、回路配線されたプ
リント基板に、その両側に多数接続されたリード端子線
の一端部3がそれぞれ面付けされることにより取り付け
られる。その際、リード端子線は、その一端部3がプリ
ント基板を貫通することなく面付けによフて接続される
ので、隣接するリード端子線の間隔を短くすることが可
能で、実装密度を高くすることができる。また、一端部
3と他端部4は互いに略平行となるように2回折り曲げ
て(図では略直角に折り曲げである)形成されているの
で、#1膨張係数の相異、あるいは振動に起因する接&
Ji所の破壊、断線等を防ぐことができる。これは、折
り曲げた部分がダンパーとして作用するためで、適当な
高さhを設定することにより取付強度の高いものが得ら
れるものである。
The chip 5 formed as described above is attached to a printed circuit board on which a circuit is wired, by attaching one end portion 3 of the lead terminal wires connected in large numbers on both sides thereof. At that time, one end 3 of the lead terminal wire is connected by surface mounting without penetrating the printed circuit board, so it is possible to shorten the distance between adjacent lead terminal wires and increase the packaging density. can do. In addition, since the one end portion 3 and the other end portion 4 are formed by bending twice so that they are approximately parallel to each other (in the figure, they are bent at approximately right angles), it is possible that the difference in #1 expansion coefficient or vibration may occur. contact &
It is possible to prevent damage to the wire, disconnection, etc. This is because the bent portion acts as a damper, and by setting an appropriate height h, a high mounting strength can be obtained.

上述したリード端子線の形成に際しては、第5図に示す
ような通常のリードフレーム1から形成することが可能
である。即ち、帯状体のリードフレーム1から先ずチッ
プ5の長さ分だけ中央付近を切断する。そして、左右両
側から2回逆方向に約90度ずつ折り曲げ、一端部3と
他端部4とが略平行になるように形成し、その他端部4
の上側にチップ5をIllり付け、ボンディング工程で
電気的に接続する。その後不必要となる両側の部分を切
り離せばよい。これにより、特に抵抗素子などを高密度
に集積化したチップ5において、リード端子線の実装密
度を高めることができるので有益であり、プリント基板
の小型化を図ることが可能となり、しかも貫通孔を設け
る必要はない。
When forming the above-mentioned lead terminal wire, it is possible to form it from a normal lead frame 1 as shown in FIG. That is, first, the strip lead frame 1 is cut around the center by the length of the chip 5. Then, it is bent twice in opposite directions from the left and right sides by about 90 degrees each, so that one end 3 and the other end 4 are approximately parallel, and the other end 4 is bent twice in opposite directions.
The chip 5 is attached to the upper side of the chip 5 and electrically connected in a bonding process. After that, just cut off the unnecessary parts on both sides. This is particularly advantageous in that the mounting density of lead terminal wires can be increased in the chip 5 in which resistive elements and the like are highly integrated, making it possible to reduce the size of the printed circuit board. There is no need to provide it.

〔発明の効果) 以上説明したように、この発明によれば、プリント基板
およびチップと接続するリード端子線の両端部を、略平
行に且つ所望の高さを有するように折り曲げて形成し1
面付けによって接続するようにしたため、その折り曲げ
部分がダンパーとして作用し、熱膨張、振動に対して取
付強度が高く、またプリント基板に貫通孔を設ける必要
がないので実装密度が高くなるという効果があり、抵抗
素子がセラミック基板に多数実装されたチップに対して
は特に有益な効果を奏するものである。
[Effects of the Invention] As explained above, according to the present invention, both ends of the lead terminal wire connecting to the printed circuit board and the chip are bent to be approximately parallel to each other and have a desired height.
Since the connection is made by surface mounting, the bent portion acts as a damper, providing high mounting strength against thermal expansion and vibration.Also, since there is no need to provide through holes on the printed circuit board, the mounting density is increased. This is particularly beneficial for chips in which a large number of resistive elements are mounted on a ceramic substrate.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例を示す平面図、第2図はそ
の側面図、第3図はチップを取り付けたリードフレーム
を示す平面図、第4図はその側面図、第5図はこの発明
に係るリード端子線を形成する過程を説明するための平
面図である。 1・・・・・・リードフレーム 3・・・・・・一端部 4・・・・・・他端部 5・・・・・・チップ 第1図 北陸電気工業株式会社
FIG. 1 is a plan view showing an embodiment of the present invention, FIG. 2 is a side view thereof, FIG. 3 is a plan view showing a lead frame with a chip attached, FIG. 4 is a side view thereof, and FIG. FIG. 3 is a plan view for explaining a process of forming a lead terminal wire according to the present invention. 1... Lead frame 3... One end 4... Other end 5... Chip Figure 1 Hokuriku Electric Industry Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims]  多数の電子回路素子が実装されたチップと、回路配線
されたプリント基板とを電気的に接続するリード端子線
を有するチップ電子部品の製造方法であって、前記リー
ド端子線にあらかじめプリント基板上の接続端子に該基
板面と平行に接続する一端部を形成し、この一端部と任
意の高さを持って平行で且つチップ上の接続端子に該チ
ップ面と平行して接続する他端部を、平行に配置された
ピッチ基準孔を有するリードフレームと垂直に折り曲げ
て一体形成し、そのリード端子線の他端部の前記垂直に
折り曲げた側に前記電子回路素子が実装されたチップを
取り付けるようにしたことを特徴とするチップ電子部品
の製造方法。
A method for manufacturing a chip electronic component having lead terminal wires for electrically connecting a chip on which a large number of electronic circuit elements are mounted and a printed circuit board on which circuit wiring is provided, the method comprising: One end is formed to be connected to the connection terminal parallel to the substrate surface, and the other end is parallel to this one end at an arbitrary height and connected to the connection terminal on the chip parallel to the chip surface. , is formed integrally with a lead frame having pitch reference holes arranged in parallel by being bent vertically, and the chip on which the electronic circuit element is mounted is attached to the other end of the lead terminal wire on the vertically bent side. A method for manufacturing a chip electronic component, characterized by:
JP1150359A 1989-06-15 1989-06-15 Method for manufacturing resistor chip component Expired - Lifetime JPH061799B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1150359A JPH061799B2 (en) 1989-06-15 1989-06-15 Method for manufacturing resistor chip component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1150359A JPH061799B2 (en) 1989-06-15 1989-06-15 Method for manufacturing resistor chip component

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP6086084A Division JPS60206055A (en) 1984-03-30 1984-03-30 Lead terminal wire

Publications (2)

Publication Number Publication Date
JPH0263111A true JPH0263111A (en) 1990-03-02
JPH061799B2 JPH061799B2 (en) 1994-01-05

Family

ID=15495267

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1150359A Expired - Lifetime JPH061799B2 (en) 1989-06-15 1989-06-15 Method for manufacturing resistor chip component

Country Status (1)

Country Link
JP (1) JPH061799B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003224240A (en) * 2003-02-21 2003-08-08 Dainippon Printing Co Ltd Lead frame

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4897046A (en) * 1972-03-24 1973-12-11
JPS58138350U (en) * 1982-03-10 1983-09-17 日本電気ホームエレクトロニクス株式会社 lead frame

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4897046A (en) * 1972-03-24 1973-12-11
JPS58138350U (en) * 1982-03-10 1983-09-17 日本電気ホームエレクトロニクス株式会社 lead frame

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003224240A (en) * 2003-02-21 2003-08-08 Dainippon Printing Co Ltd Lead frame

Also Published As

Publication number Publication date
JPH061799B2 (en) 1994-01-05

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