GB2074372A

GB2074372A - Integrated circuit field effect transistors

Info

Publication number: GB2074372A
Application number: GB8107353A
Authority: GB
Original assignee: Nippon Electric Co Ltd
Current assignee: NEC Corp
Priority date: 1980-03-10
Filing date: 1981-03-09
Publication date: 1981-10-28
Also published as: US4635088A; GB2074372B; JPS6217876B2; JPS56125854A

Description

1

SPECIFICATION

Improvements in or relating to semiconductor integrated circuits GB2074372A 1 The present invention relates to integrated circuits.

Insulated gate field effect transistors (hereinafter abbreviated as IGFET's) have been widely utilized in digital integrated circuits because they are suitable for high-density circuit integration and can operate at a low power consumption. A basic operation of an IGFET as a logic element in a digital circuit is such that an input signal is applied to its gate to control ON and OFF states of IGFET and an output signal in response to the input signal is derived from its drain or source. 10 In a digital logic circuit, a combination circuit such as NOR circuits, NAND circuits, etc. and a sequential circuit such as a flip-flop, shift register, etc. are used in various combinations depending upon logic function and application. Such digital logic circuit can be deemed to be basically a comination of AND circuits, OR circuits and NOT circuits. Especially, in a complementary IGFET integrated circuit, the circuit construction is clear and definite.

As is well known, an IGFET is a voltage-responsive logic element, and its gate can be deemed to be equivalent to a capacitor. On the other hand, a signal source for supplying an input signal to the gate and wirings leading from the signal source to the gate, respectively, have finite impedances. Consequently, the response in an effective signal level at the gate of IGFET is necessarily delayed by a time constant formed by the gate capacitance of the IGFET and the 20 aforementioned impedances, which makes it difficult to realize high-speed logic operations.

Moreover, since an electric charge stored in the gate capacitance is repeatedly charged and discharged upon respective switching operations, it has been also difficult to further reduce a power consumption. In addition, not only the gate capacitance of the IGFET, but also the capacitances of the source and drain of the IGFET serve to slow down the switching operations, 25 and at the same time these capacitances are superposed on the gate capacitance of the IGFET in the next stage, resulting in lowering of the speed of the logic operations of the circuit as a whole.

It is therefore one object of the present invention to provide an integrated circuit that can operate at a high speed.

Another object of the present invention is to provide an integrated circuit that can operate at a very low power consumption.

According to the present invention there is provided a semiconductor integrated circuit comprising a semiconductor substrate having a first region of a first conductivity type, a second, a third, a fourth, a fifth and a sixth regions of a second conductivity type opposite to said first 35 conductivity type formed separately in said fist region, spid third region being positioned adjacently to one side of said second region, said fourth region being adjacent to said third region, said fifth region being positioned adjacently to another side of said second region, said sixth region being adjacent to said fifth region, a first insulator film on a portion of said first region between said second and third regions, a second insulator film on a portion of said first 40 region between said third and fourth regions, a third insulator film on a portion of said first region between said second and fifth regions, a fourth insulator film on a portion of said first region between said fifth and sixth regions, a first conductor film on said first insulator film, a second conductor film on said second insulator film, a third conductor film disposed on said third insulator film and electrically connected to said first conductor film, a fourth conductor film 45 disposed on said fourth insulatator film and electrically connected to said second conductor film, means for supplying said fourth regions and said sixth region with a first predetermined voltage, an output terminal, and means for electrically connecting said second region to said output terminal.

According to the invention there is also provided a semi-conductor device comprising a 50 semiconductor substrate provided with a first region of a first conductivity type, a first rectangular region of a second and opposite conductivity type formed in said first region, a second rectangular region of said second conductivity type in said first region spaced apart from said first rectangular region, said second rectangular region being opposite to a first side of said first rectangular region, a third rectangular region of said second conductivity type in said first 55 region spaced apart from said first rectangular region, said third rectangular region being opposite to second side of said first rectangular region, a first gate insulator film disposed on said first region between said first and second rectangular regions, a second gate insulator film disposed on said first region between said first and third rectangular regions, a first gate 1 electrode on said first gate insulator film, a second gate electrode on said gate insulator film, 60 and conductor means for supplying said first and second gate electrodes with the same signal.

According to the invention there is also provided a semiconductor circuit comprising a first node, a second node, a first series circuit of a plurality of insulated gate field effect transistors connected in series between said first and second nodes, a second series circuit of a plurality of insulated gate field effect transistors connected in series between said first and second nodes, 65

GB2074372A 2 the number of the transistors in said first series circuit being equal to that in said second series circuit, means for supplying said second node with a predetermined voltage, means for receiving a plurality of signals, first means for applying said plurality of signals to said first series circuit, and second means for applying said plurality of signals to said second series circuit, wherein said first and second series circuits co-operate to determine a logic state of said first node in 5 response to said signals.

According to the invention there is also provided a semiconductor device comprising a semiconductor substrate having a first conductivity type region, a second conductivity type region formed in said first conductivity type region, a first insulated gate field effect transistor having a drain made of said second conductivity type region, a second insulated gate field effect 10 transistor having a drain made of said second conductivity type region, means for supplying said control conductivity type region with an electric charge, control means for controlling said first and second transistors in the same manner and means for deriving an output signal from said second conductivity type region.

A peferred embodiment of the present invention is an integrated circuit including a series 15 circuit of a given number of IGFET's connected in series in their drain- source diection, each IGFET in the series circuit being divided into a pair of identical IGFET's having a conductance of a half of the original IGFET, and the series circuit being divided into two sub-series circuits: one sub-series circuit containing one of each pair of divided IGFET's, the other sub-series circuit containing the other of each pair of divided IGFET's, the two sub-series circuits being connected 20 in parallel. One of the junctions of the parallel-connected sub-series circuits is made a common drain or source region of one pair of the divided IGFET's, so that the parasitic capacitance of the source or drain regions of that pair of the IGFET's is reduced.

A further embodiment is an integrated circuit comprising a plurality of transistor groups each consisting of a plurality of IGFET's connected in series, in which the same signal lines are 25 distributed to the respective transistor groups to make the respective transistor groups achieve substantially the same logic operations, and one ends of the respective transistor groups are formed in common.

A further embodiment is an integrated circuit comprising a plurality of transistor groups each consisting of a plurality of IGFET's connected in series, in which the gate electrodes of such 30 transistor groups are connected to the same signal lines according to the sequence of connection of the transistors in the respective transistor groups.

In a further embodiment of the present invention, there is provided an integrated circuit comprising a semiconductor substrate provided with a region of one conductivity type, a first region of the opposite conductivity type having a rectangular shape and provided in said one 35 conductivity type region, a plurality of second regions of the opposite conductivity type provided substantially in parallel to one edge of said first region as isolated sequentially at discrete distances from said one edge and isolated from each other, a plurality of third regions of the opposite conductivity type provided substantially in parallel to another edge of said first region as isolated sequentially at discrete distances from said one edge and spaced from each other, a 40 pluraliy of first conductive patterns provided via an insulating film on the respective regions between said one edge of said first region and the nearest one of said plurality of second regions and between adjacent ones of said second regions, that is, on the channel regions, a plurality of second conductive patterns provided via an insulating film on the respective regions between said another edge of said first region and the nearest one of said plurality of third 45 regions and between adjacent ones of said third regions, that is, on the channel regions, a plurality of signal wirings each connecting one of said first conductive patterns to the corresponding one of said second conductive patterns, and a common wiring for connecting in common the second region located at the farthest end from said first region and the third region located at the farthest end from said first regiion, whereby an output signal can be derived from said first region.

In the integrated circuit according to the present invention, a parasitic capacitance especially of'a drain region serving as an output node where charging or discharging is effected upon each switching, can be remarkably reduced without degrading a driving capability of a transistor.

Accordingly, a logic integrated circuit that can achieve a high speed operation as well as a very 55 low power consumption operation, is realized.

The invention will now be described, by way of example, with reference to the accompanying drawings, in which:

Figure I is a schematic circuit diagram showing a standard known NAND circuit consisting of N-channel MOS transistors; Figure 2 is a plan view of an integrated circuit in which the NAND circuit shown in Fig. 1 is realized according to the prior art;

Figure 3 is an equivalent circuit diagram of a NAND circuit constructed according to the present invention; Figure 4 is a plan view of an integrated circuit according to the present invention as applied, 65 1 5 i c 3 GB 2 074 372A 3 by way of example, to a 2-input NAND circuit; Figure 5 is a schematic plan view showing distribution of capacitances in the transistor layout shown in Fig. 2; Figure 6 is a schematic plan view similar to Fig. 5 showing distribution of capacitances 5 integrated circuit according to the present invention shown in Fig. 4; Figure 7 is a diagram representing proportions in percent of a pattern area and a peripheral length according to the present invention with reference to those in the case of employing the art and work method in the prior art as a function of a channel width W, and

Figure 8 is a layout diagram showing another preferred embodiment of the present invention.

Referring now to Fig. 1 of the drawings, there is shown a standard 2input NAND circuit in 10 the prior art, which is constructed on N-channel transistors. This circuit is composed of a load transistor TR1 and drive transistors TR2 and TR3. Normally the channel widths of the drive transistors TR2 and TR3 are identical to each other.

If the section of the drive transistors in this circuit is patterned according to the prior art -15 method, the layout of the pattern will become as shown in Fig. 2. More particularly, a mere series connection of transistors TR2 and TR3 is formed by providing gate electrodes 2 and 3 between N-type regions 1 and 5 and between N-type regions 5 and 4, respectively. The region - - 4 which is not shared by the respective transistors is used as a ground terminal, while the region 1 is used as an output terminal (OUT). This method of patterning called "art work method" is simple and clear, and hence it is generally employed at present. However, in the case where load to be driven is heavy, for the purpose of enhancing driving capabilities of the drive transistors TR 2 and TR 3, not to speak of the load transistor TR 1, the widths W of these transistors must be enlarged. However, in accordance with the increase of the widths W, the areas of the respective diffusion regions are increased, and thus the capacitances at the respective nodes would be increased. Moreover, the resistances of the polycrystalline silicon layers forming the gate electrodes 2 and 3 of the drive transistors TR2 and TR3 would be also increased up to an unnegligible extent.

Accordingly, even if driving capabilities should be enhanced by enlarging the channel widths W, from the view point of speeding up the circuit an improvement proportional to the increase of the widths would not be achieved according to the prior art.

Fig. 3 shows a 2-input NAND circuit, which can achieve a similar function to the circuit shown in Fig. 1 and which embodies the basic principle of the present invention. In order that the circuit shown in Fig. 3 becomes equivalent to the circuit shown in Fig. 1, it is necessary that when the current amplification factors of the drive transistors TR2 and TR3 are represented by 82 and 93, respectively, and the current amplification factors of the drive transistors TR21, TR22, TR31 and TR32 are represented by 18211 18221 831 and 1832, respectively, these amplification factors fulfil the conditions of:

P2 P21 + P221 J83 J831 + 1832' By fulfilling these conditions, the necessity of connecting the drain electrode of the drive transistor TR31 (or the source electrode of the drive transistor TR21) at point A in Fig. 3 to the drain electrode of the drive transistor TR32 (or the source electrode of the drive transistor TR22) at point B is eliminated, and yet the circuit shown in Fig. 3 becomes equivalent to that shown in 45 Fig. 1.

With reference to Fig. 4, one detailed embodiment of the present invention will be explained where only the section of drive transistors in the circuit shown in Fig. 3 is realized according to the present invention.

In Fig. 4, on one principal surface of a P-type semiconductor substrate are disposed N-type 50 regions 8 and 21 serving as a source and a drain, respectively, of a transistor TR31, an N-type region 22 serving as a drain of a transistor TR21 and also as a drain of a transistor TR22, an N type region 23 serving as a source of the transistor TR22 and also as a drain of a transistor TR32, and an N-type region 13 serving as a source of the transistor TR32 as directed in the same direction. A polycrystalline silicon layer 6 forms a gate electrode wiring for the transistors TR21 and TR22, and a polycrystalline silicon layer 7 forms a gate electrode wiring for the transistors TR31 and TR32. From a contact 15 provided in the N-type region 22 is led out an output terminal OUT shown in Fig. 3. A source of a load transistor TR1 may be connected to the contact 15 by a known method (not shown), contacts 12 and 14 provided in the N-type regions 8 and 13, respectively, are both connected to a grounded terminal of a power supply. In 60 the layout shown in Fig. 3, the widths of the respective N-type regions are selected about 1 /2 times as small those in the layout shown in Fig. 2. As described above, according to the present invention, the capacitance of the region 22 corresponding to an output terminal which may possibly affect the circuit performance can be reduced as compared to an integrated circuit patterned according to the prior art method, owing to the fact that two sets of series patterns are 65

4 GB2074372A 4 formed Iy dividing the widths W of the transistors into two equal parts and patterning is effected so that the two series patterns may share a drain region at one ends.

Now the effects and advantages of the present invention will be explained in greater detail with reference to Figs. 5 and 6. At first, consideration will be made on a capacitance of the drive transistors in the prior art shown in Fig. 2 as viewed from an output node contact 11 corresponding to an output terminal OUT in an output transistor section. In this case, a capacitance of a region 1 corresponding to the drain of the drive transistor TR2 and a capacitance of a region 5 corresponding to the source of the drive transistor TR2 and the drain of the drive transistor TR3 would affect the output. On the other hand, since a region 4 corresponding to the source of the drive transistor TR3 is fixedly held at the ground potential, the effect of the capacitance of this region 4 can be neglected.

In the respective cases shown in Figs. 5 and 6, it is assumed hereunder that as a rule, in the drain region forming an output node, an interval of 4 microns is provided between the periphery of the output contact and the periphery of the gate electrode and an interval of 2 microns or more is provided between the output contact and the edge of the drain region. Also it is assumed that the width of the contact is 3 microns and the minimum impurity region width is 4 microns. In Fig. 5, the length of the drain region 1 is represented by I,, , its width is represented by W. The length of the region 5 is represented by 11, and the width of the same is also represented by W. In this figure, reference symbol 114 designates the distance between the gate electrode 2 and the contact 11, which is 4 microns as described above. Reference symbol 113 20 designates the distance between the contact 11 and the edge of the drain region 1, which is 2 microns. Reference symbol 11, designates the width of the contact 11, which is 3 microns.

At first, denoting a bottom capacitance per unit area by reference symbol CA, the capacitance C, formed between the bottom surfaces of the regions 1 and 5 and the substrate is represented by the following equation:

C11 CA (W X 111 + W X 112) CA W (111 + 112)' (1) Substituting 1,1 = 9 (microns) and 112 = 4 (microns) into Equation (1) above, we obtain: 30 C11 = CA. W (9 + 4) = 13 'CA'W (2) On the other hand, the capacitance C12 formed by the side surfaces (wall surfaces) of the regions 35 1 and 5 is represented by the following equation when the capacitance per unit area of the side surface is represented by reference symbol C,:

C12 C,. (2. 11, + W + 2 ' 112) (3) Substituting the above-referred numerical values of the lengths Ill and 11, into Equation (3) above, we obtain:

C12 = C, (2 X 9 + W + 2 X 4) = C,. (2 8 + W) (4) 45 Therefore, the total capacitance C, is represented by the following equation:

z j' t z C13 C11 + C12 50 - f = W (1 3C, + CJ + 28 CB (5):F Now consideration will be made on the preferred embodiment of the present invention shown in Fig. 4, with reference to Fig. 6. In this preferred embodiment, the widths of all the impurity regions serving as a drain or a source are chosen about 1 /2 times as small as the width in the case of the prior art layout shown in Fig. 5. In this case, the capacitance as viewed from the output control 15 is equal to the sum of the capacitance of the region 21, the capacitance of the region 22 and the capacitance of the region 23. Similarly to the case shown in Fig. 5, the capacitance C21 formed by the bottom surfaces of the respective regions is represented by the following equation:

C21 = CA - (-I- W - 1,1 + 2 -L W ' 122) (6) 2 2 As mentioned previously in connection to Figs. 5 and 6, the length 12. is 3 microns and the lengths 12, and 12, are respectively 4 microns. Hence the length 121 is equal to 11 microns, and also the lengths 123 and 122 are respectively 4 microns. Therefore, substituting these numerical 65 GB2074372A 5 values into Equation (6), we obtain:

C21 CA ' ( 7217 W, 11 + W. 4) + 9'5 CA' W (7) Considering now the side surface capacitance C22 in the same manner as described above, it is represented by the following equation:

C22 C, - (2. 121 + 4. 122) (8) Substituting the numerical values of the lengths 1,1 and 122 into Equation (8) above, we obtain:

C22 = 38 C,, Accordingly, the total effective capacitance C23 is given by the following equation:

C23 = C21 + C22 = 95 CA W + 38 C, Now the capacitance reduction ratio R of the layout shown in Fig. 6 with respect to the prior art layout shown in Fig. 5 will be considered. A reduction ratio R, of the bottom surface 20 capacitance is given by the following equation:

9.5 C. W 13CA -= 0.73 (11) W Also, a reduction ratio R12 of the side surface capacitance is given by the following equation:

C22 38 C, 30 R12 = - = 12 38 28C,, + Q,. W 28 + W Thus it will be understood that the reduction ratio R12 is substantially inversely proportional to the value of the width W.

Here, if the following numerical values are employed as representative values:

W = 150g CA = 2.3 X 10-4 pF /[42, and C, = 4.0 X 10-4 pF/,u.

Then according to Equation (5), the total effective capacitance C, becomes 0.5197 pF. On the other hand, according to Equation (10), the total effective capacitance C2, becomes 0.3429 pF.

Therefore, according to the present invention, really reduction in the total effective capacitance of as large as 34% can be achieved.

Fig. 7 shows the effects of the present invention on the basis of the above-mentioned results 45 of consideration, in which capacitance proportions of the pattern area and peripheral length of the layout according to the present invention with respect to those of the layout formed by the art work method in the prior art which are used as a reference, are represented in per cents. In this figure, a channel width W of the drive transistors is taken along the X-axis, and the capacitance proportions of the pattern area and peripheral length are taken in per cents along 50 the Y-axis. A curve 111 represents a reduction ratio R, of the pattern area, while a curve 112 represents a reduction ratio R12 of the peripheral length as a function of the channel width W. It will be readily seen from Fig. 7 that the reduction ratio R,, is held substantially constant at 73% for every value of the channel width W, whereas the reduction ratio R12 is reduced as the channel width W is increased. Although comparison is made with respect to geometrical dimensions in Fig. 7, the effects of reducing the parasitic capacitances will be readily appreciated if the capacitance per unit area CA or the capacitance per unit length C, is taken into consideration.

Another preferred embodiment of the present invention is illustrated in Fig. 8, in which with respect to impurity regions 82 and 83 formed between an output node 80 and respective regions 87 and 89 to be held at the ground potential, common gates 85 and 86 are formed respectively in a pattern of rotational symmetry, and similar effects to those of the embodiment shown in Fig. 4 can be expected from this modified embodiment.

As described above, in general, capacitances of the impurity regions are represented by a sum of a term proportional to a pattern area and a term proportional to a peripheral length of a 6 GB2074372A 6 pattern, and the effects of the present invention making use of the above principle can be realized by placing a pattern of an output terminal between the gate polycrystalline silicon layers of the drive transistors TR21 and TR22, because in such a layout both the pattern area and peripheral length of the output region can be reduced. Moreover, since the proposed pattern layout is symmetric with respect to its longitudinal and transverse directions, even if any deviation should arise in pattern registration, the deviation would little affect the performance of the transistors. In addition, owing to the fact that the drive transistors are respectively divided into two parts, the resistance of the gate polysilicon layer is also reduced, and this contributes to reduction of a delay time. The above-mentioned effects of the present invention become more remarkable as the channel widths of the drive transistors are increased.

As described in detail above, according to the present invention, the circuit performance can be improved by merely making device on the art work without providing any special pattern, and since the pattern layout is symmetric with respect to its longitudinal and transverse directions, even if any deviation should arise in pattern registration, the driving capability as well as node capacitances of the transistor would be little varied. The above- described embodiments 15 of the present invention are no more than one example employing N-channel transistors, and the invention is not limited to a circuit employing N-channel transistors but the invention can be equally applied to the art work of a circuit employing P-channel transistors or complementary transistors. Especially, if the invention is applied to the art work of a complementary IGFET integrated circuit, the frequency of use of the present invention is enhanced and thus it is favorable. In addition, as a matter of course, the present invention is equally applicable to a series construction consisting of three or more transistors.

Claims

1. A semiconductor integrated circuit comprising a semiconductor substrate having a first 25 region of a first conductivity type, a second, a third, a fourth, a fifth and a sixth regions of a second conductivity type opposite to said first conductivity type formed separately in said first region, said third region being positioned adjacently to one side of said second region, said fourth region being adjacent to said third region, said fifth region being positioned adjacently to another side of said second region, said sixth region being adjacent to said fifth region, a first 30 insulator film on a portion of said first region between said second and third regions, a second insulator film on a portion of said first region between said third and fourth regions, a third insulator film on a portion of said first region between said second and fifth regions, a fourth insulator film on a portion of said first region between said fifth and sixth regions, a first conductor film on said first unsulator film, a second conductor film on said second insulator 35 film, a third conductor film disposed on said third insulator film and electrically connected to said first conductor film, a fourth conductor film disposed on said fourth insulator film and electrically connected to said second conductor film, means for supplying said fourth region and said sixth region with a first predetermined voltage, an output terminal, and means for electrically connecting said second region to said output terminal.

2. The integrated circuit according to claim 1, in which said second region has a rectangular shape with predetermined width.

3. The integrated circuit according to claim 2, in which said one and another sides of said second region is opposite to each other.

4. The integrated circuit according to claim 3, in which said third and fifth regions have a 45 rectangular shape with said predetermined width.

5. The integrated circuit according to claim 1, further comprising means for supplying said second region with a second predetermined voltage.

6. A semiconductor device comprising a semiconductor substrate praovided with a first region of a first conductivity type, a first rectangular region of a second and opposite conductivity type formed in said first region, a second rectangular region of said second conductivity type in said first region spaced apart from said first rectangular region, said second rectangular region being opposite to a first side of said first rectangular region, a third rectangular region of said second conductivity type in said first region spaced apart from said first rectangular region, said third rectangular region being opposite to second side of said first 55 rectangular region, a first gate insulator film disposed on said first region between said first and second rectangular regions, a second gate insulator film disposed on said first region between said first and third rectangular regions, a first gate electrode on said first gate insulator film, a second gate electrode on said second gate insulator film, and conductor means for supplying said first and second gate electrodes with the same signal.

7. The device according to claim 6, further comprising means for supplying said first rectangular region with an electric charge.

8. The device according to claim 6, in which said first and second gate electrodes are made of polycrystalline silicon.

9. The device according to claim 6, further comprising a first transfer gate coupled between 65 J 7 GB2074372A.7 said second rectangular region and a predetermined voltage source, a second transfer gate coupled between said third rectangular region and said predetermined voltage source and control means for controlling said first and second transfer gates at the same time.

10. A semiconductor circuit comprising a first node, a second node, a first series circuit of a plurality of insulated gate field effect transistors connected in series between said first and 5 second nodes, a second series circuit of a plurality of insulated gate field effect transistors connected in series between said first and second nodes, the number of the transistors in said first circuit being equal to that in said second series circuit, means for supplying said second node with a predetermined voltage, means for receiving a plurality of signals, first means for applying said plurality of signals to said first series circuit, and second means for applying said 10 plurality of signals to said second series circuit, wherein said first and second series circuits co operate to determine a logic state of said first node in response to said signals.

11. The circuit according to claim 10, further comprising load means for supplying said first node with an electric charge.

12. The circuit according to claim 10, in which all the transistors in said first and second 15 series circuits have the substantially same channel width.

13. A semiconductor device comprising a semiconductor substrate having a first conductivity type region, a second conductivity type region formed in said first conductivity type region, a first insulated gate field effect transistor having a drain made of said second conductivity type region, a second insulated gate field effect transistor having a drain made of said second 20 conductivity type region, means for supplying said second conductivity type region with an electric charge, control means for controlling said first and second transistors in the same manner for deriving an output signal from said second conductivity type region.

14. A semiconductor integrated circuit constructed, arranged and adapted to operate substantially as hereinbefore described with reference to, and as illustrated in, the accompanying 25 drawings.

Printed for Her Majesty's Stationery Office by Burgess Et Son (Abingdon) Ltd.-1 98 1. Published at The Patent Office, 25 Southampton Buildings, London, WC2A 1 AY, from which copies may be obtained.