GB2213667A - BIMOS logic circuit - Google Patents

Abstract

A semiconductor logic circuit uses a plurality of clocked interconnected dynamic MOS logic stages in which precharging currents are fed to the stages through clocked bipolar transistors 4, 8. The bipolar transistors driven by the same phase of the clock may have common emitters and common bases, and have a lateral structure. In a dynamic shift register data are stored on the gate capacitances C1, C2 of an input MOSFET of each stage. In a first clock phase 01 bipolar transistor 4 precharges C, in the next clock phase 02 the charge stored in C1 may cause the precharge on C2 to drain away. In this way data is shifted from stage to stage. The next stage operates in a similar way during clock phases 03,04. The use of a bipolar transistor to precharge the gate capacitances increases the speed of the circuit. <IMAGE>

Description

SEMICONDUCTOR LOGIC CIRCUIT This invention relates to semiconductor logic circuits, and particularly to such circuits fabricated in integrated circuit form.

It has been proposed to produce semiconductor logic circuits in integrated circuit form using so-called CMOS and 12L technologies and these have been found to be economical both in terms of power consumption and in terms of the area of semiconductor material needed to accommodate the circuit.

CMOS logic circuits however suffer from the disadvantages that they cannot themselves produce high output currents and must operate loads such as electric motors, solenoids and relays through buffer amplifiers. Moreover, such logic circuits can operate satisfactorily only with operating voltages in a restricted range. Whilst 12L logic circuits can be used to control high load currents directly, they can handle only a fairly low voltage.

Bipolar circuits have been produced by standard planar technology for many years and have proved capable of operating with supply voltages in a wide range, say, 1.5 to 40 volts. They can also generate output currents up to 500 mA, for example. One shortcoming of such technology is that high density logic circuits cannot be produced using the same basic processes, and therefore if a combination of bipolar circuit and logic circuits is required an extended sequence of processes has to be performed.

It is an object of the present invention to provide a logic circuit suitable for production as an integrated circuit which is economical both in power consumption and in the area of semiconductor chip required, is capable of operating with a wide range of supply voltages and can provide a substantial output current.

The invention provides a semiconductor logic circuit formed as an integrated circuit and having a plurality of sequentially connected stages, operated in use by multi-phase clock pulses, each stage including a data storage circuit having one or more MOSFETs, each selectively storing a charge on its gate capacitance affecting the conductivity of its source-drain path or of the combination of interconnected source-drain paths to indicate the data bit stored by the circuit, and a charging circuit including transistor means connected in series with the source-drain path of the MOSFET, or the combination of source-drain paths of the MOSFETs, of the data storage circuit of the particular stage from a supply conductor, and responsive to one phase of the clock pulses to apply current selectively to the gate of a MOSFET in the circuit of the or each immediately succeeding stage depending on the conductivity of the data storage circuit of the particular stage, wherein the transistor means in the charging circuit of each stage includes a bipolar transistor of which the collector region is contained within the base region which itself is contained within the emitter region and having its emitter connected to the supply conductor and receiving the particular phase of the clock pulses on its base thereby to cause current to flow periodically from its collector to the data storage circuit of the particular stage.

The bipolar transistors receiving the same phase of the clock pulses may have a common emitter region and a common base region with the individual collectors connected to data storage circuits to form alternate stages of the logic circuit.

The invention also provides a semiconductor logic circuit formed as an integrated circuit having a substrate of a first conductivity type, an epitaxial layer on the substrate and of a second conductivity type opposite to the first, one or more isolating barriers of the first conductivity type penetrating the epitaxial layer from its surface to the substrate to divide the epitaxial layer into a plurality of electrically isolated regions, first and second pluralities of bipolar transistors formed in first and second electrically isolated regions of the epitaxial layer, each bipolar transistor having a base region of the first conductivity type in the epitaxial layer and a collector region of the second conductivity type in the base region, the bipolar transistors having regions of the epitaxial layer as emitter, a dynamic MOS logic circuit formed in one or more other electrically isolated regions of the epitaxial layer and having a plurality of interconnected stages each including at least one MOS transistor arranged to store a charge on its gate, and the controlled current paths of the successive stages being connected to the collectors of the bipolar transistors of the first and second pluralities alternately, whereby clock signals applied alternately to the bases of the bipolar transistors of the first and second pluralities enabling them to pass current to their collectors cause the charges stored on the gates of the MOS transistors to be stepped along the interconnected stages as determined by their interconnection.

Each plurality of bipolar transistors may have a region of the epitaxial layer as a common emitter, and within that region they may have a common base region.

The invention further provides a semiconductor logic circuit formed as an integrated circuit including a multistage dynamic MOS logic circuit using a 4-phase clock in which the precharging of the data storage circuits of the logic circuit is effected through two sets of bipolar transistors respectively rendered conducting by two phases of the clock, and each set of bipolar transistors has a common emitter region connected to a power supply conductor, a common base region formed within the common emitter region and connected to receive one phase of the clock and individual collector regions within the common base region connected to precharge the data storage circuits of alternate stages of the logic circuit, each stage of the dynamic MOS logic circuit including an additional MOS transistor controlled by a phase of the clock to isolate the data storage circuit of the stage from the next stage during at least the initial part of the charging period of the next stage.

A stage of the dynamic MOS logic circuit may include a single MOS transistor arranged to store a charge on its gate capacitance representing a data bit. Otherwise, the stage may include two such MOS transistors with their source-drain paths connected in series to produce a NAND function, or with their source-drain paths connected in parallel to produce a NOR function. More complex logical functions may be produced using series and parallel connection of combinations of MOS transistors. A stage may be connected to more than one succeeding stage.

In order that the invention may be fully understood and readily carried into effect an example of it and some modifications of it will now be described with reference to the accompanying drawings of which: FIGURE 1 shows diagrammatically part of a 2-stage shifting register circuit using a 4-phase clock; FIGURE 2 shows the waveforms of the four phases of the 4-phase clock used in Figure 1; FIGURE 3 shows a modification of part of the circuit shown in Figure 1 to execute a NAND function; FIGURE 4 shows another modification of part of the circuit shown in Figure 1 to execute a NOR function; FIGURE 5 shows a possible construction on an integrated circuit of the bipolar transistors of a development of the circuit of Figure 1; FIGURE 6 shows in diagrammatic form the cross-section of an integrated circuit including a bipolar transistor and a MOSFET of the circuit of Figure 1; and FIGURE 7 shows part of the top surface of an integrated circuit including two MOSFETs connected in series as shown in Figure 1.

Referring to the accompanying drawings, Figure 1 shows in diagrammatic form two stages of a shifting register which uses dynamic MOS logic technology. The first stage consists of a MOSFET 1 having its source connected to a positive supply conductor 2 and its drain connected to the source of another MOSFET 3, and an NPN bipolar transistor 4 having its emitter connected to a negative supply conductor 5 and its collector connected to the drain of the MOSFET 3. The second stage is of similar construction consisting of MOSFETs 6 and 7 and an NPN bipolar transistor 8. It should be noted that Figure 1 is drawn inverted with the negative supply conductor 5 at the top and the positive supply conductor 2 at the bottom.

An input to the first stage is applied via a conductor 9 to the gate of the MOSFET 1. A conductor 10 connects the drain of the MOSFET 3 and the collector of the bipolar transistor 4 to the gate of the MOSFET 6. The output to the next stage is fed via a conductor 11 connected to the drain of the MOSFET 7 and the collector of the transistor 8.

The four phases of a 4-phase clock system are indicated by #l, 2, #3 and #4 and are applied respectively to the base of the bipolar transistor 4, the gate of the MOSFET 3, the base of the bipolar transistor 8 and the gate of the MOSFET 7. Figure 2 shows the waveforms and relative timing of the four clock phases B1, #2, p3 and 4; in this figure a positive-going change of level is indicated conventionally by movement up the page.

Three capacitors C1, C2 and C3 are shown in Figure 1.

These capacitors are not provided as explicit components but represent the capacitances of the gates of the MOSFETs to which they are connected and the associated wiring. In the operation of the circuit a charge is stored by each of these capacitances which determines the conductivity of the MOSFET of which the gate provides most of the particular capacitance. The data bit stored by a stage depends on the voltage of the charge stored on the gate of the MOSFET. The allocation of the data bits "1" and "0" to high and low level charges can be made arbitrarily.

Suppose that the voltage of the charge stored on the gate of the MOSFET 1 is low, which will maintain the MOSFET 1 in a conducting state. At clock phase 21 the positive-going pulse on the base of the transistor 4 causes it to conduct and charge the gate of the MOSFET 6 negatively, i.e. to a low level. At clock phase #2 the negative-going pulse applied to the gate of the MOSFET 3 switches it to a conducting state, and since the MOSFET 1 is already in a conducting state the negative charge on the gate of the MOSFET 6 is discharged to the positive supply conductor 2. This leaves the voltage on the gate of the MOSFET 6 at a high level, which means that the MOSFET 6 is in a non-conducting state.

At clock phase 3 the transistor 8 is caused to conduct, as is the transistor (not shown in Figure 1) of which the collector is connected to the conductor 9. The gate of the MOSFET 1 and the capacitance represented by C3 become negatively charged. At clock phase #4, the MOSFET 7 conducts but, since the MOSFET 6 is non-conducting, the negative charge on the capacitance represented by C3 is not discharged. Also at clock phase #4 the gate of the MOSFET 1 may be discharged or not depending on the next data bit to be entered for propagation along the register.

During a complete cycle of four clock phases the representation of a data bit has been propagated from the base of the MOSFET 1 to the capacitance represented by C3.

This is similar to the operation of a conventional dynamic MOS logic circuit.

It will be apparent that the pair of stages formed by the components shown in Figure 1 to the left of the broken line 12 in that Figure can be repeated and connected in series to form longer shifting registers.

The use of the bipolar transistors 4 and 8 for precharging the MOSFET gate capacitances provides the high current, high voltage capabilities of bipolar technology in conjunction with the compact logic of dynamic MOS technology.

The bipolar transistors, which in the example of the invention under consideration are of NPN type, are fabricated as one inverted form of the conventional NPN structure. In this inverted form the n-type epitaxial layer forms the emitter and the N±type diffusion, which is located in the p-type base region and which usually forms the emitter, is used as the collector. This construction of the bipolar transistors has several advantages: 1. The small area of the N±type diffusion which forms the collector reduces the leakage current of the transistors especially at high temperatures.

As the leakage current decreases the charge stored on the MOSFET gate connected to the collector, any reduction in the leakage current improves the noise immunity of the circuit and give it a lower minimum clock frequency.

2. Normally configured NPN transistors have a large capacitive coupling to the substrate and to the isolation regions. The small area of the collector of the inverted NPN structure has much lower capacitances to the substrate and isolation regions. The switching on and off of the transistors by the clock signals means that the collector capacitances have to be charged and discharged. The reduction of the collector capacitances lowers the a.c. power loss resulting from the charging and discharging and consequently the unwanted power dissipation is reduced.

3. Alternate NPN transistors can have common emitters and base regions, so that all the NPN transistors can be formed in two compact common emitter tanks.

4. A usual disadvantage of bipolar transistors configured as inverted structures is that they have low gains. As the capacitance associated with the gate of a MOSFET is very small (say 0.3pF) the low gain of a bipolar transistor used to precharge it is not a significant disadvantage. The power of the clock pulses applied to the base of the transistor has to be larger because of the low gain but it is still small.

5. The voltage drop across the NPN transistor during the charging of the MOSFET gate capacitance can be as low as a few millivolts, so that the circuit can operate on a lower supply voltage than is needed when the charging current is controlled by a MOSFET. For conventional PMOS dynamic logic the minimum operating voltage is about 12 volts, whereas a circuit according to the invention can operate on 5-6 volts.

The example of the invention described above is a shifting register in which each stage merely stores the representation of a data bit ready to pass it on to the next stage. The simple storage element such as the MOSFET 1 of Figure 1 may be replaced by a combination of MOSFETs to give a logical function of two or more data bits. Figures 3 and 4 show two examples of such combinations.

In Figure 3, two MOSFETs 20 and 21 are shown with their source-drain paths connected in series from the supply conductor 2. The gate electrodes of the MOSFETs are respectively connected to receive two different signals, INPUT 1 and INPUT 2. These signals may, for example, come from stages of two different shifting registers of the type shown in Figure 1, being connected to the gates of MOSFETs 20 and 21 in the same way as an input is applied to the gate of the MOSFET 1 or the MOSFET 6. It is, of course, important that the charging and discharging respectively of the gates of the MOSFETs 20 and 21 take place in response to the same phases of the clock.In operation, the series connection of the MOSFETs 20 and 21 when used in place of the MOSFET 1 or 6 performs a logical AND function because the discharging of the gate of the MOSFET of the next stage requires both of the MOSFETs 20 and 21 to conduct.

In Figure 4 the MOSFETs 20 and 21, which may be connected to the rest of the circuit in the same way as they were as described above with reference to Figure 3, have their source-drain paths connected in parallel so that the circuit performs a logical NOR function of the two signals, INPUT 1 and INPUT 2. As with the circuit of Figure 3, it is important that the charging and discharging respectively of the gates of the MOSFETs take place in response to the same phases of the clock.

If more complicated logical functions are required then these can be built up from NAND and NOR functions realised by series and parallel connected combinations of MOSFETs. Because the current carried by the MOSFETs is only that required to discharge the capacitance of the gate of the MOSFET of the following stage the logic networks which can be produced in this way can be very complex.

The output of a stage of the shifting register shown in Figure 1 can be used to charge and selectively discharge the gates of more than one MOSFET, thereby providing a fan-out capability.

As shown in Figure 2, the pulses of clock phases 22 and 84 overlap the trailing edges of the pulses of phases #1 and 43 respectively. In an alternative scheme of clock pulses they do not overlap one another at all, which has the advantage that no direct current path exists between the supply conductors at any time and so the power consumption and dissipation is reduced, being only that required to charge and discharge the capacitances. However, with this alternative scheme care must be taken with charge sharing to avoid the charge on a MOSFET gate being dispersed to other capacitances in a complex logic network.

Figure 5 shows a possible integrated circuit layout for the bipolar transistors of an 8-stage shifting register of the type shown in Figure 1. For clarity of illustration the MOSFETs of the circuit are shown diagrammatically along a central strip in Figure 5. The bipolar transistors are divided into two groups according to the clock phase by which they are driven. An upper group of four transistors driven by clock phase #1 is indicated by the reference 50 and a lower group of four transistors driven by clock phase #3 is indicated by the reference 51. The group 50 of transistors has an isolated region 52 of a lightly doped n-type conductivity epitaxial layer which is used as a common emitter for all the transistors of the group, and is provided with an elongate ohmic contact 53 connected to the negative supply conductor.A base region 54, also common to all the transistors of the group, is formed by diffusion or ion implantation to be of p-type conductivity, and has a contact 55 connected to receive the pulses of clock phase ~1. The four transistors of the group have separate collectors, 56, 57, 58 and 59, of highly doped n-type conductivity material formed by diffusion or ion implantation in the common base region 54. Individual connections are made from the collectors 56, 57, 58 and 59 to the MOSFET circuits forming the remaining parts of alternate stages of a shifting register of the type shown in Figure 1.

The lower group 51 of transistors is constructed in the same way as the upper group 50 and similarly has four individual connections to the MOSFET circuit forming the remaining parts of intervening stages of the shifting register.

In an integrated circuit the two groups of bipolar transistors 50 and 51 would be formed in separate regions of the epitaxial layer surrounded by isolating barriers. The regions may conveniently be of elongate shape, not necessarily straight, located beside one or more other regions in which the MOSFETs are formed. The contacts to the common emitter and common base regions of the groups of transistors should extend along those regions to provide low impedance connections to those parts of the regions which contribute most to the functioning of the individual transistors. The construction of the groups of bipolar transistors in this way enables dynamic logic and storage elements to be realised particularly economically in terms of the area of semiconductor required.

Figure 6 shows in diagrammatic form the cross-section of parts of an integrated circuit with a bipolar transistor of the type included in the groups 50 and 51 of Figure 5 on the left and a MOSFET on the right. The integrated circuit is formed on a highly doped p-type conductivity semiconductor substrate 60, for example of silicon, on which is deposited an epitaxial layer 61 of lightly doped n-type conductivity material. Three highly doped p-type conductivity regions 62, 63 and 64 penetrating the epitaxial layer 61 from its surface to the substrate 60 divide the epitaxial layer 61 into two isolated regions 65 and 66.

In the left hand region 65 an NPN bipolar transistor is formed by making a p-type conductivity base region 67 in the surface of the region 65 and a highly doped n-type conductivity collector region 68 in the base region 67.

Emitter, base and collector contact metallisations 69, 70 and 71 are formed on the surface of the device, the emitter metallisation 69 being formed on a highly doped n-type conductivity region 72 to improve the connection of the metallisation to the lightly doped emitter region.

The MOSFET formed in the right hand region 66 has source and drain regions 80 and 81 of p-type conductivity material formed by diffusion or ion implantation in the surface of the region 66. The regions 80 and 81 are separated by a gap which form the channel of the device and is bridged by a gate 82 formed by a metal or polysilicon deposit on a thin oxide insulating film 83. Metallic source and drain contacts 84 and 85 are formed on the surface of the regions 80 and 81, respectively.

A possible configuration for the MOSFETs 1 and 3 of Figure 1 is shown in plan view in Figure 7. The same references as are used in Figure 1 are also used in Figure 7 for the same parts. The positive supply conductor 2 is connected at a contact 90 to a source 91 of MOSFET 1. The drain of MOSFET 1 and the source of MOSFET 3 are formed by a region 92. The drain 93 of MOSFET 3 is connected at contact 94 to a conductor 95 joining it to the collector of the bipolar transistor 4 (not shown in Figure 7). Gate 96 of the MOSFET 1 is joined to the conductor 9 and gate 97 of the MOSFET 3 is connected to receive the clock phase 02. The hatched areas represent the oxide insulation between the gates 96 and 97 and the surface of the epitaxial layer.

In order to ascertain whether the use of an inverted bipolar transistor would adversely affect the operation of dynamic MOS logic circuitry, it is necessary to establish if the collector-emitter leakage under the worst conditions envisaged for the use of the invention, for example, in a motor vehicle when the ambient temperature is +1250C, would be large enough to discharge the PMOS gate capacitance significantly within the clock pulse period.

To this end, d.c. leakage tests were performed on inverted", small NPN transistors at high temperatures (1500C) and the leakage proved to be less than SOn (50E-9A). Therefore, the rate of discharge of the PMOS gate capacitance (estimated to be greater than 0.3pF) is given by current 50 x 10-9 = ~~~~~~~~~~~~~ = 0.167 V/ps capacitance 0.3 x 10-12 This rate of discharge would permit a minimum operating frequency for the clock, allowing for a 2V collector-emitter leakage loss, of around 84 kHz at l500C.

This minimum frequency becomes approximately 12 kHz at l250C, assuming the leakage to be halved for every 100C temperature fall. This performance is comparable with that of a conventional dynamic MOS logic circuit. The inverted NPN transistor structure is especially advantageous in use because of its much lower collector-base area, reducing leakage and higher collector concentration, which also lowers the leakage as compared with conventional bipolar transistor structure. Such a conventional bipolar transistor would have a leakage current about five times larger, i.e. 150nA. The invention is of value in many applications where maximum system integration is required, together with a high current (approx 0.5A maximum) and a high voltage (approx 40V max) output.

Thus areas of application which would particularly benefit from this invention are: 1. Automotive applications with very low standby power needs, yet high current outputs to operate motors, relays and solenoids.

2. Special purpose applications with on-chip "actuation drive" yet low current logic circuit, such as timing functions able to withstand mains interruptions.

3. Applications in telecommunications requiring integrated circuits capable of working at low power (from line-power) yet capable of switching solenoids etc.

Claims (11)

CLAIMS:

1. A semiconductor logic circuit formed as an integrated circuit and having a plurality of sequentially connected stages, operated in use by multi-phase clock pulses, each stage including a data storage circuit having one or more MOSFETs, each selectively storing a charge on its gate capacitance affecting the conductivity of its source-drain path or of the combination of interconnected source-drain paths to indicate the data bit stored by the circuit, and a charging circuit including transistor means connected in series with the source-drain path of the MOSFET, or the combination of source-drain paths of the MOSFETs, of the data storage circuit of the particular stage from a supply conductor, and responsive to one phase of the clock pulses to apply current selectively to the gate of a MOSFET in the circuit of the or each immediately succeeding stage depending on the conductivity of the data storage circuit of the particular stage, wherein the transistor means in the charging circuit of each stage includes a bipolar transistor of which the collector region is contained within the base region which itself is contained within the emitter region and having its emitter connected to the supply conductor and receiving the particular phase of the clock pulses on its base thereby to cause current to flow periodically from its collector to the data storage circuit of the particular stage.

2. A circuit according to claim 1, wherein the bipolar transistors receiving the same phase of clock pulses have a common emitter region and a common base region with individual collectors to data storage circuits to form alternate stages of the logic circuit.

3. A semiconductor logic circuit formed as an integrated circuit having a substrate of a first conductivity type, an epitaxial layer on the substrate and of a second conductivity type opposite to the first, one or more isolating barriers of the first conductivity type penetrating the epitaxial layer from its surface to the substrate to divide the epitaxial layer into a plurality of electrically isolated regions, first and second pluralities of bipolar transistors formed in first and second electrically isolated regions of the epitaxial layer, each bipolar transistor having a base region of the first conductivity type in the epitaxial layer and a collector region of the second conductivity type in the base region, the bipolar transistors having regions of the epitaxial layer as emitter, a dynamic MOS logic circuit formed in one or more other electrically isolated regions of the epitaxial layer and having a plurality of interconnected stages each including at least one MOS transistor arranged to store a charge on its gate, and the controlled current paths of the successive stages being connected to the collectors of the bipolar transistors of the first and second pluralities alternately, whereby clock signals applied alternately to the bases of the bipolar transistors of the first and second pluralities enabling them to pass current to their collectors cause the charges stored on the gates of the MOS transistors to be stepped along the interconnected stages as determined by their interconnection.

4. A circuit according to claim 3, wherein each plurality of bipolar transistors has a region of the epitaxial layer forming a common emitter for those transistors, and within that region of the epitaxial layer there is formed a region which acts a a common base for those transistors.

5. A semiconductor logic circuit formed as an integrated circuit including a multistage dynamic MOS logic circuit using a 4-phase clock in which the precharging of the data storage circuits of the logic circuit is effected through two sets of bipolar transistors respectively rendered conducting by two phases of the clock, and each set of bipolar transistors has a common emitter region connected to a power supply conductor, a common base region formed within the common emitter region and connected to receive one phase of the clock and individual collector regions within the common base region connected to precharge the data storage circuits of alternate stages of the logic circuit, each stage of the dynamic MOS logic circuit including an additional MOS transistor controlled by a phase of the clock to isolate the data storage circuit of the stage from the next stage during at least the initial part of the charging period of the next stage.

6. A circuit according to any one of claims 1 to 5, wherein each data storage circuit or each stage of the dynamic MOS logic circuit includes a single MOS transistor arranged to store a charge on its gate capacitance representing a data bit.

7. A circuit according to any one of claims 1 to 5, wherein at least one data storage circuit or stage of the dynamic MOS logic circuit includes two MOS transistors having their source-drain paths connected in series and arranged to store charges on their gate capacitances representing respective data bits, so that the at least one data storage circuit or stage of the dynamic MOS logic circuit produces a NAND function of these data bits.

8. A circuit according to any one of claims 1 to 5 and 7, wherein at least one data storage circuit or stage of the dynamic MOS logic circuit includes two MOS transistors having their source-drain paths connected in parallel and arranged to store charges on their gate capacitances representing respective data bits, so that the at least one data storage circuit or stage of the dynamic MOS logic circuit produces a NOR function of those data bits.

9. A circuit according to any one of claims 1 to 5 and 7 and 8, wherein at least one data storage circuit or stage of the dynamic MOS logic circuit includes at least three MOS transistors having their source-drain paths connected in a series-parallel combination and arranged to store charges on their gate capacitances representing respective data bits, so that the at least one data storage circuit or stage of the dynamic MOS logic circuit produces a logical function of those data bits.

10. A circuit according to any preceding claim wherein at least one data storage circuit or stage of the dynamic MOS logic circuit is connected to at least two other data storage circuits or stages of the dynamic MOS logic circuit.

11. A semiconductor logic circuit substantially as described herein and as illustrated by the accompanying drawings.