GB2135549A - Semiconductor integrated circuits - Google Patents
Semiconductor integrated circuits Download PDFInfo
- Publication number
- GB2135549A GB2135549A GB08329900A GB8329900A GB2135549A GB 2135549 A GB2135549 A GB 2135549A GB 08329900 A GB08329900 A GB 08329900A GB 8329900 A GB8329900 A GB 8329900A GB 2135549 A GB2135549 A GB 2135549A
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- Prior art keywords
- circuit
- series
- transistors
- node
- series circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
Abstract
A semiconductor circuit comprises two series circuits of IGFETs between first and second nodes, and means for supplying the same signals to both series circuits to determine the logic state of the first node (OUT). The circuit may be fabricated with two IGFETs, TR21 and TR22, sharing a common impurity- doped region which corresponds to the first node. <IMAGE>
Description
SPECIFICATION
Improvements in or relating to semiconductor integrated circuits
The present invention relates to integrated circuits.
Insulated gate field effect transistors (hereinafter abbreviated as IGFET's) have been widely utilized in digital integrated circuits because they are suitable for high-density circuit integration and can operate at a low power consumption. A basic operation of an IGFET as a logic element in a digital circuit is such that an input signal is applied to its gate to control ON and OFF states of IGFET and an output signal in response to the input signal is derived from its drain or source. In a digital logic circuit, a combination circuit such as NOR circuits, NAND circuits, etc. and a sequential circuit such as a flipflop, shift register, etc. are used in various combinations depending upon logic function and application. Such digital logic circuit can be deemed to be basically a combination of AND circuits, OR circuits and NOT circuits.Especially, in a complementary IGFET integrated circuit, the circuit construction is clear and definite.
As is well known, an IGFET is a voltageresponsive logic element, and its gate can be deemed to be equivalent to a capacitor. On the other hand, a signal source for supplying an input signal to the gate and wirings leading from the signal source to the gate, respectively, have finite impedances. Consequently, the response in an effective signal level at the gate of IGFET is necessarily delayed by a time constant formed by the gate capacitance of the IGFET and the aforementioned impedances, which makes it difficult to realize high-speed logic operations.
Moreover, since an electric charge stored in the gate capacitance is repeatedly charged and discharged upon respective switching operations, it has been also difficult to further reduce a power consumption. In addition, not only the gate capacitance of the IGFET, but also the capacitances of the source and drain of the IGFET serve to slow down the switching operations, and at the same time these capacitances are superposed on the gate capacitance of the IGFET in the next stage, resulting in lowering of the speed of the logic operations of the circuit as a whole.
It is therefore one object of the present invention to provide an integrated circuit that can operate at a high speed.
Another object of the present invention is to provide an integrated circuit that can operate at a very low power consumption.
According to the invention there is provided a semiconductor circuit comprising a first node, a second node, a first series circuit of a plurality of insulated gate field effect transistors connected in series between said first and second nodes, a second series circuit of a plurality of insulated gate field effect transistors connected in series between said first and second nodes, the number of the transistors in said first series circuit being equal to that in said second series circuit, means for supplying said second node with a predetermined voltage, means for receiving a plurality of signals, first means for applying said plurality of signals to said first series circuit, and second means for applying said plurality of signals to said second series circuit, wherein said first and second series circuits co-operate to determine a logic state of said first node in response to said signals.
A preferred embodiment of the present invention is an integrated circuit including a series circuit of a given number of IGFET's connected in series in their drain-source direction, each IGFET in the series circuit being divided into a pair of identical IGFET's having a conductance of a half of the original IGFET, and the series circuit being divided into two sub-series circuits: one subseries circuit containing one of each pair of divided IGFET's, the other sub-series circuit containing the other of each pair of divided
IGFET's, the two sub-series circuits being connected in parallel. One of the junctions of the parallel-connected sub-series circuits is made a common drain or source region of one pair of the divided IGFET's, so that the parasitic capacitance of the source or drain regions of that pair of the
IGFET's is reduced.
A further embodiment is an integrated circuit comprising a plurality of transistor groups each consisting of a plurality of IFGET's connected in series, in which the same signal lines are distributed to the respective transistor groups to make the respective transistor groups achieve substantially the same logic operations, and one ends of the respective transistor groups are formed in common.
A further embodiment is an integrated circuit comprising a plurality of transistor groups each consisting of a plurality of IGFET's connected in series, in which the gate electrodes of such transistor groups are connected to the same signal lines according to the sequence of connection of the transistors in the respective transistor groups.
In a further embodiment of the present invention, there is provided an integrated circuit comprising a semiconductor substrate provided with a region of one conductivity type, a first region of the opposite conductivity type having a rectangular shape and provided in said one conductivity type region, a plurality of second regions of the opposite conductivity type provided substantially in parallel to one edge of said first region as isolated sequentially at discrete distances from said one edge and isolated from each other, a plurality of third regions of the opposite conductivity type provided substantially in parallel to another edge of said first region as isolated sequentially at discrete distances from said one edge and spaced from each other, a plurality of first conductive patterns provided via an insulating film on the respective regions between said one edge of said first region and the nearest one of said plurality of second regions and between adjacent ones of said second regions, that is, on the channel regions, a plurality of second conductive patterns provided via an insulating film on the respective regions between said another edge of said first region and the nearest one of said plurality of third regions and between adjacent ones of said third regions, that is, on the channel regions, a plurality of signal wirings each connecting one of said first conductive patterns to the corresponding one of said conductive patterns, and a common wiring for connecting in common the second region located at the farthest end from said first region and the third region located at the farthest end from said first region, whereby an output signal can be derived from said first region.
In the integrated circuit according to the present invention, a parasitic capacitance especially of a drain region serving as an output node where charging or discharging is effected upon each switching, can be remarkably reduced without degrading a driving capability of a transistor. Accordingly, a logic integrated circuit that can achieve a high speed operation as well as a very low power consumption operation, is realized.
The invention will now be described, by way of example, with reference to the accompanying drawings, in which:~
Figure 1 is a schematic circuit diagram showing a standard known NAND circuit consisting of N-channel MOS transistors;
Figure 2 is a plan view of an integrated circuit in which the NAND circuit shown in Figure 1 is realized according to the prior art;
Figure 3 is an equivalent circuit diagram of a
NAND circuit constructed according to the present invention;
Figure 4 is a plan view of an integrated circuit according to the present invention as applied, by way of example, to a 2-input NAND circuit;
Figure 5 is a schematic plan view showing distribution of capacitances in the transistor layout shown in Figure 2;;
Figure 6 is a schematic plan view similar to
Figure 5 showing distribution of capacitances in the integrated circuit according to the present invention shown in Figure 4;
Figure 7 is a diagram representing proportions in percent of a pattern area and a peripheral length according to the present invention with reference to those in the case of employing the art work method in the prior art as a function of a channel width W, and
Figure 8 is a layout diagram showing another preferred embodiment of the present invention.
Referring now to Figure 1 of the drawings, there is shown a standard 2-input NAND circuit in the prior art, which is constructed of N-channel transistors. This circuit is composed of a load transistor TR 1 and drive transistors TR2 and TR3.
Normally the channel widths of the drive transistors TR2 and TR3 are identical to each other.
If the section of the drive transistors in this circuit is patterned according to the prior art method, the layout of the pattern will become as shown in Figure 2. More particularly, a mere series connection of transistors TR2 and TR3 is formed by providing gate electrodes 2 and 3 between N-type regions 1 and 5 and between Ntype regions 5 and 4, respectively. The region 4 which is not shared by the respective transistors is used as a ground terminal, while the region 1 is used as an output terminal (OUT). This method of patterning called "art work method" is simple and clear, and hence it is generally employed at present. However, in the case where load to be driven is heavy, for the purpose of enhancing driving capabilities of the drive transistors TR2 and TR3, not to speak of the load transistor TR1, the widths W of these transistors must be enlarged.However, in accordance with the increase of the widths W, the areas of the respective diffusion regions are increased, and thus the capacitances at the respective nodes would be increased. Moreover, the resistances of the polycrystalline silicon layers forming the gate electrodes 2 and 3 of the drive transistors TR2 and TR3 would be also increased up to an unnegligible extent.
Accordingly, even if driving capabilities should be enhanced by enlarging the channel widths W, from the view point of speeding up the circuit an improvement proportional to the increase of the widths would not be achieved according to the prior art.
Figure 3 shows a 2-input NAND circuit, which can achieve a similar function to the circuit shown in Figure 1 and which embodies the basic principle of the present invention. In order that the circuit shown in Figure 3 becomes equivalent to the circuit shown in Figure 1, it is necessary that when the current amplification factors of the drive transistors TR2 and TR3 are represented by p2 and p3, respectively, and the current amplification factors of the drive transistors TRZ 1, TR22,TR31 and TR32 are represented by#21,#2, p3r and p32t respectively, these amplification factors fulfil the conditions of: : p2=p21 +p22t p3=p31 +p32- By fulfilling these conditions, the necessity of connecting the drain electrode of the drive transistor TR3 1 (or the source electrode of the drive transistor TR2 1 ) at point A in Figure 3 to the drain electrode of the drive transistor TR32 (or the source electrode of the drive transistor TR22) at point B is eliminated, and yet the circuit shown in
Figure 3 becomes equivalent to that shown in
Figure 1.
With reference to Figure 4, one detailed embodiment of the present invention will be explained where only the section of drive transistors in the circuit shown in Figure 3 is realized according to the present invention.
In Figure 4, on one principal surface of a P-type semiconductor substrate are disposed N-type regions 8 and 21 serving as a source and a drain, respectively, of a transistor To31, an N-type region 22 serving as a drain of a transistor TR2 1 and also as a drain of a transistor TR22, an N-type region 23 serving as a source of the transistor
TR22 and also as a drain of a transistorTR32, and an N-type region 13 serving as a source of the transistor TR32 as directed in the same direction.
A polycrystalline silicon layer 6 forms a gate electrode wiring for the transistors TR21 and
TR22, and a polycrystalline silicon layer 7 forms a gate electrode wiring for the transistors TR31 and
TR32. From a contact 15 provided in the N-type region 22 is led out an output terminal OUT shown in Figure 3. A source of a load transistor
TR1 may be connected to the contact 1 5 by a known method (not shown), contacts 12 and 14 provided in the N-type regions 8 and 13, respectively, are both connected to a grounded terminal of a power supply. In the layout shown in
Figure 3, the widths of the respective N-type regions are selected about 1/2 times as small as those in the layout shown in Figure 2.As described above, according to the present invention, the capacitance of the region 22 corresponding to an output terminal which may possibly affect the circuit performance can be reduced as compared to an integrated circuit patterned according to the prior art method, owing to the fact that two sets of series patterns are formed by dividing the widths W of the transistors into two equal parts and patterning is effected so that the two series patterns may share a drain region at one ends.
Now the effects and advantages of the present invention will be explained in greater detail with reference to Figures 5 and 6. At first, consideration will be made on a capacitance of the drive transistors in the prior art shown in
Figure 2 as viewed from an output node contact 11 corresponding to an output terminal OUT in an output transistor section. In this case, a capacitance of a region 1 corresponding to the drain of the drive transistor TR2 and a capacitance of a region 5 corresponding to the source of the drive transistorTR2 and the drain of the drive transistorTR3 would affect the output.
On the other hand, since a region 4 corresponding to the source of the drive transistor TR3 is fixedly held at the ground potential, the effect of the capacitance of this region 4 can be neglected.
In the respective cases shown in Figures 5 and 6, it is assumed hereunder that as a rule, in the drain region forming an output node, an interval of 4 microns is provided between the periphery of the output contact and the periphery of the gate electrode and an interval of 2 microns or more is provided between the output contact and the edge of the drain region. Also it is assumed that the width of the contact is 3 microns and the minimum impurity region width is 4 microns. In
Figure 5, the length of the drain region 1 is represented by 111, its width is represented by W.
The length of the region 5 is represented by 1,2 and the width of the same is also represented by
W. In this figure, reference symbol 114 designates the distance between the gate electrode 2 and the contact 11, which is 4 microns as described above. Reference symbol 113 designates the distance between the contact 11 and the edge of the drain region 1, which is 2 microns. Reference symbol 115 designates the width of the contact 11, which is 3 microns.
At first, denoting a bottom capacitance per unit area by reference symbol CA, the capacitance C, formed between the bottom surfaces of the regions 1 and 5 and the substrate is represented by the following equation: Cll=CA (Wxl11+VVxI12) =CA ~ W(I11+l12). (1)
Substituting i11=9 (microns) and 112=4 (microns) into Equation (1) above, we obtain:: C11=CA ~ W(9+4) =1 3 CA W ~W (2)
On the other hand, the capacitance C12 formed by the side surfaces (wall surfaces) of the regions 1 and 5 is represented by the following equation when the capacitance per unit area of the side surface is represented by reference symbol CB: C12=CB ~ (2 ~ I"+W+2 ~ 112) (3)
Substituting the above-referred numerical values of the lengths 111 and 112 into Equation (3) above, we obtain:: C12=CB (2x9+W+2x4) =CB ~ (28+W) (4)
Therefore, the total capacitance C13 is represented by the following equation:
C13=C1 1 +C12
=W(1 3CA+CB)+28CB (5)
Now consideration will be made on the
preferred embodiment of the present invention shown in Figure 4, with reference to Figure 6. In this preferred embodiment, the widths of ail the impurity regions serving as a drain or a source are chosen about 1/2 times as small as the width in the case of the prior art layout shown in Figure 5.
In this case, the capacitance as viewed from the output control 1 5 is equal to the sum of the capacitance of the region 21, the capacitance of the region 22 and the capacitance of the region 23. Similarly to the case shown in Figure 5, the capacitance C21 formed by the bottom surfaces of the respective regions is represented by the following equation:
1 1 C21=CA ~ (-'N 121+2 W 122) (6) 2 2
As mentioned previously in connection to
Figures 5 and 6, the length 126 is 3 microns and
the lengths 124 and 126 are respectively 4 microns.
Hence the length 121 is equal to 11 microns, and
also the lengths 123 and 122 are respectively 4
microns. Therefore, substituting these numerical values into Equation (6), we obtain: 1 2 =9.5C,W (7)
Considering now the side surface capacitance
C22 in the same manner as described above, it is represented by the following equation: Q2=C6 ~ (2 - 121 +4121+4 122) (8) Substituting the numerical values of the lengths 121 and 122 into Equation (8) above, we obtain: C22=38CB (9) Accordingly, the total effective capacitance C23 is given by the following equation::
C23=C21 +C22=9.5CA ~ W+38C6 (10)
Now the capacitance reduction ratio R of the layout shown in Figure 6 with respect to the prior art layout shown in Figure 5 will be considered. A reduction ratio R11 of the bottom surface capacitance is given by the following equation:
Also, a reduction ratio R12 of the side surface capacitance is given by the following equation:
Thus it will be understood that the reduction ratio
R12 is substantially inversely proportional to the value of the width W.
Here, if the following numerical values are employed as representative values: W=150,u CA=2.3X 10-4 pF/u2, and C6=4.Ox 1 0-4 pF/y.
then according to Equation (5), the total effective capacitance C13 becomes 0.5197 pF. On the other hand, according to Equation (10), the total effective capacitance C23 becomes 0.3429 pF.
Therefore, according to the present invention, really reduction in the total effective capacitance of as large as 34% can be achieved.
Figure 7 shows the effects of the present invention on the basis of the above-mentioned results of consideration, in which capacitance proportions of the pattern area and peripheral length of the layout according to the present invention with respect to those of the layout formed by the art work method in the prior art which are used as a reference, are represented in per cents. In this figure, a channel width W of the drive transistors is taken along the X-axis, and the capacitance proportions of the pattern area and peripheral length are taken in per cents along the
Y-axis. A curve 111 represents a reduction ratio
R11 of the pattern area, while a curve 1 12 represents a reduction ratio R12 of the peripheral length as a function of the channel width W.It will be readily seen from Figure 7 that the reduction ratio R11 is held substantially constant at 73% for every value of the channel width W, whereas the reduction ratio R12 is reduced as the channel width W is increased. Although comparison is made with respect to geometrical dimensions in
Figure 7, the effects of reducing the parasitic capacitances will be readily appreciated if the capacitance per unit area CA or the capacitance per unit length CB is taken into consideration.
Another preferred embodiment of the present invention is illustrated in Figure 8, in which with respect to impurity regions 82 and 83 formed between an output node 80 and respective regions 87 and 89 to be held at the ground potential, common gates 85 and 86 are formed respectively in a pattern of rotational symmetry, and similar effects to those of the embodiment shown in Figure 4 can be expected from this modified embodiment.
As described above, in general, capacitances of the impurity regions are represented by a sum of a term proportional to a pattern area and a term
proportional to a peripheral length of a pattern, and the effects of the present invention making use of the above principle can be realized by placing a pattern of an output terminal between the gate polycrystalline silicon layers of the drive transistors TR2 1 and TR22, because in such a layout both the pattern area and peripheral length of the output region can be reduced. Moreover, since the proposed pattern layout is symmetric with respect to its longitudinal and transverse directions, even if any deviation should arise in pattern registration, the deviation would little affect, the performance of the transistors. In addition, owing to the fact that the drive transistors are respectively divided into two parts, the resistance of the gate polysilicon layer is also reduced, and this contributes to reduction of a delay time. The above-mentioned effects of the present invention become more remarkable as the channel widths of the drive transistors are increased.
As described in detail above, accqrding to the present invention, the circuit performance can be improved by merely making device on the art work without providing any special pattern, and since the pattern layout is symmetric with respect to its longitudinal and transverse directions, even if any deviation should arise in pattern registration, the driving capability as well as node capacitances of the transistor would be little varied. The above-described embodiments of the present invention are no more than one example employing N-channel transistors, and the invention is not limited to a circuit employing Nchannel transistors but the invention can be equally applied to the art work of a circuit employing P-channel transistors or complementary transistors. Especially, if the invention is applied to the art work of a complementary IGFET integrated circuit, the frequency of use of the present invention is enhanced and thus it is favorable. In addition, as a matter of course, the present invention is equally applicable to a series construction consisting of three or more transistors.
Claims (3)
1. A semiconductor circuit comprising a first node, a second node, a first series circuit of a plurality of insulated gate field effect transistors connected in series between said first and second nodes, a second series circuit of a plurality of insulated gate field effect transistors connected in series between said first and second nodes, the number of the transistors in said first series circuit being equal to that in said second series circuit, means for supplying said second node with a predetermined voltage, means for receiving a plurality of signals, first means for applying said plurality of signals to said first series circuit, and second means for applying said plurality of signals to said second series circuit, wherein said first and second series circuits co-operate to determine a logic state of said first node in response to said signals.
2. The circuit according to claim 1, further comprising load means for supplying said first node with an electric charge.
3. A semiconductor circuit as claimed in claim 1 , the circuit being constructed, arranged and adapted to operate substantially as hereinbefore described with reference to, and as illustrated in,
Figures 3, 4, 6, 7 and 8 of the accompanying drawings.
3. The circuit according to claim 1, in which all the transistors in said first and second series
circuits have the substantially same channel width.
4. A semiconductor circuit constructed,
arranged and adapted to operate substantially as
hereinbefore described with reference to, and as illustrated in, the accompanying drawings.
New Claims or Amendments to Claims Filed on
16 April 1984
Superseded Claims 1 to 4
New or Amended Claims:~
1. A semiconductor integrated circuit comprising a plurality of input terminals, an output terminal, a reference potential terminal, a power supply terminal, a first series circuit of a plurality of first insulated gate field effect transistors, the source-drain paths of said first transistors being directly connected in series between said output terminal and said reference potential terminal, a second series circuit of a plurality of second insulated gate field effect transistors, the source-drain paths of said second transistors being directly connected in series between said output terminal and said reference potential terminal, the number of said first transistors in said first series circuit being equal to that of said second transistors in said second series circuit and also equal to that of said input terminals, means coupled between said output terminal and said power supply terminal for supplying said output terminal with a predetermined voltage, and means for connecting each of said input terminals to the gate electrode of a respective one of said first transistors and to the gate electrode of a respective one of said second transistors, wherein said first and second series circuits co-operate to determine a logic state at said output terminal in response to signals at said input terminals.
2. The circuit according to claim 1, in which said supply means is a load transistor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2997280A JPS56125854A (en) | 1980-03-10 | 1980-03-10 | Integrated circuit |
| GB8107353A GB2074372B (en) | 1980-03-10 | 1981-03-09 | Integrated circuit field effect transistors |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8329900D0 GB8329900D0 (en) | 1983-12-14 |
| GB2135549A true GB2135549A (en) | 1984-08-30 |
| GB2135549B GB2135549B (en) | 1985-03-20 |
Family
ID=26278704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08329900A Expired GB2135549B (en) | 1980-03-10 | 1983-11-09 | Semiconductor integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2135549B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2224160A (en) * | 1988-10-24 | 1990-04-25 | Marconi Instruments Ltd | Integrated semiconductor circuits |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1509976A (en) * | 1975-02-27 | 1978-05-10 | Rca Corp | Logic circuit |
| GB1568396A (en) * | 1975-10-06 | 1980-05-29 | Tokyo Shibaura Electric Co | Complementary mos logic circuit |
| GB2059706A (en) * | 1979-08-15 | 1981-04-23 | Nippon Electric Co | Driver circuit |
-
1983
- 1983-11-09 GB GB08329900A patent/GB2135549B/en not_active Expired
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1509976A (en) * | 1975-02-27 | 1978-05-10 | Rca Corp | Logic circuit |
| GB1568396A (en) * | 1975-10-06 | 1980-05-29 | Tokyo Shibaura Electric Co | Complementary mos logic circuit |
| GB2059706A (en) * | 1979-08-15 | 1981-04-23 | Nippon Electric Co | Driver circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2224160A (en) * | 1988-10-24 | 1990-04-25 | Marconi Instruments Ltd | Integrated semiconductor circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8329900D0 (en) | 1983-12-14 |
| GB2135549B (en) | 1985-03-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PE20 | Patent expired after termination of 20 years |
Effective date: 20010308 |