GB2072947A - Junction type field effect semiconductor device and a method of fabricating the same - Google Patents

Abstract

A contact (4) to a region (14) of a semiconductor device extends through a window in a series of surface layers at least one (1) of which is of polycrystalline semiconductor material the edge of which is oxidised (27) to define, at least in part, the window. A junction type field effect semiconductor device has a drain region (11) of one conductivity type formed on a surface of a low impurity density single crystal region (13) of the same conductivity type. A gate region (14) of the opposite conductivity type encloses the drain region (11). A polycrystal region (1) is formed on the drain region (11) and a contact window is formed with a part determined by a side oxidation film (27) on the polycrystal region (1). This contact window is used to receive conducting material (4) connected to the gate region. Also disclosed in the application are methods of fabricating junction type field effect semiconductor devices of this type. <IMAGE>

Description

SPECIFICATION Junction type field effect semiconductor device and a method of fabricating the same This invention relates to junction type field effect semiconductor devices, for example, vertical type SITs, FETs and integrated circuits incorporating the same, and to methods of fabricating junction type field effect semiconductor devices.

Considering an inverted type SIT as an example, a SITL with a lateral bipolar transistor (BJT) as a load has an ultra low value of the product of power consumption and delay time such as 1 to 2 fj/gate, and so a high speed operation in the order of sub-nano seconds can be carried out. Moreover, the performance is superior to that of l2L.

Although the performance can be obtained relatively easily by the use of a 2 to 5 ym design rule process, of course, higher performance could be obtained if a finer pattern rule is employed.

However, there are problems when a finer pattern rule is employed, one of these problems being the reduction of channel width (gate space) due to the reduction in gate area. Another problem is how to position precisely and form an extremely small drain region within the reduced gate space. The usual way of reducing gate area is to reduce the area of a window used for selective diffusion at the time of the formation of a gate region.

However, there are some technical limitations.

Another method is reduce the cross-sectional area of the channel. As a result, the gate space becomes smaller. When the window, which is formed in the reduced channel cross-sectional area for the purpose of forming the drain region, is larger in size than desirable or when the window is not positioned in the desired position, a gate high impurity density region and a drain high impurity density region often overlap. As a result, junction capacity between the gate and the drain becomes so large that the improvement in performance is not achieved even though the gate space is reduced. Therefore, it is necessary to position the window for the formation of the drain region with an accuracy of less than 1 ,um. Even an accuracy of +0.5 ym obtained by normal auto-alignment techniques is not sufficient.A similar problem exists in the region between the source and the gate of a vertical-type SIT or FET. To form a normally off type SITL, a reduced gate space is required, and a reduced gate space is also required for a normally on type SITL in order to improve control efficiency (rl) of gate voltage and to increase the value of gm.

According to one aspect of the present invention there is provided a junction type field effect semiconductor device comprising a main electrode single crystal region of one conductivity type formed on a surface of a low impurity density single crystal region of the said one conductivity type, a gate region of the opposite conductivity type enclosing said main electrode single crystal region on said surface, a polycrystal region formed either on said main electrode single crystal region or on said gate region, and a contact window in a portion of the gate region, the contact window having at least a part which is defined by a side oxidation film formed on said polycrystal region, said contact window being used to receive conducting material connected to said gate region.

In one embodiment the polycrystal region is provided on said main electrode single crystal region and acts as a wiring member therefor, a conductive wiring material connected to said gate region being provided on said polycrystal region but isolated therefrom by the side oxidation film and an upper oxide film on said polycrystal region.

In another embodiment the polycrystal region is provided on said gate region, a window being defined by an inner side oxidation film on said polycrystal region, said main electrode single crystal region being formed on a surface of said low impurity density single crystal region.

According to a further aspect of the present invention there is provided a method of fabricating a junction type field effect semiconductor device comprising the steps of: selectively forming a first gate region of an opposite conductivity type on a major surface of a low impurity density single crystal region of one conductivity type and coating said major surface with a first insulation film; forming a multi-layer film consisting of a second insulation film and a polycrystal layer on said first insulation film and forming a window through the multi-layer film and the first insulation film to expose a region of said low impurity density region; forming a thermal oxidation film on at least the side face of said polycrystal layer bordering said window; forming a second gate region of said opposite conductivity type after said low impurity density region in the window is exposed again; and defining a contact window by re-exposing the said exposed region and forming gate wiring so as to cover one portion of said second insulation film and said contact window.

Said second insulation film may be or may include a silicon nitride film.

Preferably one conductivity type impurity is contained in the surface of said polycrystal layer at the time of deposition, the remainder of the polycrystal layer having a low impurity density.

According to still another aspect of the present invention a method of fabricating a junction type field effect semiconductor device comprises the steps of: forming an island-like insulation film consisting of at least two layers one of which is a nitride film and the other of which is an oxide film on a surface of a low impurity density region of one conductivity type and forming a selective oxidation film; depositing at least a first polycrystal layer after a first window is formed between an end portion of said selective oxidation film and an end portion of said island-like insulation film, the size of said first window being defined by the side-etched portion of one layer of said island-like insulation film; exposing a portion of the first polycrystal layer which substantially corresponds to said first window and removing the first polycrystal layer on said island-like insulation film to form a second window; and forming the second window by removing a portion of said island-like insulation film after oxidising the exposed portion of the remaining first polycrystal layer, so that an opposite conductivity type gate region is formed by the use of the first window, a main electrode region of said one conductivity type being formed by the use of the second window, and a channel region being formed in the low impurity density region.

The opposite conductivity type impurity may be added to at least one portion of said first polycrystal layer before the oxidation of the exposed portion thereof.

Preferably a second polycrystal layer of said one conductivity type is deposited in the second window and the second polycrystal layer is used as a portion of wiring for a main electrode. At least one nitride film may be deposited on said first polycrystal layer, said portion of main electrode wiring formed by said polycrystal layer being formed after the oxidation and the formation of the second window, a portion of the first polycrystal layer being exposed by removing said nitride film on the first polycrystal layer after the oxidation, and subsequently providing wiring for the gate electrode.

In a preferred embodiment the impurity density of the first polycrystal layer is relatively low, an opposite conductivity type gate region being formed through the first polycrystal layer and the first window after the nitride film on the first polycrystal layer has been removed, a gate electrode and its wiring then being formed.

The invention is illustrated, merely by way of example, in the accompanying drawings, in which: Figure 1 a is a plan view of an inverted type SIT according to the present invention; Figures 1 b and 1 c are cross-sectional views taken on lines A-A' and B-B' in Figure 1 a, respectively; Figures 2a to 2e are cross-sectional views illustrating the steps of fabricating a SIT by a method according to the present invention; Figures 3a to 3g are cross-sectional views illustrating the steps of fabricating a junction type field effect semiconductor device by another method according to the present invention; Figure 4a is a plan view of an inverted type SIT according to the present invention;; Figures 4b and 4c are cross-sectional views taken on the lines A-A' and B-B' in Figure 4a respectively; Figures 5a to 5g are sectional views illustrating the steps of fabricating a l2L type SITL by a further method according to the present invention; Figures 6a to 6e are sectional views illustrating the steps of fabricating an inverted type SIT by yet another method according to the present invention; and Figures 7a to 7h are sectional views illustrating the steps of fabricating a 12L type SITL by a yet further method according to the present invention, Figure 7h being a partial sectional view perpendicular to the section shown in Figure 7g.

Throughout the drawings like parts have been designated by the same reference numerals.

Figure 1 illustrates a junction type field effect semiconductor device according to the present invention as a vertical type SIT or FET.

Figure 1 a is a plan view of the semiconductor device, insulation films being omitted for clarity.

Figures 1 b and 1 c are sectional views taken on the lines A-A' and B-B' of Figure 1a respectively. In the case of an inverted type SIT, an n+ single crystal source region 12, which is one of the main electrodes of the SIT, is constituted by a substrate or buried layer. The SIT has an n+ polycrystal layer 1, an n+ drain region 11 and an n region 13 which acts as a channel region between the drain region 11 and the source region 12. The drain region 1 1 is enclosed by p+ gate regions 114 which are formed on the surface thereof.

A gate electrode 4 is in contact with the gate region 14 which is C-shaped, and the upper face of the gate region 14 is isolated from the polycrystal layer 1 by an oxidation or insulation film 17 of, for example, silicon dioxide (SiO2) or silicon nitride (Si3N4). The side face of the gate region 14 is isolated from the polycrystal layer by an oxidation or insulation film 27 in a similar manner. The polycrystal layer 1 is also isolated from the p+ gate region 114 by an oxidation or insulation film 7.

With this structure, gate space W depends upon the width of the polycrystal layer and the insulation film 27 on the side face, and the realisation of a fine pattern depends upon the technique used for cutting the polycrystal layer 1.

An n+ polycrystal layer 1 of 1 to 2 m thickness can easily be realised. The contact portion of the p+ gate region 14 in contact with the gate electrode 4 effectively acts as a gate and therefore a p+ region used for a contact hole can be omitted.

From the point of view of capacitance, the insulation films 7, 17, 27 are preferably as thick as possible.

An inverted type n channel SIT has been described in relation to Figures 1 a to 1 c but it will be appreciated that the present invention is equally applicable to a vertical type p channel SIT or FET.

Figures 2a to 2e are cross-sectional views taken on the line A-A' of Figure 1 a to illustrate the steps of forming the SIT of Figures 1 a to 1 c by a method according to the present invention. The source region 12 is omitted from these Figures for clarity. In Figures 2a, the n region 13 is deposited on the n+ source region 12 by an epitaxial growth technique, and the p+ gate region 1 14 is formed by a selective diffusion technique and subsequent oxidation thereof after coating with the insulation film 7. For the subsequent steps, it is preferable that the p+ gate region# 1 14 is not too deep and the oxidation film 7 is relatively thick. A high pressure oxidation technique or a CVD technique or a plasma deposition technique is preferable.

In Figure 2b, a window is formed in the insulation film 7 so as to correspond to the portion at which the SIT is to be formed in the following steps, and silicon polycrystal layers 1, 101 and oxide or nitride insulation films 1 7, 117 are deposited by conventional technique. After this, a portion of the insulation film 17 and the polycrystal layer 1 corresponding to the portion at which the p+ gate region 14 is to be formed in the form of a letter C are removed. The polycrystal layers 1, 10 are n+ doped polycrystal or low impurity density polycrystal and n type impurity is deposited therein before the deposition of the insulation films 1 7, 117. For the following steps, the diffusion coefficient of the added impurity is preferably small (such as As or Sb) and B may be used forp type semiconductor devices.Also all the polycrystal layer 101 except for the portion acting as drain n+ polycrystal layer 1 can be removed.

However, a portion may be left as shown in Figure 2b Of course, the p+ gate region 14 which will be formed in a later step is desired to be slender. This is so as to obtain more accurate positioning or on the basis of the line width employed in the masking step. It is preferable to leave the polycrystal layer 1 when greater accuracy of the line width is required, and it is preferable to remove the polycrystal layer 101 and the insulation film 11 7 when positioning accuracy is more important than that of line width. In this step, the positions, sizes and width of the n+ drain region 11 and the p+ gate region 14 are determined.

Figure 2c is a sectional view in which oxidation films 27, 37 are formed on side faces of the polycrystal layers 1, 101 and the surface of the n region 13 by a thermal oxidation technique. A steam oxidation or a high pressure oxidation technique is suitable for this in order to suppress enlargement of other regions due to diffusion. The thickness of the oxidation film 27 on the side faces of the polycrystal layers 1, 101 is greater than that of the oxidation film 37 on the n region 13.

Since n type impurity of relatively high impurity density is added to the polycrystal layers 1, 101, it is easily liable to oxidise at high speed, for example, 1.3 to 2 times as fast.

Since the surfaces of the polycrystal layers 1, 101 are coated with the insulation films 17, 117, oxidation is not affected. In Figure 2d, the oxidation film 37 on the n region 13 is removed by a directional plasma etching technique or an ion etching technique without cutting the oxidation film 27 on the side face of the polycrystal layers 1, 101. Since the insulation films 17, 11 7 are also subjected to etching at the same time, it is necessary either that the insulation films 17, 117 are sufficiently thicker than the oxidation film 37 or that the material of the insulation films 17, 117 is not liable to be etched.Figure 2e is a sectional view in which the window so formed is employed for forming the p+ gate region 14 by a selective diffusion technique, and the gate electrode 4 and a drain electrode 1' are formed at the same time. It is preferable that the diffusion technique for forming the p+ gate region is carried out in a non-oxidising atmosphere or dry oxygen, and that the oxidation film is not coated or a thin oxidation film is formed. Therefore a large current ion injection technique is preferable to the deposition of boron glass.

An inverted type SIT is obtained by the abovedescribed steps. As described above, the gate space W and the gate area are determined in the steps of masking and selectively etching of Figure 2b, and the oxidation step of Figure 2c and the size and the position thereof are decided by selfalignment techniques. As a result, a minimum size SIT to be obtained in the step of masking can be formed. Therefore, even by today's photolithographic techniques, 2 #m x 2 Mm n+ drain region and 1 ym x 2 ,um channel sectional area can be realised. The width of the n- region between the p+ gate region and the n+ drain region depends upon the thickness of the insulation film 27.In this case, it is of use for controlling the width of the n- drain region 13 since faster oxidation of the n+ polycrystal layer can be utilized. For example, a width of 0.3 to 0.5 ~m for the n- region 13 can be obtained by a self-alignment technique. The reduction of capacitance can be obtained by increasing the thickness of the three insulation films. It is possible to reduce the area of the p+ gate region 14 by an amount equal to 2 x w x thickness of the insulation film 37.

Figure 3 is a sectional view illustrating another embodiment of a method of fabricating a junction type field effect semiconductor device according to the present invention. Figure 3a is a sectional view in which thick selective oxidation films 7, 107 are formed on the n+ source region 12 (not shown) by the use of silicon nitride films 8, 48.

The selective oxidation operation can be carried out after cutting the n- region 13. This is advantageous to reduce capacitance and carrier strage. Next, the film 48 is removed by a masking step and the p+ gate region 114 is formed by a diffusion technique (Figure 3b). To remove the film 8, an etching operation is effected all over the surface and the polycrystal layer 1, the silicon dioxide insulation film 17 and the silicon nitride film 18 are deposited after the window corresponding to the position of the SIT is defined (Figure 3c).

In this case, the polycrystal layer 1 may be socalled doped polycrystal to which AS or Sb is added or may be low impurity density polycrystal (preferably, p type or n type, and preferably having lower impurity density than that of the n region 13, although under some circumstances a relatively high impurity density can be tolerated).

In the latter case impurity is added to the insulation film 1 7 using a doped oxide including As or Sb, or a spin coat diffusion source. The polycrystal layer can be arranged as a multi-layer with a low impurity density layer and a high impurity density layer.

In the next step, an insulation film consisting of the insulation film 17 and the film 18 and the polycrystal layer 1 for wiring material which is formed on the portion to be the n+ drain region 11 in the following step are not removed, and for the purpose of forming the p+ gate region 14 in a later step, the n- region 13 between the oxidation film 107 and the insulation film 7 is exposed (Figure 3d). Oxidation films 27, 37 are formed on the side faces of the polycrystal layer 1 and the exposed face of the n region 13 by a selective oxidation technique, respectively (Figure 3e). Then, a window is defined by a directional etching technique to form the p+ gate region 14 (Figure 3f), and electrodes are formed to obtain a complete semiconductor device (Figure 3g).The gate electrode 4 is usually made of metal, such as, for example, aluminium, platunum, aluminiumsilicon, however the wiring may be p type silicon polycrystal as a diffusion source in the p+ gate region 14.

In the embodiment illustrated in Figure 3, it will be seen that the oxidation film 27 with sufficient thickness can be obtained by forming the film 18 on the polycrystal layer 1, and the insulation layer 17 may be a multi-layer. This is useful for the reduction of gate-drain capacitance in the inverted arrangement to that of Figure 3 in which the insulation layer 17 is formed on a relatively thick film 18 by a CVD technique.

As described above, according to the fabrication method of the present invention, SIT which is formed by most fine pattern technique allowable in the step of masking, can be realized with lower capacitance by self-alignment technique due to the employment of polycrystal drain.

Figure 4a is a plan view of an inverted type SIT according to the present invention, oxidation films being omitted for clarity. Figure 4b and Figure 4c are sectional views taken on the line A-A' and B-B' in Figure 4a respectively.

Then region 13 on the n+ source region 12 and the drain region 11 and the p+ region 14 are respectively connected to a drain electrode 1 and a gate electrode 4 through an n+ polycrystal layer 111 and a p+ polycrystal layer 114.

The n+ polycrystal layer 111 is isolated from the p+ polycrystal layer 114 by the oxidation film 27 on an upper face of the polycrystal layer 114 and the oxidation film 107 on the side face thereof, and is also isolated from the n- region 13 by the insulation film 7. The polycrystal layer 114 is also formed on the insulation film 7. With this arrangement, since a contact portion can be formed on the insulation film 7 by the use of the polycrystal layer 114, it is possible to reduce the gate junction area only by reduction of the area of the window for the formation of the p+ gate region 14. If the oxidation films 27, 107 on the upper and side faces of the polycrystal layer 114 are sufficiently thick, the gate-drain capacitance and the gate space W can be reduced, respectively.

The n+ drain region 11 can be formed so as to be relatively shallow by using the polycrystal layer 111, and the reduction of endurance characteristics for voltage due to an aluminium spike phenomenon can be avoided.

Figures 5a to 5g are sectional views illustrating a further method according to the present invention for fabricating an 12L type SITL.

As illustrated in Figure Sa, a silicon dioxide buffer film is deposited as necessary on the surface of the n- region 1 3 formed on a n+ source region (not shown) by an epitaxial growth technique, and a silicon nitride (Si3N4) film and a silicon dioxide (SiO2) film are deposited thereon by a CVD technique or thermal formation technique.

Then, island-like regions composed of silicon nitride films 1 8, 58, insulation films 1 7, 57 and resists 1 9, 59, respectively, are formed on the portion corresponding to a SIT portion to be formed and on the portion corresponding to an injector portion to be formed by a plasma etching technique or an ion etching technique. In this case, the resists can be used as mask members formed by a conventional photo-lithographic technique.

Figure Sb illustrates the preparatory step for forming the window for the gate in which the insulation films 1 7, 57 are etched from side directions by a normal wet type etching technique or isotropic etching technique, such as a plasma etching technique, using the resists 1 9, 59 as masks.

At this time, if the width of the resist 59 corresponding to the injector portion to be formed is selected to be less than half of a value cut by the side etching for silicon dioxide, the resist 59 is lifted off in this step and it is possible to monitor the amount cut by the side etching. Such a monitor portion may be provided on another portion of the n- region 13. Figure 5c illustrates the formation of the selective oxidation film 7 by using silicon nitride films 18. 58 as masks after the resists are removed. A concave portion may be defined in the n- region 13 as necessary before the formation of the selective oxidation film 7.In Figure 5d, after a first window is defined in the periphery of the silicon nitride film 18 by the use of the insulation film 1 7 as a mask and a window for an injector is defined by removing the silicon mitride film 58 in the step shown in Figure 5c, a polycrystal layer and a silicon nitride film are deposited all over the surface. Then, polycrystal layers 114,115 and silicon nitride films 28, 1 58 are left in the form of an island so as to cover the first window for the SIT gate and the window for the injector. At this time, the insulation film 17 is exposed in the polycrystal layer 114 for forming the second window for the formation of the n+ drain region. It may be also possible that p type impurity is added to the polycrystal layers 114, 115 in advance and then it is deposited. Also, a layer may be formed on the surface of the polycrystal layers 114,115 by a conventional ion injection technique or a diffusion technique before the deposition of the silicon nitride films 28, 1 58.

A polycrystal double layer composed of a low impurity density layer and high impurity density layer may also be employed. Of course, not only may a silicon nitride film be deposited on the polycrystal layers 114, 11 5, but also, for example, a silicon dioxide film.

Next, as shown in Figure Se, thick silicon dioxide insulation films 107, 1 57 are formed on the side faces of the polycrystal layers 114,115 respectively for suppressing the diffusion of p type impurity by using a high pressure oxidation technique or a thermal oxidation technique at low temperature. The second window for the drain becomes smaller and the width of high resistance layer between the gate and the drain becomes wider as the thickness of the insulation films 107, 157 increases. This serves to reduce capacitance.

Therefore, it is preferable to use an anodic oxidation technique in Figure 56. After this, the p+ gate region 14 and the injection region 15 are formed so as to be a predetermined depth as shown in Figure 5f. At this time, the silicon nitride films 28, 1 58 are removed, the upper faces of the polycrystal layers 114,115 are subjected to oxidation and the silicon dioxide oxidation films 27, 1 57' are formed. A P type selective diffusion technique may be carried out through the polycrystal layers 114,115 not only in the step of Figure 5d but also in this step.After this, as shown in Figure 5g, a second window for the formation of the drain is defined by removing a portion of the silicon nitride film 18 to form the n+ drain region 11 and then metal wiring is carried out through a contact window to obtain a completed semiconductor device. Since the n+ drain region 11 is formed through the polycrystal layer 111 as shown in Figure 5g, a relatively shallow n+ drain region may be formed. This serves to reduce capacitance.

It will be appreciated that a photo-lithographic step for forming a specially slender mask is not necessary since the first window for the formation of the gate is defined by the side etching. Not only side etching of the insulation film 1 7 is possible, but also side etching of the silicon nitride film 1 8.

The allowable alignment error of the second window for the drain is approximately +0.5 to +0.3 fltm and the allowable width error thereof is approximately 1 to 2 Mm. It is possible to reduce the gate-drain capacitance by subsequently oxidising the upper face and the side face of the polycrystal layer 114, Moreover, since the gate contact is made by the polycrystal layer 114, the junction area of the n+ region 13 can be reduced greatly and the gate-source capacitance can also be reduced. As a result, a remarkable improvement in performance can be achieved.

Figures 6a to 6e are sectional view of yet another method according to the present invention for fabricating an inverted type SIT. The steps of Figures 6a and 6b substantially correspond to the steps of Figures 5a and Sb. In Figure 6c, the silicon nitride film 28 and the silicon dioxide film 27 are deposited on the polycrystal layer 114 including p type impurity. However, at this time, the insulation film 17 is removed after the formation of the first window for the gate. In Figure 6d, the p+ gate region 14 is formed as the side face of the polycrystal layer 11 4 and is covered with the silicon dioxide film 107.After this, the second window for the drain is defined in the silicon nitride film 18 by the use of the silicon dioxide films 27, 107 as masks, and the n+ drain region 11 is formed by the use of the n+ polycrystal layer 111 (Figure 6e). In this case, to reduce capacitance, it is preferable to increase sufficiently the thickness of the silicon nitride film 28 and the silicon dioxide film 27, and, for example, respective thicknesses of 0.2 #m or less can be achieved.

Figures 7a to 7h are sectional views illustrating yet further methods according to the present invention for fabricating an l2L type SITL. The steps illustrated in Figures 7a to 7dsubstantially correspond to the steps illustrated in Figures 5a to 5d. However, in Figure 7d, the polycrystal layer 114 is n type of p type and of low impurity density preferably lower than the impurity density of the n n region 13. In the steps of Figure 7e, the side faces of the polycrystal layers 114,115 are covered with the silicon dioxide films 107, 1 57, and the insulation film 17 on the silicon nitride film 18 is removed to form the second window.

The order of these steps may be changed if desired.

Then, as shown in Figure 7f, one portion of the silicon nitride film 18 is removed and the second window is defined. After this, the polycrystal layer 111 is deposited, and is subjected to a selective etching technique and an oxidation technique.

Although n type impurity is added to the polycrystal layer 111 in advance, the layer 111 may be composed of an n- layer and an n+ layer.

In either case, n type impurity with small diffusion coefficient, such as As or Sb is required for heating process in a later step. In Figure 7g, the silicon nitride films 28, 158 are removed by etching all surfaces, and the window for gate formation selective diffusion is defined. Then, the p+ gate region 14 and the injector region 15 are formed in the n region 13 by the diffusion of p type impurity, and the resistance value of the polycrystal layers 111,115 is reduced. In this case, the selective diffusion is preferably carried out under the condition where the thickness of the oxidation film does not become too thick, such as in an atmosphere of dry oxygen, inert gas, such as nitrogen, or a mixture thereof. This makes it possible easily to connect the gate to its contact member.

After this, wiring metals, such as aluminium, platinum or the like for the gate electrode 4 and an injector electrode 5 are arranged to obtain the completed semiconductor device. In this embodiment the gate contact is directly formed on the slender p+ gate region 14 without the formation of special spaces and, moreover, the gate electrode 4 is wired on the polycrystal layer 111 formed on the n+ drain region 11 through the insulation film 117. In particular, the p+ gate region 14 under the polycrystal layer 111 for drain wiring can enclose the drain region 11, but somewhat shallowly, by fast diffusion in the polycrystal layer 114. Even if the n+ drain region 11 cannot be completely enclosed thereby, the width of the unenclosed portion, which is between the p+ gate region 14, is narrower than the gate space. As a result, no problems occur.

The described embodiments of the present invention have the following important features: (1) Since the size of the first window for the gate is determined by the amount of the silicon nitride film cut by side etching, a small size pattern can be realised.

(2) Any masking step using a fine mask member is not required since a relatively thick first polycrystal layer can be left on the first window.

The gate contact portion can be formed in the first polycrystal layer, and the window for the formation of the drain can be reduced in size by forming a thick oxidation film on the side face of the first polycrystal layer by at least the value corresponding to the thickness of the oxidation film, as compared with the case of using only a mask. Since this serves to omit or reduce the high impurity density region junction between gate and drain, the capacitance can be reduced.

(3) The gate space can be reduced to such a degree to achieve minimum allowable length or positioning accuracy in the masking step. As a result, a lower power consumption and high gm semiconductor device can be realised.

(4) Since the diffusion is carried out through the polycrystal layer, aluminium spike or the like never occurs regardless of the shallow junction.

The present invention is applicable not only to inverted type SIT, but also to vertical type, n channel orp channel SIT, FET, other field effect semiconductor devices having the same channel structure (for example, SIT thyristor or memory) or integrated circuitry including these elements (for example, l2L type SITL having a lateral bipolar transistor as a load, other SITL, analog SIT-IC or FET-IC). Moreover methods according to the present invention are also applicable to an inverted type or vertical type bipolar transistors.

For fabricating bipolar transistors, a p type polycrystal layer may be employed instead of an n+ polycrystal layer 1 in Figure 3c, and n type impurity is added to the insulation film 17. The present invention is also applicable to methods of fabricating bipolar transistors after the formation of the base region.

The present invention makes it possible to provide a high performance field effect semiconductor device which can be fabricated by simple steps and to provide its fabricating method.

The semiconductor device will serve to obtain high IC and low power consumption, and the application of the present invention is wide, such as IC for timepieces, micro processors, memories, AID converters or D/A converters.

Claims (16)

1. A junction type field effect semiconductor device comprising a main electrode single crystal region of one conductivity type formed on a surface of a low impurity density single crystal region of the said one conductivity type, a gate region of the opposite conductivity type enclosing said main electrode single crystal region on said surface, a polycrystal region formed either on said main electrode single crystal region or on said gate region, and a contact window in a portion of the gate region, the contact window having at least a part which is defined by a side oxidation film formed on said polycrystal region, said contact window being used to receive conducting material connected to said gate region.

2. A junction type field effect semiconductor device as claimed in claim 1 in wich the polycrystal region is provided on said main electrode single crystal region and acts as a wiring member therefor, a conductive wiring material connected to said gate region being provided on said polycrystal region but isolated therefrom by the side oxidation film and an upper oxide film on said polycrystal region.

3. A junction type field effect semiconductor device as claimed in claim 1 in which the polycrystal region is provided on said gate region, a window being defined by an inner side oxidation film on said polycrystal region, said main electrode single crystal region being formed on a surface of said low impurity density single crystal region.

4. A method of fabricating a junction type field effect semiconductor device comprising the steps of: selectively forming a first gate region of an opposite conductivity type on a major surface of a low impurity density single crystal region of one conductivity type and coating said major surface with a first insulation film; forming a multi-layer film consisting of a second insulation film and a polycrystal layer on said first insulation film and forming a window through the multi-layer film and the first insulation film to expose a region of said low impurity density region; forming a thermal oxidation film on at least the side face of said polycrystal layer bordering said window; forming a second gate region of said opposite conductivity type after said low impurity density region in the window is exposed again; and defining a contact window by re-exposing the said exposed region and forming gate wiring so as to cover one portion of said second insulation film and said contact window.

5. A method as claimed in claim 4 in which said second insulation film is or includes a silicon nitride film.

6. A method as claimed in claim 4 or 5 in which one conductivity type impurity is contained in the surface of said polycrystal layer at the time of deposition, the remainder of the polycrystal layer having a low impurity density.

7. A method of fabricating a junction type field effect semiconductor device comprising the steps of: forming an island-like insulation film consisting of at least two layers one of which is a nitride film and the other of which is an oxide film on a surface of a low impurity density region of one conductivity type and forming a selective oxidation film; depositing at least a first polycrystal layer after a first window is formed between an end portion of said selective oxidation film and an end portion of said island-like insulation film, the size of said first window being defined by the side-etched portion of one layer of said island-like insulation film; exposing a portion of the first polycrystal layer which substantially corresponds to said first window and removing the first polycrystal layer on said island-like insulation film to form a second window; and forming the second window by removing a portion of said island-like insulation film after oxidising the exposed portion of the remaining first polycrystal layer, so that an opposite conductivity type gate region is formed by the use of the first window, a main electrode region of said one conductivity type being formed by the use of the second window, and a channel region being formed in the low impurity density region.

8. A method as claimed in claim 7 in which the opposite conductivity type impurity is added to at least one portion of said first polycrystal layer before the oxidation of the exposed portion thereof.

9. A method as claimed in claim 7 or 8 in which the second polycrystal layer of said one conductivity type is deposited in the second window and the second polycrystal layer is used as a portion of wiring for a main electrode.

10. A method as claimed in claim 9 in which at least one nitride film is deposited on said first polycrystal layer, said portion of main electrode wiring formed by said polycrystal layer being formed after the oxidation and the formation of the second window, a portion of the first polycrystal layer being exposed by removing said nitride film on the first polycrystal layer after the oxidation, and subsequently providing wiring for the gate electrode.

11. A method as claimed in claim 10 in which the impurity density of the first polycrystal layer is relatively low, an opposite conductivity type gate region being formed through the first polycrystal layer and the first window after the nitride film on the first polycrystal layer has been removed, a gate electrode and its wiring then being formed.

12. A junction type field effect semiconductor device substantially as herein described with reference to and as shown in the acompanying drawings.

13. A method of fabricating a junction type field effect semiconductor device substantially as herein described with reference to the accompanying drawings.

14. A junction type field effect semiconductor device having a main electrode single crystal region of one conductivity type formed on the surface of a low impurity density single crystal region of the one conductivity type and a gate single crystal region of an opposite conductivity type enclosing said main electrode single crystal region on said surface, characterised in that a polycrystal region is formed either on said main -electrode single crystal region or on said gate single crystal region, and a contact window to be formed in another region of said single crystal regions has a portion which is defined by at least side oxidation films formed on said crystal region, said contact window being used to receive conducting material connected to a desired region.

1 5. A method for fabricating junction type field effect semiconductor device, comprising steps of: selectively forming a first gate region of an opposite conductivity type on a major surface of a low impurity density single crystal region of one conductivity type and coating said major surface with a first insulation film; defining a window in said first insulation film, forming a multi-layer film consisting of a second insulation film and a polycrystal layer extended on said first insulation film formed on said first gate region from one portion of said window, and exposing one portion of said low impurity density region between a window in said first insulation film and said polycrystal layer; forming a thermal oxidation film on at least the side face of said polycrystal layer; forming a second gate region of the opposite conductivity type so as to superpose one portion of said first gate region after the exposed portion of said low impurity density region is exposed again; and defining a contact window by exposing one portion of said exposed portion again and forming a gate wiring so as to cover one portion of said second insulation film and said contact window.

16. A method of fabricating junction field effect semiconductor device, comprising the steps of: forming an island-like insulation film consisting of at least two layers which are a nitridation film and an oxidation film on a surface of one conductivity type low impurity density region and forming a selective oxidation film; depositing at least a first polycrystal layer after a first window is formed between the end portion of said selective oxidation film and the end portion of said islandlike insulation film, the size of said first window being defined by the side-etched portion of one insulation film of said two layer insulation films; leaving the portion of the polycrystal layer which approximately corresponds to said first window and removing the first polycrystal layer on said island-like insulation film to form a second window; and forming the second window by removing a portion of said island-like insulation films after oxidising the exposed portion of a left first polycrystal layer, whereby an opposite conductivity type gate region is formed by the use of the first window, one of main electrode regions of the one conductivity type is formed by the use of the second window and a channel region is formed in the low impurity density region.