GB2063626A

GB2063626A - Improvements in or relating to circuit arrangements for identifying alignment words for use in digital signal transmission systems

Info

Publication number: GB2063626A
Application number: GB8030221A
Authority: GB
Original assignee: Societa Italiana Telecomunicazioni Siemens SpA
Current assignee: Italtel SpA
Priority date: 1979-10-11
Filing date: 1980-09-18
Publication date: 1981-06-03
Also published as: IT1207258B; AU6315280A; BR8005874A; SE8007125L; ES494704A0; IT7926405A0; JPS5661849A; FR2467516A1; DE3038360A1; AR228857A1; ES8105124A1

Abstract

A circuit arrangement is provided for identifying an alignment word of m bits from a demultiplexer DM of a digital communication system having n channels. The circuit arrangement Fig. 2 (not shown) includes a memory comprising n shift registers of length (n + m)/n for receiving n bit flows from the demultiplexer DM. A decoder DC energizes one of its n outputs according to the way in which the bits of the alignment word have been distributed in the shift registers of the memory. A coder CM provides a code q corresponding to the energized output, where n</=2<q>, and supplies this code as a control signal to an exchange matrix MS which reorganizes the n bit flows, if necessary, into n bit flows of the n channels. Thus, the demultiplexer output is aligned by the circuit arrangement, which is only required to operate at 1/n times the speed of the demultiplexer. <IMAGE>

Description

SPECIFICATION Improvements in or relating to circuit arrangements for identifying alignment words for use in digital signal transmission systems The present invention refers to a circuit arrangement for identifying an alignment word.

Such a circuit arrangement may be used in the receiving section (demultiplexer) of a digital signal transmission system which, in its transmitting section, includes a multiplexing unit receiving on n inputs an equal number of digital signal flows from an equal number of data sources, which will be termed in the following "tributary" groups. The output of the transmitting section is a data flow multiplexed "bit by bit", containing the bits of the "tributary" groups, a predetermined number of bits forming the alignment word, and other bits such as justification-control justification and service bits. The receiving station includes a demultiplexing unit to which is associated a unit capable of identifying the alignment word and a synchronization unit. The aim of said units is to forward in a correct manner the bits received to n the "tributary" groups to which they are allocated.

Circuit arrangements capable of identifying the alignment word and of synchronizing the demultiplexer are known, such arrangements usually including a register having a number of cells equal to the number of bits expressing the alignment word. The register is connected to a decoder unit capable of identifying the alignment word and of setting to zero the demultiplexer, which generally includes a register having a number of cells equap to the number of bits expressing the alignment word, to which is connected a decoder unit capable of identifying the word and of setting to zero a chain of counters timing the demultiplexing operations. A circuit arrangement of this type has the disadvantage that the circuits provided therein have to operate at the bit.

frequency of the transmission system to which they belong.

For instance, in the case where the transmission system in question is a 1 40 M bit/s system, the circuit arrangement must be provided with components capable of operating at such a speed. In the case of transmission systems of higher hierarchy (for example 560 M bit/s), there arise technological problems of increasing difficulty relating to the particularly high speed.

Furthermore, components capable of operating at high speed generally dissipate a power substantially higher than components operating at low speed. The use of fast components, with respect to the use of slower components, therefore requires power supplies capable of supplying the increased power required and causes problems regarding the disposal of heat developed in the equipment.

According to the invention, there is provided a circuit arrangement for identifying an alignment word for use with a digital signal multiplexer of the type having a transmitting section including a multiplexing unit for receiving on n inputs an equal number of d digital signal flows and a receiving section including a demultiplexing unit comprising a first register having n memory cells for receiving in series the flow of multiplexed data, a unit for extracting timing pulses from the flow of multiplexed data, a counter having a counting capacity n connected to receive the timing pulses from the output of the extracting unit, and a second register which is arranged, in response to a counter output pulse, to receive in parallel, according to n possible configurations, the bits stored in the first register, the circuit arrangement comprising memory means comprising n shift registers, each of which has (n+ m)/n memory cells, where m is the number of bits of the alignment word, and each of which is arranged to be connected to a respective cell of the second register, decoder means arranged to energize one of n outputs in response to the configuration according to which the bits indicating the alignment word in the memory means have been distributed, coding and storing means arranged to translate into q bits, where q is connected to n by relation n ' 2q, the code corresponding to the output of the decoder means, and an exchange matrix arranged to supply on n outputs the bits stored in the memory means identified by the binary codes corresponding to the output of the coding and storing means.

It is thus possible to provide a circuit arrangement capable of identifying the alignment word and of carrying out synchronization at the bit speed of the "tributary" groups. The circuit arrangement can be used with a demultiplexer having a counter of counting capacity n capable of distributing to n registers the flow of bits reaching the demultiplexer. The counter, unlike in known systems, is never set to zero whereby it begins counting starting from a random number and consequently distributes the bits to the n registers according to n possible configurations. The circuit arrangement identifies the configuration according to which the bits expressing the alignment word have been distributed and this identification enables correct forwarding of the bits stored in the registers to the n tributary groups to which they are allocated.

The invention will be further described, by way of example, with reference to the accompanying drawings, wherein: Figure 1 is a block diagram of a circuit arrangement constituting a preferred embodiment of the invention; Figure 2 shows in detail memory means MM od Fig. 1; Figure 3 shows in detail decoder means DC of Fig. 1; Figure 4 shows in detail coding and storing means CM of Fig. 1; and Figure 5 shows in detail exchange matrix MS of Fig. 1.

In Fig. 1 DM indicates a demultiplexer comprising a unit UE for extracting timing pulses CK from a multiplexed flow of bits supplied to a register RS having n memory cells. As, in most transmission systems, n is equal to four, the embodiment described herein refers to a unit capable of demultiplexing a flow of data relating to four tributary groups.

The pulses CK determine loading of the bits in the register RS and are also supplied to a counter CN, which has a counting capacity of four but which is not provided with a zerosetting input, whereby, upon switching on the apparatus, counting begins starting from a random number.

The output of the counter CN provides a sequence of pulses of frequency CK/4 which are used to control transfer of the bits contained in the register RS to a register RP. The pulses CK/4 therefore have the function of dividing the flow of data received into blocks of four bits but, because the counter CN is not pre-set to zero, division into blocks is carried out starting from a random position and consequently the transfer is carried out according to n possible configurations.

The output of the register RP is connected to a circuit arrangement constituting a preferred embodiment of the invention and, comprising memory means MM consisting of four shift registers. The memory means MM are connected to decoder means DC, which scan the configurations that the alignment word may assume after it has been transferred to the registers of the memory means MM and energize the output to which the configuration assumed by said bits refers.

The circuit arrangement furthermore comprises an exchange matrix MS which is addressed by the codes corresponding to the output of means CM in such a way as to determine the supply at a first output of the bits allocated to the first tributary group, at a second output of the bits allocated to the second tributary group, and so forth.

Fig. 2 shows in detail the memory means MM which comprise shift registers R1, R2, R3 and R4, which are each capable of storing four bits and which, when a pulse of the sequence CK/4 is present, store the bit present in the cell of the register RP to which they are connected. Depending on the phase by means of which the bits reach the demultiplexer and depending on the number from which the counter CN starts counting, the bits are distributed in the registers R1-R4 according to four possible configurations.

One of the configurations that the alignment word, which in 140 M bit/s. Sys tems has the configuration 11111010000, may assume is illustrated in Fig. 2. Supposing the bits reach the demultiplexer with the same phase, if the counter CN starts counting from the next number with respect to the number from which counting had started in the case shown in Fig. 2, the first bit of the word is located in the last cell of the register R2 while the last bit is located in the first cell of the register R, and so forth.

Fig. 3 shows the decoderunit DC which comprises units D1, D2, D3 and D4. The unit D, is capable of exciting its output d, when the alignment word is distributed in registers R,-R4 as shown in Fig. 2. The unit D2 is capable instead of energizing its output d2 when the first bit of the alignment word is located in the last cell of the register R2, while the last bit is located in the first cell of the register R, and so forth.

Fig. 3 shows the decoder unit DC which comprises units D1, D2, D3 and D4. The unit outputs d,-d4 of the decoder DC is therefore energized. The outputs d,-d4 are connected to the coding and storing means CM which are shown in detail in Fig. 4 and include a coder CD capable of translating the excitation of one of the four outputs d,-d4 of the decoder DC into a binary code expressed by means of two bits supplied to the data inputs of first and second D type bistable circuits FF, and FF2.

The bistale circuits FF, and FF2 receive on their other inputs a signal kfrom the output of an AND gate P, to a first input of which is connected an OR gate 0 whose inputs receive the signals d,-D4. A second input of the gate P receives a signal p active when the signals d,-d4 coincide with the end of time intervals identified by measuring a "frame" time start ing from the preceding activation.

When signal k is active, the code at the outputs f and f2 of the bistable circuits FF, and FF2 corresponds the code at the outputs of the coder CD. These codes are supplied to the control inputs of multiplexers MT1, MT2, MT3 and MT4 forming part of the exchange matrix MS shown in detail in Fig. 5.

The inputs 1 of the multiplexers MT,-MT4 are connected to the cells of the registers R,-R4 where four given bits are transferred when counter CN begins counting starting from such a number that the a alignment word is distributed as indicated in Fig. 2. The inputs 2 of the multiplexers MT,-MT4 are connected to the cells of the registers R,-R4 where four given bits are transferred when the counter CN begins counting starting from the next number with respect to the number from which the previous case had started, and so forth.

In the case where the transmission system in question is a 140 M bit/s system, the components of the demultiplexing unit must be capable of operating at 140 M bit/s, while the components of the circuit arrangement need only be capable of operating at 34 M bit/s.

Claims

1. A circuit arrangement for identifying an alignment word for use with a digital signal multiplexer of the type having a transmitting section including a multiplexing unit for receiving on n inputs an equal number of digital signal flows and a receiving section including a demultiplexing unit comprising a first register having n memory cells for receiving in series the flow of multiplexed data, a unit for extracting ti timing pulses from the flow of multiplexed data, a counter having a counting capacity n connected to receive the timing pulses from the output of the extracting unit, and a second register which is arranged, in response to a counter output pulse, to receive in parallel, according to n possible configurations, the bits stored in the first register, the circuit arrangement comprising memory means comprising n shift registers, each of which has (n+ m)/n memory cells, where m is the number of bits of the alignment word, and each of which is arranged to be connected to a respective cell of the second register, decoder means arranged to energize one of n outputs in response to the configuration according to which the bits indicating the alignment word in the memory means have been distributed, coding and storing means arranged to translate into q bits, where q is connected to n by relation n'2q, the code corresponding to the output of the decoder means, and an exchange matrix arranged to supply on n outputs the bits stored in the memory m means identified by the binary codes corresponding to the output of the coding and storing means.

2. A circuit arrangement as claimed in claim 1, in which the coding and storing means comprise a coder having q outputs connected to the data inputs of q D type bistable circuits, respectively, whose clock inputs are connected to the output of an AND gate, a first input of which is connected to an OR gate, whose inpurts are connected to respective outputs of the decoder means, the AND gate having a second input connected to receive a signal activated after each time interval identified by measuring a "frame" time starting from the previous activation.

3. A circuit arrangement as claimed in claim 1 or 2, in which the exchange matrix includes n multiplexers each of which has n data inputs and q control inputs connected to reveive the codes from the output of the coding and storing means, the n data inputs of each multiplexer being connected to the respective cells of the shift registers of the memory means where a group of n bits is transferred, for transmission by the exchange matrix at the same time, when division of the bits received has taken place according to the n configuration.

4. A circuit arrangement substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

5. A digital signal multiplexer having a receiving section including a demultiplexing unit connected to a circuit arrangement as claimed in any one of the preceding claims.