GB2062417A

GB2062417A - Improvements in or relating to circuit arrangements for synchronizing demultiplexers

Info

Publication number: GB2062417A
Application number: GB8033550A
Authority: GB
Original assignee: Italtel SpA
Current assignee: Italtel SpA
Priority date: 1979-10-29
Filing date: 1980-10-17
Publication date: 1981-05-20
Also published as: AR225323A1; FR2469060A1; DE3040787A1; IT7926859A0; BR8005706A; IT1207280B

Abstract

There is provided a circuit arrangement for synchronizing a demultiplexer when used with a decoder unit which produces an output in response to the observation of a binary configuration coinciding with an alignment word. The circuit arrangement comprises a logic network RL which supplies a pulse in response to production of an output by the decoder unit simultaneously with the end of time intervals of length corresponding to a "frame" time starting from the emission of each decoder unit output. A register RU is connected to the output of a ROM (read-only-memory), containing a number of codes characteristic of an equal number of steps of the operating program. The address inputs of the ROM are connected to a predetermined number of cells of the register and to the output of the logic network. <IMAGE>

Description

SPECIFICATION Improvements in or relating to circuit arrangements for synchronizing demultiplexers The present invention refers to a circuit arrangement capable of synchronizing a demultiplexer, for instance in the receiving section (demultiplexer) of a digital signals transmission system, which, in its transmitting section, includes a multiplexer unit receiving on n inputs an equal number of digital signal flows originating from an equal number of data sources which will be termed in the following "tributary groups".

The output of the transmitting station comprises a data flow organized in frames of duration t, containing the bits of the tributary groups, a predetermined number of bits forming an alignment word and other bits such as justification-control, justification and service.

The receiving station includes a demultiplexing unit to which is associated a decoder unit capable of recognizing the alignment word and a synchronization unit. These units forward in a correct manner the bits received to n tributory groups to which they are allocated.

An embodiment of a decoder unit capable of recognizing an alignment word is described in British Patent Application No.

corresponding to Italian Patent Application No.

26405 A/79.

It is desirable to perform synchronization of the demultiplexing unit in response to the identification of the alignment word, but to prevent synchronization from being performed every time the decoder means reveal the presence of a binary configuration simulating the alignment word.

There exist known circuit arrangements capable of carrying out such synchronizing operations based on a predetermined operating program according to which the demultiplexer is considered synchronized, or not synchronized, after the decoder unit has signalled the identification, or failure of identification, of the alignment word by a predetermined number of frames. Such circuit arrangements generally include a first counter which increases its contents, or a second counter which decreases its contents, in response to excitation, or in response to failure of excitation, of the output of the decoder unit. There is also provided means capable of enabling or stopping the counting of the counters, for instance,when the alignment word is recognized for two consecutive frames, but not the subsequent frame.

A circuit arrangement of the type described is rather complex and does not allow each changes in the operating program.

According to the invention, there is provided a circuit arrangement capable of synchronizing, according to an operating program having a predetermined number of steps, a demultiplexer for receiving signals organized in frames of duration t when used with a decoder unit capable of exciting its output in response to the observation of a binary configuration coinciding with a frame alignment word, the circuit arrangement comprising a logic network arranged to supply a signal in response to the excitation of the output of the decoder unit and arranged to indicate if the output of the decoder unit is excited in coincidence with the end of a time interval of length t starting from each preceding excitation of the decoder unit output, the circuit arrangement further comprising a register connected to the output of a read-only-memory which contains codes characteristic of and equal in number to the predetermined number of steps of the operating program, the address input of the read-onlymemory being connected to a predetermined number of cells of the register and to the output of the logic network.

It is thus possible to provide a circuit arrangement for the synchronization of a demultiplexing unit which is simple and not costly and which enables the operating program to be easily modified.

The invention will be further described, by way of example only, with reference to the accompanying drawings, wherein: Figure 1 is a flow diagram, internationally recommended by "CCITT" and "CEPT", according to which a preferred circuit arrangement operates: Figure 2 shows a circuit arrangement constituting a preferred embodiment of the invention; and Figure 3 illustrates waveforms relating to the circuit arrangement of figure 2.

In Figure 1, 0 represents a state indicating the out-of-synchronism condition f a preferred circuit arrangement upon switching on of an apparatus or due to line interruptions, while 3 represents a state indicating the condition of the circuit arrangement when synchronism has been attained.

The transition from the state sms to a state 1 is carried out in response to the identification of an alignment word located in a frame T, of a multiplexed signal. This identification entails the emission of a pulse indicated at c in Fig. 3.

When the next frame T2 reaches the demultiplexer, it is determined whether, after a time interval t measured starting from the emission of the pulse c, the alignment word is present. If the determination gives a positive result, emission of pulse f is recorded and consequently transitition to state 2 is achieved. If instead the determination gives a negative result, the emission of pulse fdetermines return back to state # because in frame T a binary configuration simulating the alignment word had been found.

Transition from state 2 to state 3, or the return back to the state , is carried out in response to the emission of the pulse f, or in response to the emission of the pulse f. The circuit arrangement remains in the state 3 for further emission of pulses f, whereas, when a pulse fis emitted, transition to state 4 is recorded.

From state 4 the emission of a pulse fentails return back to state 3 whereas emission of a pulse 7entails transition to state 5. Similarly, transition from state 5 to state 6, or return back to state 3 occur for corresponding conditions.

From the state 6 emission of a pulse fentails return back to the state 3 whereas emission of a pulse fentails return to the state sX and consequently the emission of an alarm signal z as well as starting of a further synchronism search.

The circuit arrangement shown in detail in Fig.

2 includes a logic network RL which comprises a first AND gate P1 an input of which receives a signal c supplied by decoder mean when the presence of a binary configuration coinciding with the alignment word is detected. The other input of the gate P, receives a signal ffrom the output of a bistable circuit FF of D type. The output of the gate P, is connected to the input 1 of a first multiplexer MTr, the output of which is connected to the data input D of the bistable circuit FF, whose other input receives pulses from the output of a second multiplexer MT2.

The input 1 of the second multiplexer MT2 is connected to a second AND gate P2 which receives at a first input the output of the gate P1 and at a second input a sequence of pulses d obtained through means (not illustrated) capable of extracting timing pulses from the flow of bits received, and capable of dividing by n the sequence as well as carrying out the reverse.

The input 2 of the first multiplexer MT, is connected to an AND gate P3 which receives at a first input the signal c and at a second input a sequence of pulses g from the output of enabling means AB.

The enabling means AB comprise a counter CN supplied by a sequence of timing pulses CK extracted from the flow of multiplexed bits, the counter having a counting capacity equal to the number N of bits provided in one frame of the multiplexed signal and being reset to zero by a signal Kfrom the output of the first multiplexer MT,. The enabling means AB also comprise a decoder DC capable of supplying the pulse g when CN has counted N pulses.

The input 2 of the second multiplexer MT2 is connected to a fourth AND gate P4 which receives at a first input the signal g and at a second input the sequence of pulses d.

The multiplexers MT, and MT2 are controlled by a signal b which is active when the operating program is in a state other than the state 0.

The circuit arrangement further comprises a ROM (read-only-memory) and a register RU which, coiciding with the excitation of pulse h, stores the bits corresponding to the output of the ROM. The first four outputs r1, r2 r3 and r4 of the register RU are connected to the inputs of the ROM, and the output b is active when the bits r1-r4 indicate a state other than state s%s, whereas excitation of output z indicates an alarm condition.

The operation of the circuit arrangement of Fig.

2 will now be described with the aid of the waveforms shown in Fig. 3, wherein diagram a represents a multiplexed signal organized as frames of duration t. Diagram b illustrate the signal which is active when the operating program is in a state other than state QI whereby, upon switching on of the apparatus, it has a logic level such as to enable the multiplexes MT, and MT2 to send to their outputs the signals present at their inputs 1.

When the decoder unit reveals the presence, in the flow of data received, of a binary configurating coinciding with the alignment word, it supplies an output pulse (see diagram c) to the input D of the bistable circuit FF which receives at its other input the pulse shown in diagram e. When the pulses shown in diagram c are present, the signal K is activated which sets to zero the counter CN.

Diagram d shows the timing pulses supplied to the inputs of the gates P2 and P4.

The output of the bistable circuit FF therefore coincides with the signal shown in diagram fand consequently the signal present on the inverted output disables the gate P, so as not to take into consideration further identifications of the alignment word which might be present in the same frame.

Excitation of the output falters the address supplied to the ROM and consequently the bits r, to r4 and address a memory line where a binary configuration characteristic of state 1 is located as well as a bit b of logic level such as to cause the emission, by the multiplexers MT, and MT2, of the bits present at their inputs 2.

If the further excitation of signal c coincides with the excitation of signal g, which becomes active after a frame time t starting from the emission of the signal K, the output of the gate P3 corresponds to a pulse supplied to the input D of the bistable circuit FF, which receives at its clock input a pulse, coinciding with the pulses e, corresponding to the output of the gate P4.

The output of the bistable circuit FF therefore corresponds to a pulse coinciding with those shown in diagram fand consequently the binary configuration characteristic of state 1 indicated by means of bits r1, to r4 andfaddressesanew memory line where code characteristic of state 2 is located. However, if upon excitation of the clock input of the bistable circuit FF the output of the multiplexer MT, is de-energized, the bits r1, to r4 together with the bit fnot active, would have addressed a line where a code characteristic of the zero state 6 is located.

From state 2, if the furter excitation of the signal c coincides once again with the excitation of the signal g, excitation of the output fof the bistable circuit FF is recorded, which determines addressing of the binary configuration characteristic of state 3 indicating a synchronism condition. If the aforesaid "coincidence" does not occur, output fof FF is de-energized and consequently in this case also a binary configuration characteristic of the zero-state 5 is addressed.

By noting the logic level which the signal fhas coinciding with the pulses e, the remaining portion of the operating program is performed.

In particular, when the output of the register RU coincides with a code characteristic of state 6, the non-excitation of the output fof the bistable circuit FF causes the code characteristic of the zero-state to be addressed. In these conditions, the signal b is de-energized once again and consequently the multiplexers MT1, and MT2 supply to their outputs the codes present at their inputs 1 so as to carry out once again the search for the alignment word on the whole row of bits received. Such operating program may be easily modified by altering the codes written in the ROM (read-only-memory).

The circuit arrangement may be provided by means of components capable of operating at the speed of the tributary groups in accordance with the disclosure of British Patent Application No.

referred to hereinbefore.

Claims

1. A circuit arrangement capable of synchronizing, according to an operating program having a predetermined number of steps, a demultiplexer for receiving signals organized in frames of duration t when used with a decoder unit capable of exciting its output in response to the observation of a binary configuration coinciding with a frame alignment word, the circuit arrangement comprising a logic network arranged to supply a signal in response to the excitation of the output of the decoder unit and arranged to indicate if the output of the decoder unit is excited in coincidence with the end of a time interval of length t starting from each preceding excitation of the decoder unit output, the circuit arrangement further comprising a register connected ton the output of a read-onlymemory which contains codes characteristic of and equal in number to the predetermined number of steps of the operating program, the address input of the read-only-memory being connected to a predetermined number of cells of the register and to the output of the logic network.

2. A circuit arrangement as claimed in claim 1, in which the logic network comprises a D type bistable circuit whose data input and clock input are connected to the outputs of first and second multiplexers, respectively, each of the multiplexers having a pair of data inputs and a control input which is arranged to receive a signal which is active when the operating program is in a state other than an initial state prior to synchronisation and which then causes the signals present at the second data input of the multiplexer to be supplied to the output thereof, the first data input of the first multiplexer being connected to a first AND gate arranged to receive at its inputs the output of the decoder unit and the inverted output of the bistable circuit, the first input of the second multiplexer being connected to a second AND gate arranged to receive at its inputs the output of the first AND gate and a sequence of timing pulses, the second data input of the first multiplexer connected to a third AND gate arranged to receive at its inputs the output of the decoder unit and the output of enabling means capable of emitting a pulse after a time interval t starting from the excitation of output of the first multiplexer, the second data input of the second multiplexer being connected to a fourth AND gate arranged to receive at its inputs the sequence of timing pulses and the output of the enabling means.

3. A circuit arrangement as claimed in claim 2, in which the enabling means comprises a counter having a counting capacity equal to the number of pulses provided in each frame of the multiplexed signal and arranged to receive at its counting input a sequence of timing pulses a frequency equal to the bit rate of the multiplexed signal and at its zero-setting input the pulse from the output of the first multiplexer, and a decoder arranged to excite its output when the counter is full.

4. A circuit arrangement as claimed in claim 2 or 3, inwhich the signal supplied to the control inputs of the multiplexers and a signal indicating an alarm condition are constituted by an equal number of bits associated to the codes, characteristic of the steps of the operating program, written in the read-only-memory.

5. A circuit arrangement for synchronizing a demultiplexer substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.