GB2023341A - Improvements in or relating to monolithic integrated semiconductor digital circuit modules - Google Patents

Improvements in or relating to monolithic integrated semiconductor digital circuit modules

Info

Publication number
GB2023341A
GB2023341A GB7919512A GB7919512A GB2023341A GB 2023341 A GB2023341 A GB 2023341A GB 7919512 A GB7919512 A GB 7919512A GB 7919512 A GB7919512 A GB 7919512A GB 2023341 A GB2023341 A GB 2023341A
Authority
GB
United Kingdom
Prior art keywords
circuit
monolithic integrated
terminal
relating
integrated semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB7919512A
Other versions
GB2023341B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of GB2023341A publication Critical patent/GB2023341A/en
Application granted granted Critical
Publication of GB2023341B publication Critical patent/GB2023341B/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/22—Means for limiting or controlling the pin/gate ratio
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017545—Coupling arrangements; Impedance matching circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1731—Optimisation thereof
    • H03K19/1732—Optimisation thereof by limitation or reduction of the pin/gate ratio
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Processing Of Color Television Signals (AREA)
  • Networks Using Active Elements (AREA)
  • Logic Circuits (AREA)

Abstract

The development of monolithic integrated semiconductor circuits has now advanced to a point at which the production of the housing which is to accommodate the circuit, together with the provision of the requisite terminal electrodes, decisively influences the price of the overall arrangement. Therefore it is desirable to reduce the number of external terminals required for the semiconductor body, and thus simplify the housing. The invention provides that at least one terminal A is provided on the semiconductor body in which the integrated circuit is formed is permanently connected to act both as a signal input for a first functional circuit stage and as a signal output for a second function circuit stage of the integrated circuit, and provision is made for the selection of the particular mode of operation to be controlled via an external auxiliary circuit connected to the terminal (A). Various embodiments are described. The two functional circuit stages may each possess a shift register (SR2 and SR1) as signal input and as signal output. <IMAGE>
GB7919512A 1978-06-06 1979-06-05 Monolithic integrated semiconductor digital circuit modules Expired GB2023341B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19782824862 DE2824862A1 (en) 1978-06-06 1978-06-06 MONOLITHICALLY INTEGRATED DIGITAL SEMICONDUCTOR CIRCUIT

Publications (2)

Publication Number Publication Date
GB2023341A true GB2023341A (en) 1979-12-28
GB2023341B GB2023341B (en) 1983-01-06

Family

ID=6041189

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7919512A Expired GB2023341B (en) 1978-06-06 1979-06-05 Monolithic integrated semiconductor digital circuit modules

Country Status (4)

Country Link
JP (1) JPS54162438A (en)
DE (1) DE2824862A1 (en)
FR (1) FR2428353A1 (en)
GB (1) GB2023341B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0069509A1 (en) * 1981-06-25 1983-01-12 Fujitsu Limited A circuit for reading out address data applied to a memory in a one-chip microcomputer
EP0157424A2 (en) * 1984-04-04 1985-10-09 Bull HN Information Systems Inc. LSI microprocessor chip with backward pin compatibility
EP0177848A2 (en) * 1984-09-26 1986-04-16 Honeywell Bull Inc. LSI microprocessor chip with backward pin compatibility and forward expandable functionality
US4878168A (en) * 1984-03-30 1989-10-31 International Business Machines Corporation Bidirectional serial test bus device adapted for control processing unit using parallel information transfer bus

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2517630B2 (en) * 1975-04-21 1977-12-01 Siemens AG, 1000 Berlin und 8000 München PARTIAL SETUP OF A DATA PROCESSING SYSTEM
NL7512834A (en) * 1975-11-03 1977-05-05 Philips Nv MEMORY WITH VOLATILE INFORMATION STORAGE AND RANDOM ACCESSIBILITY.
DE2744111A1 (en) * 1977-09-30 1979-04-05 Siemens Ag CIRCUIT ARRANGEMENT FOR THE INPUT OF INTERRUPTION COMMANDS AND OUTPUT OF INTERRUPTION CONFIRMATIONS FOR COMPUTER SYSTEMS

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0069509A1 (en) * 1981-06-25 1983-01-12 Fujitsu Limited A circuit for reading out address data applied to a memory in a one-chip microcomputer
US4878168A (en) * 1984-03-30 1989-10-31 International Business Machines Corporation Bidirectional serial test bus device adapted for control processing unit using parallel information transfer bus
EP0157424A2 (en) * 1984-04-04 1985-10-09 Bull HN Information Systems Inc. LSI microprocessor chip with backward pin compatibility
EP0157424A3 (en) * 1984-04-04 1986-10-29 Honeywell Information Systems Inc. Lsi microprocessor chip with backward pin compatibility
EP0177848A2 (en) * 1984-09-26 1986-04-16 Honeywell Bull Inc. LSI microprocessor chip with backward pin compatibility and forward expandable functionality
EP0177848A3 (en) * 1984-09-26 1988-01-13 Honeywell Bull Inc. Lsi microprocessor chip with backward pin compatibility and forward expandable functionality

Also Published As

Publication number Publication date
GB2023341B (en) 1983-01-06
DE2824862C2 (en) 1990-10-31
FR2428353B1 (en) 1984-11-30
FR2428353A1 (en) 1980-01-04
JPS54162438A (en) 1979-12-24
DE2824862A1 (en) 1979-12-20

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19930605