FR2428353A1 - SEMICONDUCTOR DIGITAL MONOLITHIC INTEGRATED CIRCUIT - Google Patents
SEMICONDUCTOR DIGITAL MONOLITHIC INTEGRATED CIRCUITInfo
- Publication number
- FR2428353A1 FR2428353A1 FR7913590A FR7913590A FR2428353A1 FR 2428353 A1 FR2428353 A1 FR 2428353A1 FR 7913590 A FR7913590 A FR 7913590A FR 7913590 A FR7913590 A FR 7913590A FR 2428353 A1 FR2428353 A1 FR 2428353A1
- Authority
- FR
- France
- Prior art keywords
- integrated circuit
- monolithic integrated
- semiconductor digital
- semiconductor
- signal input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/22—Means for limiting or controlling the pin/gate ratio
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017545—Coupling arrangements; Impedance matching circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1731—Optimisation thereof
- H03K19/1732—Optimisation thereof by limitation or reduction of the pin/gate ratio
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Networks Using Active Elements (AREA)
- Processing Of Color Television Signals (AREA)
Abstract
L'invention concerne un circuit intégré monolithique numérique à semi-conducteurs. Dans ce circuit, qui comporte deux circuits partiels K1, K2, deux registres à décalage SR1, SR2, il est prévu au moins un raccord électrique A du corps semi-conducteur raccordé de façon fixe aussi bien à une entrée des signaux qu'à une sortie des signaux, les signaux numériques transmis par le raccord A pouvant être exploités au choix par l'intermédiaire de circuits extérieurs. Application notamment aux circuits de télécommande d'appareils de télévision.A digital semiconductor monolithic integrated circuit is disclosed. In this circuit, which comprises two partial circuits K1, K2, two shift registers SR1, SR2, there is provided at least one electrical connection A of the semiconductor body fixedly connected both to a signal input and to a signal input. signal output, the digital signals transmitted by connection A which can be used as desired via external circuits. Application in particular to remote control circuits for television sets.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19782824862 DE2824862A1 (en) | 1978-06-06 | 1978-06-06 | MONOLITHICALLY INTEGRATED DIGITAL SEMICONDUCTOR CIRCUIT |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2428353A1 true FR2428353A1 (en) | 1980-01-04 |
FR2428353B1 FR2428353B1 (en) | 1984-11-30 |
Family
ID=6041189
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7913590A Granted FR2428353A1 (en) | 1978-06-06 | 1979-05-29 | SEMICONDUCTOR DIGITAL MONOLITHIC INTEGRATED CIRCUIT |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPS54162438A (en) |
DE (1) | DE2824862A1 (en) |
FR (1) | FR2428353A1 (en) |
GB (1) | GB2023341B (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57212563A (en) * | 1981-06-25 | 1982-12-27 | Fujitsu Ltd | Address reading circuit for one-chip microcomputer |
US4878168A (en) * | 1984-03-30 | 1989-10-31 | International Business Machines Corporation | Bidirectional serial test bus device adapted for control processing unit using parallel information transfer bus |
US4654789A (en) * | 1984-04-04 | 1987-03-31 | Honeywell Information Systems Inc. | LSI microprocessor chip with backward pin compatibility |
US4677548A (en) * | 1984-09-26 | 1987-06-30 | Honeywell Information Systems Inc. | LSI microprocessor chip with backward pin compatibility and forward expandable functionality |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2330116A1 (en) * | 1975-11-03 | 1977-05-27 | Philips Nv | MEMORY IN WHICH THE STORED INFORMATION IS PASSENGER AND THE ACCESS TO THE INFORMATION IS RANDOM |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2517630B2 (en) * | 1975-04-21 | 1977-12-01 | Siemens AG, 1000 Berlin und 8000 München | PARTIAL SETUP OF A DATA PROCESSING SYSTEM |
DE2744111A1 (en) * | 1977-09-30 | 1979-04-05 | Siemens Ag | CIRCUIT ARRANGEMENT FOR THE INPUT OF INTERRUPTION COMMANDS AND OUTPUT OF INTERRUPTION CONFIRMATIONS FOR COMPUTER SYSTEMS |
-
1978
- 1978-06-06 DE DE19782824862 patent/DE2824862A1/en active Granted
-
1979
- 1979-05-29 FR FR7913590A patent/FR2428353A1/en active Granted
- 1979-06-05 GB GB7919512A patent/GB2023341B/en not_active Expired
- 1979-06-06 JP JP7108679A patent/JPS54162438A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2330116A1 (en) * | 1975-11-03 | 1977-05-27 | Philips Nv | MEMORY IN WHICH THE STORED INFORMATION IS PASSENGER AND THE ACCESS TO THE INFORMATION IS RANDOM |
Non-Patent Citations (1)
Title |
---|
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 13, no. 7, décembre 1970, page 1819, New York, USA * |
Also Published As
Publication number | Publication date |
---|---|
DE2824862A1 (en) | 1979-12-20 |
JPS54162438A (en) | 1979-12-24 |
GB2023341B (en) | 1983-01-06 |
GB2023341A (en) | 1979-12-28 |
FR2428353B1 (en) | 1984-11-30 |
DE2824862C2 (en) | 1990-10-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |