GB2021861A - Field effect transistors - Google Patents

Field effect transistors

Info

Publication number
GB2021861A
GB2021861A GB7918077A GB7918077A GB2021861A GB 2021861 A GB2021861 A GB 2021861A GB 7918077 A GB7918077 A GB 7918077A GB 7918077 A GB7918077 A GB 7918077A GB 2021861 A GB2021861 A GB 2021861A
Authority
GB
United Kingdom
Prior art keywords
nitride
polysilicon
gate
source
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB7918077A
Other versions
GB2021861B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Boeing North American Inc
Original Assignee
Rockwell International Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/909,886 external-priority patent/US4277881A/en
Priority claimed from US05/913,258 external-priority patent/US4231051A/en
Application filed by Rockwell International Corp filed Critical Rockwell International Corp
Publication of GB2021861A publication Critical patent/GB2021861A/en
Application granted granted Critical
Publication of GB2021861B publication Critical patent/GB2021861B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32105—Oxidation of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

In a self-aligning method an oversize gate insulator is covered with a layer of polysilicon which is masked with a nitride "button" to enable the polysilicon and underlying insulator to be etched to the desired dimensions. A silicon wafer 32 has a layer 34 of thermal oxide which is patterned to form source and drain windows the spacing between which is greater than the final channel length. A layer of polysilicon is then applied and covered with silicon nitride 54 and these layers are patterned to mask the device areas and expose the surrounding oxide which is removed and replaced by thermally grown field oxide 50. The nitride layer is repatterned to mask gate, source and drain areas, the unprotected polysilicon is removed leaving spaced contacts 40 and the unwanted margins of the oxide strip 34 thus exposed are removed so that the gate nitride button defines the gate width and position. Thermal oxide 60 is grown in the grooves between the contacts 40. The source and drain regions 70 and 72 are formed by driving dopant in from the polysilicon in this step and/or by ion implantation before this step. The nitride buttons are removed and a conductive layer is applied, and patterned to form external source, gate and drain connections 62S, 62G and 62D. Mask alignment tolerances are high, in particular it suffices if the gaps between the nitride buttons straddle the edges of the source and drain windows. In an alternative method the field oxide is formed in an initial step using a nitride mask which is then removed. <IMAGE>
GB7918077A 1978-05-26 1979-05-24 Field effect transistors Expired GB2021861B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/909,886 US4277881A (en) 1978-05-26 1978-05-26 Process for fabrication of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US05/913,258 US4231051A (en) 1978-06-06 1978-06-06 Process for producing minimal geometry devices for VSLI applications utilizing self-aligned gates and self-aligned contacts, and resultant structures

Publications (2)

Publication Number Publication Date
GB2021861A true GB2021861A (en) 1979-12-05
GB2021861B GB2021861B (en) 1982-09-29

Family

ID=27129542

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7918077A Expired GB2021861B (en) 1978-05-26 1979-05-24 Field effect transistors

Country Status (1)

Country Link
GB (1) GB2021861B (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0054102A2 (en) * 1980-12-11 1982-06-23 Rockwell International Corporation Very high density cells comprising a ROM and method of manufacturing same
EP0054110A1 (en) * 1980-12-15 1982-06-23 Rockwell International Corporation ROM with redundant ROM cells employing a highly resistive polysilicon film for programming the cells
GB2121235A (en) * 1982-06-01 1983-12-14 Western Electric Co Method for manufacturing an insulated gate field effect transistor device
AT387474B (en) * 1980-12-23 1989-01-25 Philips Nv METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE
US5043298A (en) * 1989-03-09 1991-08-27 Kabushiki Kaisha Toshiba Process for manufacturing a DRAM cell
EP0477995A1 (en) * 1985-04-01 1992-04-01 Fairchild Semiconductor Corporation Process for forming CMOS and bipolar devices on the same substrate
US5340762A (en) * 1985-04-01 1994-08-23 Fairchild Semiconductor Corporation Method of making small contactless RAM cell
GB2362756A (en) * 1999-11-30 2001-11-28 Lucent Technologies Inc Semiconductive device having a self-aligned contact and landing pad structure and method of making same

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0054102A2 (en) * 1980-12-11 1982-06-23 Rockwell International Corporation Very high density cells comprising a ROM and method of manufacturing same
EP0054102A3 (en) * 1980-12-11 1983-07-27 Rockwell International Corporation Very high density cells comprising a rom and method of manufacturing same
EP0054110A1 (en) * 1980-12-15 1982-06-23 Rockwell International Corporation ROM with redundant ROM cells employing a highly resistive polysilicon film for programming the cells
AT387474B (en) * 1980-12-23 1989-01-25 Philips Nv METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE
GB2121235A (en) * 1982-06-01 1983-12-14 Western Electric Co Method for manufacturing an insulated gate field effect transistor device
EP0477995A1 (en) * 1985-04-01 1992-04-01 Fairchild Semiconductor Corporation Process for forming CMOS and bipolar devices on the same substrate
US5340762A (en) * 1985-04-01 1994-08-23 Fairchild Semiconductor Corporation Method of making small contactless RAM cell
US5043298A (en) * 1989-03-09 1991-08-27 Kabushiki Kaisha Toshiba Process for manufacturing a DRAM cell
GB2362756A (en) * 1999-11-30 2001-11-28 Lucent Technologies Inc Semiconductive device having a self-aligned contact and landing pad structure and method of making same
GB2362756B (en) * 1999-11-30 2002-06-05 Lucent Technologies Inc Semiconductor device having self-aligned contact and landing pad structure and method of forming same

Also Published As

Publication number Publication date
GB2021861B (en) 1982-09-29

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee