JP2596113B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a contact window of a fine semiconductor element.

2. Description of the Related Art Along with the high integration of semiconductor devices, miniaturization of elements is progressing. In order to realize the miniaturization of the element, it is necessary to finely form a contact window for wiring used in the element. Therefore, in the conventional method of manufacturing a semiconductor device, the realization is achieved by forming a fine photoresist pattern window.
For example, a description will be given with reference to FIGS. 5A to 5E. First, as shown in FIG. 5A, a P-type Si in which an oxide film 102 is formed in an element isolation region to perform element isolation is provided. On a substrate 101, a gate oxide film 103 and a poly-Si 104 which is a gate electrode wiring material are formed. Then, a resist 105 is formed at a position where a gate electrode wiring is to be formed by using photolithography technology.

Next, as shown in (b), the poly-Si 104 is anisotropically etched using the resist 105 as an etching mask to obtain a gate wiring 104 '. After removing the resist 105
Form a CVD oxide film. Further, the CVD oxide film is anisotropically etched by dry etching to form the same (C) sidewall spacer 106 ', and an n ⁺ region 107 is formed in the contact portion by ion implantation or the like. Next, as shown in (d), a CVD oxide film 108 such as PSG (phosphorus-doped glass) or BPSG (boron-phosphorus-doped glass) is formed, and heat treatment is performed to smooth the surface.

Then, a resist 109 is formed by removing the resist in the contact forming portion by using the photolithography technique. CVD oxide film 10 using resist 109 as an etching mask
8 is etched to expose the surface of the n ⁺ region 107 of the contact portion, and then the Al wiring 110 is formed as in (e) to form the source and drain wiring contacts of the MOSFET transistor. Met.

Problems to be Solved by the Invention However, in the conventional manufacturing method shown in FIG. 5, the following problems remain.

(1) In the resist 109 shown in FIG. 5 (d), when the contact portion becomes 1 μm or less, it is very difficult to form a contact window of the resist 109 with high accuracy, and opening a window smaller than 1 μm is very difficult. Difficult Also, if the contact is greatly spread, the gate electrode 104 'and the Al wiring 110 are in contact with each other, and the operation as a MOSFET is not performed.

(2) Since the resist 109 is formed by using the mask alignment of the photolithography technique, an alignment deviation of about 0.2 to 0.5 μm usually occurs. In order to prevent a defect due to the misalignment, a margin for alignment is required. Providing an alignment margin increases the area occupied by one element, and thus makes it difficult to miniaturize and highly integrate the element.

Means for Solving the Problems The present invention comprises a step of forming a conductive thin film to be a gate electrode on at least the entire main surface of a semiconductor substrate on which an element isolation region and a gate oxide film are formed; Forming a first photoresist in a region where a gate electrode is to be formed, and etching the first insulating thin film and the conductive thin film using the first photoresist as an etching mask. Performing the step of removing the first photoresist;
Forming the second insulating thin film, forming the second insulating thin film, performing a desired amount of anisotropic etching of the second insulating thin film, and ion-implanting the contact portion. Forming an impurity concentration region, forming a third insulating thin film on the entire surface, and forming a second photoresist in a region near the contact formation portion without considering the margin between the gate electrode and the contact formation portion. Forming a;
Using the second photoresist as an etching mask,
The method includes a step of etching the third insulating thin film by a desired amount, a step of removing the second photoresist, and a step of forming a wiring.

According to the present invention, after the gate electrode is insulated and separated by the first insulating thin film and the second insulating thin film on the gate electrode wiring, a third insulating thin film is formed on the gate electrode. By forming a contact window by etching a part (or all) of the third insulating thin film, the contact portion can be formed in a self-aligned manner with the gate electrode. It is not necessary and can be easily formed.

Further, even if a mask misalignment occurs during the formation of a resist at the time of forming a contact, the insulating property between the gate electrode and the wiring is not affected, so that there is no need for a margin for alignment and the element can be miniaturized. This also enables high integration.

Embodiment Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to the first invention.
FIG. 4 is a process cross-sectional view for explaining the embodiment of the present invention, in which an oxide film 2 is formed in a device isolation region and then a P-type (100) silicon (Si) substrate 1 on which a MOSFET gate oxide film 3 is formed. Then, as shown in FIG. 1A, a 300 nm thick n ⁺ polysilicon 4 doped with phosphorus is formed as a conductor thin film serving as a gate electrode, and a 300 nm thick CVD oxide film 5 is formed as a first insulating thin film.

Then, a resist 6 as a first resist is formed on the region where the gate electrode is to be formed by using the photolithography technique. Next, as shown in FIG.
Using dry etching as an etching mask
The CVD oxide film 5 is anisotropically etched and n ⁺ polysilicon 4
Is anisotropically etched to form a gate electrode 4 ', the resist 6 is removed, and a CV as a second insulating thin film is formed on the entire surface.
A D oxide film 7 is formed to a thickness of 100 to 300 nm. Next, as shown in FIG. 1C, the CVD oxide film 7 is anisotropically etched by dry etching or the like to form a sidewall spacer 7 ', and then arsenic (As) is introduced by ion implantation or the like to form an n ⁺ region. 8 is formed. Next, as shown in (D), a CVD oxide film 9 having low thermal fluidity as a third insulating thin film is formed on the entire surface by 200 nm.
Then, a CVD oxide film (BPSG film) 10 containing boron (B) and phosphorus (P) as an insulating thin film having high thermal fluidity is formed to a thickness of 300 nm.

Next, as shown in (E), a heat treatment is performed in a mist atmosphere of 800 ° C. or more to flow the BPSG film 10 to smooth the surface, thereby facilitating the formation of wiring to be formed later, and then forming a contact. The region other than the region and the vicinity of the gate electrode 4 'forming the contact, that is, the region other than the region above the gate electrode and the contact region is formed by the second photolithography technique.
A resist 11 is formed as a resist. At this time, the opening portion of the resist is wider than the contact portion, and it is not necessary to form a fine hole in the resist. Next, as shown in (F), the BPSG 10 and the CVD oxide film 9 are anisotropically etched by dry etching or the like. At this time, a part of the BPSG film 10 and the CVD oxide film 9 remain near the sidewall spacer 7 '. This allows
One end of the contact surface of n ⁺ region 8 is determined in a self-aligned manner with gate electrode 4 ′. Next, as shown in (G), the resist 11 is removed, a natural oxide film naturally formed on the surface of the n ⁺ region 8 is removed by wet etching or the like, and then the Al thin film 12 for forming the wiring and the Al thin film 12 are removed. A resist 13 on the wiring formation region is formed. Next, as shown in FIG.
After etching the Al thin film 12 using the as an etching mask, the resist 13 is removed to form contacts for the source / drain regions of the MOSFET.

(Second Embodiment) FIG. 2 is a process sectional view for explaining a second embodiment of the method of manufacturing a semiconductor device according to the present invention. After forming by the same method as in (C), as shown in FIG. 2 (D), a BPSG film 12 as an insulating thin film having high thermal fluidity as a third insulating thin film is formed on the entire surface. Next, as shown in FIG. 7E, a heat treatment is performed in a mist atmosphere of 800 ° C. or more to flow the BPSG film 10 so as to smooth the surface so that subsequent wiring can be easily formed. A resist 11 is formed in a region other than the vicinity of the gate electrode 4 'for forming a contact. At this time, the opening of the resist is wider than the contact portion, and it is not necessary to make a fine hole in the resist. Thereafter, the BPSG film 10 is etched in substantially the same manner as in the first embodiment, and then an Al wiring 12 'is formed to obtain the same (H).

Third Embodiment FIG. 3 is a process sectional view for explaining a third embodiment of the method of manufacturing a semiconductor device according to the present invention. After being formed in the same manner as in (C), a third insulating thin film is formed as shown in FIG.
After the formation of the CVD oxide film 9, a resist 11 is formed in a region other than the contact formation region and the vicinity of the gate electrode 4 'for forming the contact. Also in this case, similarly to the above-described first and second embodiments, fine drilling of a resist is unnecessary. Hereinafter, almost the same as in the first embodiment, after etching the CVD oxide film 9, the Al wiring 12 is formed. 'To obtain the same (K).

(Fourth Embodiment) FIG. 4 is a process sectional view for explaining a fourth embodiment of the method of manufacturing a semiconductor device according to the present invention. After forming by the same method as in D), heat treatment is performed in a fog atmosphere at 800 ° C. or higher to flow the BPSG10 film and smoothen the surface. Next, as shown in FIG. 4 (L), a resist 11 is formed in a region other than the contact formation region. At this time, the resist 11 does not need to completely cover the gate electrode 4 'region, but is formed so as to be partially exposed, so that a hole can be formed wider than the actual contact region. Thereafter, the BPSG film 10 and the CVD oxide film 9 are etched in substantially the same manner as in the first embodiment, and then the Al wiring 12 "is formed to obtain the same (N).

In the above, the BPSG film has been described as an insulating film having high thermal fluidity from the first embodiment to the fourth embodiment. May be used. Even when a fine contact is required as described in the first to fourth embodiments, a resist opening for opening a contact window can be formed on the gate electrode, and the fine resist can be formed. Drilling is not required. In addition, since the gate electrode 4 'and the contact portion are determined in a self-aligned manner, it is not necessary to provide a margin for mask alignment.

Effects of the Invention As described above, according to the method of manufacturing a semiconductor device of the present invention, the following effects can be obtained.

(1) Since the gate electrode is covered with the first insulating thin film and the second insulating thin film, a resist opening for forming a contact may be formed on the gate electrode. The opening of the window is large,
It becomes easy to form a resist hole for contact.

(2) Further, since the contact can be formed in a self-aligned manner with respect to the gate electrode, there is no need for a mask alignment margin between the contact portion and the gate electrode, and the element can be formed finely.

[Brief description of the drawings]

FIG. 1 is a process sectional view for explaining a first embodiment of a method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a process cross-section for explaining a second embodiment of the method for manufacturing a semiconductor device according to the present invention. FIG. 3 is a process sectional view for explaining a third embodiment of the method of manufacturing a semiconductor device of the present invention, and FIG. 4 is a view for explaining a fourth embodiment of the method of manufacturing a semiconductor device of the present invention. FIG. 5 is a process sectional view showing an example of a conventional method for manufacturing a semiconductor device. 1 silicon substrate, 6 resist (first resist), 2 oxide film, 7 CVD oxide film (second insulating thin film), 3 gate oxide film, 7 'side Wall spacer, 4... N ⁺ polysilicon, 8... N ⁺ region,
4 ': gate electrode, 9: CVD oxide film (third insulating thin film), 5: CVD oxide film (first insulating thin film), 10 ...
... BPSG film (insulating thin film with high thermal fluidity).

Claims (3)

(57) [Claims] A step of forming a conductive thin film serving as a gate electrode on at least the entire main surface of a semiconductor substrate on which an element isolation region and a gate oxide film are formed; and forming a first insulating thin film on the conductive thin film. Forming, forming a first photoresist in a region where a gate electrode is to be formed, and etching the first insulating thin film and the conductive thin film using the first photoresist as an etching mask;
A step of removing the first photoresist, a step of forming a second insulating thin film on the entire surface, a step of anisotropically etching the second insulating thin film by a desired amount, and ion implantation to a contact portion Forming a high-impurity-concentration region, forming a third insulating thin film over the entire surface, and forming a third insulating thin-film in a region other than the vicinity of the contact formation portion without considering the allowance between the gate electrode and the contact formation portion. Forming a second photoresist, using the second photoresist as an etching mask, etching the third insulating thin film by a desired amount, removing the second photoresist, and wiring Forming a semiconductor device. 2. An insulating thin film having a low thermal fluidity is formed from a third insulating thin film, and then an insulating thin film having a high thermal fluidity is formed. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said semiconductor device is formed by flowing. 3. The semiconductor according to claim 1, wherein the third insulating thin film is formed by using an insulating thin film having a high thermal fluidity and flowing the third insulating thin film by heat treatment. Device manufacturing method.