GB2014766A - Data processing apparatus - Google Patents

Data processing apparatus

Info

Publication number
GB2014766A
GB2014766A GB7847981A GB7847981A GB2014766A GB 2014766 A GB2014766 A GB 2014766A GB 7847981 A GB7847981 A GB 7847981A GB 7847981 A GB7847981 A GB 7847981A GB 2014766 A GB2014766 A GB 2014766A
Authority
GB
United Kingdom
Prior art keywords
instruction
output
store
adder
latches
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB7847981A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB2014766A publication Critical patent/GB2014766A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/328—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for runtime instruction patching

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

Data processing apparatus incorporates a prewritten instruction store and instruction driver hardware which mitigates the relative inflexibility of a prewritten instruction store without undue extra cost or operating time overhead. A read only instruction store 1' is connected to an adder 15 together with the output from output latches 21 of a writable data store 2. The output of the adder is connected to the instruction register 7'. In response to one native instruction in the instruction register 7', the data store 2' is accessed and its output is held in the latches 21. In response to another native instruction in the instruction register 7', the instruction store 1' is accessed and its output is added to the output of the latches 21 in the adder 15 and the modified instruction is entered into the instruction register 7' thus providing simple direct instruction modification. <IMAGE>
GB7847981A 1978-02-15 1978-12-11 Data processing apparatus Withdrawn GB2014766A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA296,870A CA1106978A (en) 1978-02-15 1978-02-15 Simple flexible indexing method for ros storage microcomputers

Publications (1)

Publication Number Publication Date
GB2014766A true GB2014766A (en) 1979-08-30

Family

ID=4110763

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7847981A Withdrawn GB2014766A (en) 1978-02-15 1978-12-11 Data processing apparatus

Country Status (5)

Country Link
JP (1) JPS54114944A (en)
CA (1) CA1106978A (en)
DE (1) DE2902601A1 (en)
FR (1) FR2417807A1 (en)
GB (1) GB2014766A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0110227A2 (en) * 1982-11-24 1984-06-13 HONEYWELL INFORMATION SYSTEMS ITALIA S.p.A. Control memory organization

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62205429A (en) * 1986-03-06 1987-09-10 Nec Corp Microcomputer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0110227A2 (en) * 1982-11-24 1984-06-13 HONEYWELL INFORMATION SYSTEMS ITALIA S.p.A. Control memory organization
EP0110227A3 (en) * 1982-11-24 1984-07-25 Honeywell Information Systems Italia S.P.A. Control memory organization

Also Published As

Publication number Publication date
CA1106978A (en) 1981-08-11
FR2417807A1 (en) 1979-09-14
JPS54114944A (en) 1979-09-07
DE2902601A1 (en) 1979-08-16

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)