JPS56162156A - Data processing system - Google Patents
Data processing systemInfo
- Publication number
- JPS56162156A JPS56162156A JP6508680A JP6508680A JPS56162156A JP S56162156 A JPS56162156 A JP S56162156A JP 6508680 A JP6508680 A JP 6508680A JP 6508680 A JP6508680 A JP 6508680A JP S56162156 A JPS56162156 A JP S56162156A
- Authority
- JP
- Japan
- Prior art keywords
- address
- debug
- actual
- logical
- debug information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE:To perform flexible debug information processing, by converting a debug execution address besides an instruction address and an operand address to an actual by an address conversion mechanism to access a memory for debug, etc. CONSTITUTION:For the purpose of obtaining an actual address from a logical address for one virtual space, contents of a segment base register SBR and the S field of a logical address register LAR are inputted to an operator ALUO to obtain a pertinent address of a segment table ST, and this address is accessed to input a page table leading address PTC and the P field of the logical addres regiser LAR to an operator ALU1, and a pertinent address of a page table, and this address is accessed to read out an actual page address BPA. The virtual space is extended, and a debug information address space is provided, thereby performing flexible debug information processing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6508680A JPS56162156A (en) | 1980-05-16 | 1980-05-16 | Data processing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6508680A JPS56162156A (en) | 1980-05-16 | 1980-05-16 | Data processing system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56162156A true JPS56162156A (en) | 1981-12-12 |
JPS6113615B2 JPS6113615B2 (en) | 1986-04-14 |
Family
ID=13276769
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6508680A Granted JPS56162156A (en) | 1980-05-16 | 1980-05-16 | Data processing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56162156A (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH046574Y2 (en) * | 1987-12-28 | 1992-02-24 | ||
JPH02116822U (en) * | 1989-03-03 | 1990-09-19 | ||
JPH08280427A (en) * | 1995-04-12 | 1996-10-29 | Sakuseshia:Kk | Production of catcher for pierced earring |
-
1980
- 1980-05-16 JP JP6508680A patent/JPS56162156A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6113615B2 (en) | 1986-04-14 |
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