DE2902601A1 - PROCEDURE AND DATA PROCESSING SYSTEM FOR IMPLEMENTING AN COMMAND MODIFICATION - Google Patents

Description

. 29Q26Q1

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Applicant: International Business Machines

ι Corporation, Armonk, NY 10504

I heb-om

! Procedure and data processing system for implementation ι a command modification

The invention relates to a method and a data processing system for command modification and in particular a method and an arrangement by which each part of a Command can be modified in a data processing system before it is carried out.

State of the art

In modern data processing systems, especially in small systems and microprocessors, the commands are normally supplied by read-only memory. This of course means that you lose flexibility in comparison with stored-program programs Systems in which commands can be changed in their sequence and in their operation code.

Heretofore, there have been complicated indexing methods and arrangements used with index registers to overcome these difficulties. Usually such procedures and Apply circuits only to a part of the entire instruction set and / or you only have a limited number of Index registers that need to be loaded and modified, or the operational part of the instruction itself cannot be used change.

The circuit of US Pat. No. 3,503,046 issued to German patent application A 52 326 dated April 30, 1966, discloses an instruction modification circuit which This appears to be disadvantageous insofar as arithmetic registers are essentially used for indexing. this

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is a less than favorable restrictive condition because additional machine cycles are required to load the registers are. There are also idle machine cycles for modification of the command and further cycles for setting and resetting a bistable trigger circuit for the desired one Modification of commands needed. Only one instruction address modification is provided in this patent.

The object of the invention is to provide a further improved arrangement and a further improved method for the modification of instructions without the need for additional registers and complicated circuitry while virtually any or all of the commands can be modified at the same time.

As is known, modern data processing systems, in particular Small systems and microcomputers store instructions by means of read-only memories, while data storage by using modifiable memories such as B. Saving with random access is achieved. According to the The present invention are commands stored in a read-only memory (ROS) by means of a freely addressable Memory retrievable data can be modified. Thereby are made a read-only memory a command and from a freely addressable memory fetched data, and if an indexing gate is keyed, the command and the Data combined in an adder circuit. The modified command then appears at the output of the adder circuit on. With this simple arrangement, the instruction set of the read-only memory can be modified in many ways The only limitation is the capacity of the freely addressable memory. So you can achieve a very high level of versatility by adding a little additional circuitry.

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Thus, the invention provides a method and a Anj be established order for the modification of instructions in data encryption processing systems ¹ according to the .aufweisen at least two memory.

: A first of these memories, which is normally a read-only memory: is stored for selective access Information addressed. The command addressed and fetched from the first memory then becomes an error modifying circuit fed to an adder I can contain. Then data is stored in another memory, which is usually random access memory, according to ; one from the first memory during a previous one Processing cycle, if possible addressed to the command recorded immediately preceding processing cycle. the so addressed data are fed to a command modifier circuit which is selectively controllable so that can also selectively output this addressed data to the command modification circuit. The one from the The data recorded in the modification circuit and the command fetched are then combined in the command modification circuit combines and provides a modified command to the data processing system for use by it Plant in essentially the same way as an unmodified one Command.

You can see immediately that this results in a considerably expanded set of instructions.

The invention is now based on an exemplary embodiment explained in detail in conjunction with the accompanying drawings.

In the drawings shows
1 shows a block diagram of a data processing unit

state-of-the-art system to which

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a command modification according to the invention is applied,

Fig. 2 is a block diagram of a data processing system, the method and the arrangement used according to the invention, and

FIG. 3 is a simplified circuit diagram of an embodiment of the present invention as shown in FIG a data processing system is used.

The prior art data processing system shown in FIG. 1 contains two memories, namely an instruction memory 1 and a data memory 2.

A command consists of an operation part or operand and an address part, although there are also commands additional fields for special purposes. Of course, the invention can also be extended to such Apply commands.

Each memory is assigned its own address register, which is used in a known manner for selective addressing and selective retrieval of the memory content by branching or switching is used. The instruction memory 1 is through a Command address register 3 (BAR) controlled, while the data memory 2 is controlled by a data address register 4 (DAR) will. Thus, commands or data can be selectively retrieved from their respective memories.

A branch line 5 permits the branching of commands within a program, while the line 6 is used to issue commands from the command memory to initiate data access in the data memory 1 and other command sequences .

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The command appearing at the output of the command memory 1 is fed to an operation register 7, which at clock-wise Actuation by a clock pulse the command to an input 10 of an arithmetic and logic unit 8 (ALU) for a processing of data supplied from the data memory 2 to the input 11 of the arithmetic and logical Unit 8 and from output 13 of ALU 8 via accumulator 9 to input 12 of ALU 8.

The output 14 of the accumulator and the input 12 of the ALU are connected to input / output devices in a known manner.

In general, in data processing systems, as shown, for example, in FIGS. 1, 2 and 3 are shown, commands stored in the system from a command memory, such as the command memory 1 shown here, and called up in a data memory, such as. B. the data memory 2 stored and retrieved from this data can be used. In modern data processing systems, especially in small systems and microcomputers, the instruction memory consists of a read-only memory, whereby these read-only memories are either provided with these stored commands during manufacture or are designed as so-called programmable read-only memories (PROM) that are equipped with a Sequence of commands can be programmed.

Once these memories are permanently installed, it is usually not economically feasible to change the programming of the PROM or to exchange the instruction memory , since the downtimes would not be acceptable.

In systems such as in FIG. 1, the data stored in the data memory can be changed. This is usually done either a random access memory or a

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Serial memory used, whereby the insertion, modification or deletion of data stored in the memory in the system by internal or external input signals can be carried out.

It is also generally known that in data processing systems of this type, two surgical phases are usually performed in a cycle, usually one after the other or in parallel or both. These operations are access to commands or command fetching and then the application of commands or the execution of commands with data to achieve the desired result.

It seems logical to examine how a data processing system works in the middle of an operation.

First of all, the command call and then the command execution should be considered. During the next Command selectively from the command memory as read-only memory according to the address stored in the command address register 3 is called up, the data in the data memory 2 are stored in the processing cycle of the system in accordance with the data in the DAR 4 addresses located selectively and retrieved in the ALU with from the output 14 of the accumulator 9 to the input 12 of the ALU 8 combined data returned.

After this operating cycle has elapsed, the output 13 of ALU 8 is a product of the operation designated in the operation register 7 with the operation at the data output of the data memory 2 and at the output 14 of the accumulator 9 on data delivered. That output signal occurring at output 13 is then passed through the data processing system is set in the accumulator 9 in the usual manner.

"Then the command address register 3 is switched on after the address of the next command or over the branch line when a branch command

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should occur immediately. The data address register 4 is used for addressing the next data word set according to the address identifier contained in the command fetched from the command memory.

For an application of the method and the arrangement according to the invention to this belonging to the prior art System will be a command modifier / gate and special commands followed by modify commands are called, provided, as will be described in detail.

Arrangements that work in a similar way to the block diagram according to FIG. 1, are provided with similar reference numerals.

The improved data processing system according to the invention shown in Fig. 2 includes at least two addressable memories (although the use of additional memories for greater versatility is also to be considered), one of which is the instruction memory 1 'and the other of which is the data memory 2 ¹ . The information in these memories can be called up selectively via the corresponding index registers, namely the command ^{address register 3 1} and the data address register 4 '.

In this embodiment, there is the command modifying circuit from an instruction modification adder stage (IMA) 15, although other modifying circuits such as AND / OR or Exclusive-OR gates etc., depending on the desired results, can be used, this adder 15 at its input 16 with the instruction memory Coming commands is controlled while the input 18 is connected to the IMA gate circuit 17.

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Data are transferred to the IMA gate circuit 17 from the data memory 2 * fed.

^{The operation register 7 1} connected to the IMA 15, the ALU 8 * and the accumulator 9 ¹ have the same function as the corresponding parts in FIG. 1. The ^{branch line 5 * connecting the instruction address register 3 1} and the data address register 4 * is used as before for instruction branching . A line 19 connects the output 20 of the IMA 15 to the data address register 4 'for a selective retrieval of data from the connected data memory 2'.

As already explained, for the application of the invention Procedure on a data processing system, a special command must be provided, which is referred to as a modification command and which with the usual others Commands are stored together in the command memory 1 '.

In the data processing systems most affected here the content of the command memory 1 * cannot be changed so that the memory content, the commands within the command memory 1 'cannot be changed. Of the from the command memory 1 'via the command address register 3' The modification command called works like any other command called from the memory when executing Operations. The operand part and the address part of the Command codes are retrieved from the command memory 1 'more or less at the same time as data according to the im Data address register 4 * (i.e. the address of the previous Line 19 recorded command) can be retrieved from the data memory 2 *.

Provided that no previous modification command requires a modification of the modification command currently under consideration, this command is unmodified

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, allowed through IMA 15 (since the IMA gate circuit 17 is not j over a pulse on the pulse line 21 is gated jand therefore remains blocked).

If the operation register 7 ¹ is actuated by a clock pulse on the IT clock line 22, the modification command runs to the input 10 'of the ALU 8 and sets the ALU 8 ¹ to the desired function. Data supplied to input 11 of ALU 8 ¹ from data memory 2 ¹ and previously processed data I from accumulator 9 which are supplied to ALU input 12 'are then stored in the ALU in accordance with the operand received at input 10' 8 ¹ arithmetically combined with one another.

At the end of this phase, the ^{result appearing at the ALU output 13 1} is set in the accumulator 9 ¹ and thus passed on to the output devices (not shown).

At the end of this operating phase, the BAR 3 'is replaced by a Clock pulse advanced and the address part of the aforementioned modification command enters DAR 4 '.

During the next operational phase, the next command from the command memory 1 ¹ is called up in the usual way according to the ^{address stored in the BAR 3 1} , while practically at the same time data is called up from the data memory 2 ¹ via an address that comes from the address part of a previous one Instruction in DAR 4 ¹ , ie in this case from the modification instruction.

In the method according to the invention, the data are from; the data memory 2 ¹ through the IMA gate circuit 17 only allowed if a modification command to carry out! a modification is processed, but not if the executed command (such as the previous command) is an ordinary command coming from the command memory 1 '.

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The previous modification command is carried out the subsequent actuation of the IMA gate circuit 17, which the data from the data memory 2 'after the input 18 of the IMA 15 lets through, which is then recorded at input 16 Commands and the data recorded at input 18 are arithmetically combined with one another, for example by addition, and a modified instruction address after DAR 4 'and a modified instruction opcode or operand sends to the operation register 7 '»

The improvement according to the invention has the effect that the modification command modifies each subsequent command and the modified command can ^{be processed in the usual way in the arithmetic, logic unit 8 1} and also in other ways in the system.

The person skilled in the art will immediately recognize that when a modification instruction is decoded -Operands in the operation register 7 'a toggle pulse to the IMA gate circuit 17 almost immediately the pulse input 21 is applied so that the next command can be modified.

Fig. 3 shows a simplified circuit diagram of an embodiment of the invention in a data processing system, such as For example, it is shown schematically in FIG the corresponding structural elements and components for carrying out the invention.

The person skilled in the art will immediately recognize that this embodiment to be described here is based on microprocessors with a word length of 8 bits and can be used with 8-bit instructions (4 bits for the address and 4 bits are provided for the operand).

It is immediately evident that the present invention, with appropriate modifications, can be applied to data words and commands

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other lengths is applicable. Longer data words and longer commands would of course increase the processing options and also increase the complexity of the system.

In general, small data processing systems and microprocessors are composed of integrated circuits, which are commercially available. Commercially available circuits such as registers and gate circuits are preferred used whenever possible, while other circuits, such as read-only memory for special Requirements can be ordered. The invention will now be made with reference to FIG. 2, specifying suitable therefor Components are described.

As shown in Fig. 3, two addressable memories are provided, further memories can of course also be provided. The command memory 1 "can hold 8-bit commands store and is formed from two masked, programmed integrated circuits 1a and 1b. Each of these integrated Circuits is available from Texas Instruments Inc. under Part No. 74187 from j and can be used with • predetermined programming can be procured. Since every in-

I I

jgrierte circuit can only store 4-bit information, j

^: two integrated circuits required. The integrated!

Circuit 1a is used to store the address part of the Be ι

missing and the circuit 1b for storing the ent- '

speaking operands are used.

The read only memories are programmed with two types of commands, namely normal commands and modification commands. The latter instructions have operands of selected encoding with certain common identifiers, the after decoding provide a switching signal or gating signal for the command modifier circuits, so that subsequent Command modifications can be carried out.

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The other memory, the data memory 2 ", also exists of two parts. Each part consists of an integrated circuit with a 16x4 bit memory for random Access. These random access memories are available as off-the-shelf parts under Parts Wr. 7489 from Texas Instruments Inc. available. The random access memory, the data memory, is denoted by 2a and 2b. Simultaneous actuation of the two partial memories allows operations with 8-bit data words.

The command memory 1 "is made from a command address register 3" via corresponding command cables A and A "for a selective Access to stored commands addressed. The activated, stored commands appear on the output side Output cables B and B '"Supply the output cables B and B' the address part and the corresponding operand part of the commands to IMA 15 ".

In the same way, the data memory 2 ″ via the associated data address register DAR 4 ″ via a data register or Output cable D addressed for selective access to stored data. The data output cables E and E "are on the ALU 8 "connected.

; In this example the instruction address register 3 "consists of two registers 3a and 3b connected together. The registers 3a and 3b can be switched either by stepping or by branch charging via a branch cable c, which consists of the Lines Ci, C2, C3 and C4 are actuated. Entry guidelines K1 and K2 are used in the usual way to load registers 3a and 3b, respectively. Registers 3a and 3b can be obtained commercially under Part No. 74163 from Texas Instruments Inc. be integrated circuits available.

DAR 4 "is a 4-bit, pulse-activated, self-locking register that is connected to the IMA address output on the input side on cable C connected. 9 09 8 3 3/0588

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The operation register 7 "is connected to the IMA 15b output C and, when loaded, delivers output signals to the ALU 8 via the ALU- '■ operand input ^{cable D 1.} The registers DAR 4" and 7 "can use commercially available parts with the Part No. 7495 from Texas Instruments Inc.

The modification adding circuit IMA 15 'consists of two Adding stages 15a and 15b and represents the modification circuit in this example Each of the adder stages 15a or 15b can provide a 4-bit sum for the modification operation. Each of the adding stages 15a or 15b can be commercially available Part No. 7483 can be obtained from Texas Instruments Inc.

Other circuits, such as, for example, AND / OR gates, exclusive OR gates, can also be used as the modification circuit or many other functional circuits, depending on the type of modification of an instruction, can be used and it is here expressly stated that the invention does not

■ Adding circuits should be restricted as modification circuits.

The modification adding circuit 15 'is connected on the input side to the command output cables B and B ^{1, respectively.} The cable B list is connected to the adder 15a and the cable B ¹ to the adder 15b and supplies the corresponding address or operand part of the command. The output lines J and J ^{1 of} the modification adding gate circuits 17a and 17b of the modification gate circuit 17 'supply modification input signals after the adding stages 15a and 15b, respectively. The gate circuits 17a, 17b in this example are integrated circuits which are commercially available from Texas Instruments Inc. under Part No. 74157. The input signals on the lines E and E ¹ for the gate circuit 17a or 17b can be derived from the output cables E and E ¹ of the data memory 2 ".

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Output signals then only appear on lines J and J " on when the pulse input K3 is triggered by a corresponding Output of the decoder circuit 23 is operated, the is controlled by the operand input cable D '»

The decoder 23 can be obtained as a programmable read-only memory circuit (PROM) / ie a decoder constructed as an integrated circuit in which corresponding bit patterns are stored, under the type no. 82S123, commercially available from Signetics Corporation. The decoder 23 supplies the corresponding input signals via the lines K1 and K2 for loading the command address register 3 * and for actuating the IMA gate circuit 17 'when corresponding signals: or information are available on the cable D ¹ , ie when the operand part of a modification command lies on the cable D '. The other output signals that are available on the remaining output lines Kn can be used at other points in the data processing system, for example to control the output of signals at the accumulator 9 ″ or as input control for the ALU 8 ″.

The arithmetic logic unit 8 "consists of paired integrated circuits available under part number 74181 from Texas Instruments Inc., which are designated here as 8a J and 8b. The integrated circuits 8a and 8b are input to the output cables E and E. ¹ or connected to the input / output cables F or F ^1. Operand input cable D ¹ sets the desired function for a comparison of the information supplied by the aforementioned cables in the ALU 8 ".

The ALU output cables G and G 'are on the sub-circuits 9a and 9b of the accumulator 9 "are connected. The accumulator 9" is connected on the output side to input / output devices and then emits output signals when the charging line 24 is actuated by the system in the usual manner

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The accumulator 9 "consists of a pair of 4-bit registers and can be separated from the ALU without affecting the contents of the accumulator. Each of the two registers 9a and 9b of the accumulator 9 ″ may be one commercially available from Texas Instruments Inc. under Part No. 74295 be integrated circuit.

Although the working sequence of the method and the mode of operation of the circuit constructed according to the invention are now clear should be, but the mode of operation of the embodiment of the invention shown in FIG. 3 according to the invention Procedures are described.

As already mentioned, ordinary commands and modification commands are stored in the command memory 1 ″ a modification command occurs, it is decoded after detection by the decoder 23 and supplies the modification of the next command.

The system is now to be considered in operation. A command is to be fetched from the command memory 1 ". For To call up the command, the command address register can be operated in the same way that the stepping line is activated once which initiates a sequential loading process , or by loading the content of the output signal of the adder that occurs on cable C or ■ Adding circuit through selective impulse actuation ! the charging line K2 or K1. This allows a command block or a separate command can be selected within a command block.

When BAR 3 "is pressed, a command in the command memory is selectively activated ^{via cables A and A 1. The selected command then appears on output cables B and B 1} and is applied to the inputs of the modification adders 15a and 15b, respectively.

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If the immediately preceding command was not a modification command, then the decoding stage 23 does not supply a keying pulse via line K3 to gate circuit 17 "(17a and 17b), so that the output lines J and J 'remain inactive. Regardless of what the order was for the manager B and B 'occurs, this will occur on the output lines C and C in unmodified form and will be in the system processed in the usual way »

If, on the other hand, the previous command was a modification command, then the gate circuit 17 ° is keyed so that information arriving from the data memory 2 " via the cables E and E" is passed through to the lines J and J '. The modification adding circuit 15' is this information arithmetic combine and deliver a modified instruction (ie an instruction fetched from instruction memory 1 which is modified by data fetched by the address of a previous modification instruction) «

In this way, either the operand or the address or both parts of an instruction are modified.

The invention provides that all parts or each part of the] data, for example two of the 8 bits for a modification ^; either part of the operand address or both parts j of an instruction can be supplied. ^:

: It is further seen that when a · is to be modified loading 'ifehl a null command, the "retrieved from data memory 2 ¹ Idaten be used as the modified command, so that on; thus, if desired, data and commands. can be stored in the data memory.

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At the end of an instruction access cycle, a clock pulse is emitted on the line of the DAR 4 "and the operation register 7", which causes the output ^{cables D and D 1 to} carry output signals, while the instruction address register 1 "

j continued in the usual way for access to new commands is switched.

The address part of the modified command then runs into the data memory 2 ″ via the cable D, while the corresponding modified operand part on cable D 'one ! Function set in ALU 8 ".

The ALU 8 "combines the data supplied ^{here via cables E and E 1} and the input / output cables F and F ^1.

In the next cycle, the accumulator 9 "(9a, 9b) is set to the output signal of the ALU 8". This output signal occurs on input / output lines F and F 'and controls peripheral devices such as B. Printer, Fern-I recorders or magnetic tape units.

In this way an instruction can be modified; the data address register can be assigned the address of a modified one Instruction can be loaded and the operation register can be opened with

I loaded a modified operand.

It will be appreciated that the decoder 23 can easily be constructed or chosen to take any subsequent command the command immediately following can be modified.

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Claims (1)

PATENTAN 'S CLAIMS Method for modifying commands in a \ : data processing system with at least two memories with memory address registers, an operation register,; an arithmetic and logical unit and an accumulator, ! characterized by the following process sequence: j - addressing the first of the two memories (V, 1 ") ! for selective access to a stored command and forwarding that command to a Command modification circuit (IMA, 15), - Addressing data in the other memory (2 ¹ , 2 ") in accordance with an instruction taken from the first memory in a previous processing cycle, - Forwarding of the data thus obtained to a modifying gate (17) and selective gating this gate circuit for a selective switching through of this data after the command modifying circuit (IMA, 15) and Combining these data supplied to the command modifying circuit with the command received there to issue a modified command for the data processing system. Method according to Claim 1, characterized in that the first memory is a read-only memory and the second memory a randomly addressable, modifiable memory can be used. J3. Method according to claim 1 or 2, characterized in that
that as a command modifying circuit, an adder circuit CA 977 004 29026Qi is used, which is a modify gate is connected upstream, which is then selectively activated and keyed when you have the address of a mode: fication command was supplied during the immediately preceding processing cycle and then the so addressed data to the modify-adder circuit (IMA, 15) gives, and that there these data and the addressed and retrieved Instruction to a modified instruction can be combined with each other in such a way that selectively the operand * - part and / or the address part of the command addressed and retrieved can be modified. Data processing system for carrying out a method according to claims 1 to 3 with at least two Storage and memory address registers with an operational register, an arithmetic and a logical Unit (ALU) and an accumulator connected to it, characterized by a selectively controllable instruction memory (1) and a selectively controllable and in its memory content modifiable data memory (2), both of which are selectively associated with their Memory address registers (BAR, DAR, 3, 4) are controllable, and one to the instruction memory and via a gate circuit (17) to the data memory (2) connected modification circuit (IMA, 15) for a combination of the data with the command to create a modified command and in that the gate circuit (17) accordingly one of the command modifying circuit in command recorded in a previous cycle can be applied. CA 977 004 2802601 Data processing system according to Claim 4, characterized in that the command memory is a read-only memory and the Data storage is random access storage. Data processing system according to Claim 5, characterized in that that the command modifying circuit contains a gate circuit (17a, 17b) which after receiving the address of a modification instruction during the immediately preceding processing cycle for a selective one Switching the retrieved data through to the modify-adder circuit (15, IMA) can be pressed. 30β833 / 05βδ CA 977 004