FR2417807A1 - METHOD AND DEVICE FOR MODIFYING INSTRUCTIONS IN A DATA PROCESSING SYSTEM - Google Patents

METHOD AND DEVICE FOR MODIFYING INSTRUCTIONS IN A DATA PROCESSING SYSTEM

Info

Publication number
FR2417807A1
FR2417807A1 FR7901296A FR7901296A FR2417807A1 FR 2417807 A1 FR2417807 A1 FR 2417807A1 FR 7901296 A FR7901296 A FR 7901296A FR 7901296 A FR7901296 A FR 7901296A FR 2417807 A1 FR2417807 A1 FR 2417807A1
Authority
FR
France
Prior art keywords
data processing
processing system
modifying instructions
instruction
modifying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7901296A
Other languages
French (fr)
Inventor
Stephen L Dunik
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2417807A1 publication Critical patent/FR2417807A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/328—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for runtime instruction patching

Abstract

Procédé et dispositif permettant de modifier des instructions contenues dans une mémoire inaltérable 1 au moyen de données contenues dans une mémoire altérable 2. Un modificateur d'instructions 8 combine les sorties de ces deux mémoires pour fournir une instruction modifiée. Ce procédé et ce dispositif n'exigent pas de registres supplémentaires ou de circuits complexes tout en offrant la possibilité de modifier n'importe quelle instruction d'un programme ou microprogramme.Method and device for modifying instructions contained in an unalterable memory 1 by means of data contained in an alterable memory 2. An instruction modifier 8 combines the outputs of these two memories to provide a modified instruction. This method and device does not require additional registers or complex circuitry while providing the ability to modify any instruction of a program or firmware.

FR7901296A 1978-02-15 1979-01-12 METHOD AND DEVICE FOR MODIFYING INSTRUCTIONS IN A DATA PROCESSING SYSTEM Withdrawn FR2417807A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CA296,870A CA1106978A (en) 1978-02-15 1978-02-15 Simple flexible indexing method for ros storage microcomputers

Publications (1)

Publication Number Publication Date
FR2417807A1 true FR2417807A1 (en) 1979-09-14

Family

ID=4110763

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7901296A Withdrawn FR2417807A1 (en) 1978-02-15 1979-01-12 METHOD AND DEVICE FOR MODIFYING INSTRUCTIONS IN A DATA PROCESSING SYSTEM

Country Status (5)

Country Link
JP (1) JPS54114944A (en)
CA (1) CA1106978A (en)
DE (1) DE2902601A1 (en)
FR (1) FR2417807A1 (en)
GB (1) GB2014766A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1153668B (en) * 1982-11-24 1987-01-14 Honeywell Inf Systems CONTROL MEMORY ORGANIZATION
JPS62205429A (en) * 1986-03-06 1987-09-10 Nec Corp Microcomputer

Also Published As

Publication number Publication date
GB2014766A (en) 1979-08-30
DE2902601A1 (en) 1979-08-16
CA1106978A (en) 1981-08-11
JPS54114944A (en) 1979-09-07

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Legal Events

Date Code Title Description
ST Notification of lapse