JPS62205429A - Microcomputer - Google Patents

Abstract

PURPOSE:To execute the free change and the holding of the secret of the contents of a machine instruction executed by an CPU by providing an address control circuit, a logical synthesizing circuit, etc., and changing the value of a built-in RAM. CONSTITUTION:From a program counter 1 to an address control circuit 11, a bus line 16 is provided. Thus, a RAM 4 is individually accessed from an address pointer 2 by the input of a control signal inversion MODIFY through a circuit 11 and accessed from the counter 1 simultaneously with a ROM 3. The ROM 3 and the RAM 4 are connected by bus lines 15, 16 and 18, and through a logical synthesizing circuit 12, the output is logically synthesized. Either of the data read from the ROM 3 by the input of the signal inversion MODIFY or the logical synthesizing result is sent through a changing-over circuit 13 to a data bus 5 and stored into an instruction register 6. Thus, the contents of the machine instruction executed by a CPU can be freely changed and the secret can be held.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer, and particularly to a microcomputer having one chip.

[Conventional technology]

FIG. 4 shows a block diagram of a conventional microcomputer incorporating ROM and RAM. In the conventional microcomputer, data stored in the ROM 3 designated by the program counter 1 is input to the instruction register 6 via the data bus 5. Furthermore, the contents of the RAM 4 indicated by the address pointer 2 are output to the data bus 5.

Generally, a user can program machine language data arbitrarily into the ROM 3, and the operation of the microcomputer is determined by the contents of the ROM 3.

[Problem that the invention seeks to solve]

In the conventional microcomputer described above, when a mask ROM is used in which the data stored in the built-in ROM 3 is determined during the manufacturing process, it is not possible to change the contents of the machine language instructions stored in the ROM 3 after manufacturing. There was a drawback that it could be stored away.

Furthermore, in the conventional microcomputer, a third party could easily read the machine language instructions stored in the built-in ROM 3 by using the test function (built-in ROM helifi function) of the microcomputer. Therefore, it has the disadvantage that its secrecy cannot be maintained.

An object of the present invention is to change the value of the built-in AM even if the contents of the built-in ROM are fixed.
To provide a microcomputer which can freely change the contents of machine language instructions executed by a PU and can keep secrets.

[Means for solving problems]

A microcomputer device incorporating a microcomputer H1ROM and a RAM according to the present invention includes means for simultaneously accessing the ROM and RAM, and means for executing a logical synthesis result of the output of the ROM and the output of the RAM as an instruction. are doing.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

As shown in FIG. 1, in this embodiment, a new address control circuit +1 is provided as a means for simultaneously accessing ROM3, R, and AM4, and program counters 1 to 11,
A bus line 16 is also provided from the program counter 1 to the address control circuit 11 in parallel with the bus line 15 connected to 0M3,
Through the RAM4H address control circuit 11, the control signal MO
By inputting DIFY, access can be made from the seat address pointer 2 independently or from the program counter 1 at the same time as the ROM 3. Note that the numbers written in parentheses for each bus line indicate the number of bits.

Next, a logic synthesis circuit 12 is provided to logically synthesize the respective outputs of ROM3 and RAM4.
Both M4s were connected with a bus line to enable logic synthesis. For example, an exclusive OR gate can be used as the logic synthesis circuit.

Next, a switching circuit 13 is provided as a means for executing the logic synthesis result as a command, and is connected to both the ROM 3 and the logic synthesis circuit 12 by a bus line, and is controlled by inputting a control signal MODIFY.
Either the data read from in, 0M3 or the logic synthesis result is sent to the data bus 5 and stored in the instruction register 6.

An example of the detailed circuit of the newly installed address control circuit is shown in the second section.
FIG. 3 shows an example of a detailed circuit of the switching circuit.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 to 3 and Table 1.

Table 1 First, as an initial value, program counter 1 points to address θ of ROM 3 with a capacity of 4 bytes. Control terminal 7
When the control signal MODIFY is set to "1", the address control circuit 11 configured as shown in FIG. The switching circuit 13 configured as shown in FIG. In other words, if the address of program counter 1 is @000 as shown in Table 1, it will not operate in the same way as the conventional example (Fig. 4).
', @001 am, ......, the corresponding ROMa storage data "03", @A7"
, . . . are taken into the instruction register 6. Here, when the value of program counter 1 is at address ``''BA3'BA3' and the control signal MODIFY is set to @O#, at,
The control circuit 11 uses an 8-bit address that is a combination of the lower 4 bits of the program counter output and the upper 4 bits generated by the address generation circuit 110 to write to the fiRAM 4.
control to point to. In this embodiment, F" is generated in hexadecimal as the upper 4 bits2), so the 256-byte R
In the AM area, 16 bytes at address ``Fo#~''FF' are valid. Therefore, as shown in Table 1, the address control circuit 11 Lower 4 of program counter 1
RAM
This means that ROM3 and ROM4 were accessed at the same time. Also, the control signal MO
When DIFY is 0'', the switching circuit 13 works to output the output of the logic synthesis circuit 12 to the data bus 5.
Exclusive OR of ``''EA3''''EA3' address ``2D'' and RAM content ``a01'' at address @Fs''``2D'' ■ ``0
1"-"2C" is taken into the instruction register 6 via the data bus 5.

Similarly, the value of program counter 1 becomes "EA9".
.

``When EAA# and ``EAB'' increase, the output of the address control port 11, that is, the address of the built-in RAM 4 becomes ``
The commands change to "F9", "FA", and @FB, and the instruction register 6 contains 14n"■105"="4E#" and "A", respectively.
4#■'68''=@CC'', "69"■'''A1''=@
C8" is input. As a result, the control signal MOD
While iFY is @0#, the instruction register 6 contains ROM.
The contents of the machine language data in step 3 modified by the data in RAM 4 cannot be taken in as an instruction.

In this embodiment, a method of modifying a part of the program stored in the built-in ROM using the control terminal 7 has been described, but a wide range of other applications are possible. In other words, an arbitrary area of the built-in RAM can be designated as an area for storing modification data using the address conversion circuit, or the control signal MOD I FY can always be set to 10# to modify all the machine language data in the built-in ROM. machine language instructions may be generated. In addition to external terminals, there is also a method of using a mode register or the like as a control means.

〔Effect of the invention〕

As explained above, the present invention provides machine language instructions by obtaining machine language instructions from the logical synthesis results of built-in ROM output and built-in RAM output.
By changing the value of M, the content of machine language instructions executed by the CPU can be freely changed.

Roughly speaking, if the built-in ROM output modification function according to the present invention is used, even if a third party reads the contents of the built-in ROM using the built-in ROM verification 1 function, the content of the machine language instruction executed by the CPU cannot be determined from that information alone. Because it is not possible to know
It has the effect of keeping that secret.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
A circuit diagram of an example of a detailed circuit of the address control circuit shown in Figure 3.
The figure is a circuit diagram of an example of a detailed circuit of the switching circuit in figure 1,
The figure is a block diagram of an example of a conventional microcomputer. 1...Program counter, 2...Address pointer, 3...Inner & ROM, 4...
...Built-in RAM. 5...Data bus, 6...Instruction register, 7...External control terminal, 11...Address control circuit, 12...Logic Synthesis circuit, 13
...Switching circuit, 15.16°17.18...
...Pass line, 110...RAM upper address generation circuit. Agent: Patent Attorney Ken Uchihara ¥10

Claims (1)

[Claims] A microcomputer having a built-in ROM and a RAM, characterized in that it has means for simultaneously accessing the ROM and the RAM, and means for executing a logical synthesis result of the output of the ROM and the output of the RAM as an instruction. .