GB2012135A - Parallel analog-to-digital converter - Google Patents
Parallel analog-to-digital converterInfo
- Publication number
- GB2012135A GB2012135A GB79440A GB7900440A GB2012135A GB 2012135 A GB2012135 A GB 2012135A GB 79440 A GB79440 A GB 79440A GB 7900440 A GB7900440 A GB 7900440A GB 2012135 A GB2012135 A GB 2012135A
- Authority
- GB
- United Kingdom
- Prior art keywords
- comparator
- output
- reference levels
- differential
- analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
An analog signal is converted into an n bit digital signal (B1, B2, B3) by n comparator circuits (C1, C2, C3) which compare the analog input to 2<n>-1 reference inputs (A1-A7). Each comparator output alternates as the analog signal increases through the reference levels, logic circuitry including n-1 exclusive- OR gates (34, 38) decoding the comparator outputs into the n bit code. The comparator circuit C3 for comparing the analog input signal VIN with each of reference levels A1, A3, A5 and A7 and providing an alternating output comprises pairs of differential input transistors Q1 and Q2, Q4 and Q5 etc. and current sink transistors Q3, Q6 etc. associated with the reference levels. The collectors of the differential transistor pairs are cross coupled to two output resistors R9, R10 which are connected to a differential exclusive-OR gate 38. A latching circuit Q18, Q19 is operable to latch the comparator output when the comparator is in other than the comparing mode. <IMAGE>
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US86710278A | 1978-01-05 | 1978-01-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2012135A true GB2012135A (en) | 1979-07-18 |
| GB2012135B GB2012135B (en) | 1982-06-23 |
Family
ID=25349087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB79440A Expired GB2012135B (en) | 1978-01-05 | 1979-01-05 | Parallel analogue -to-digital converter |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS6028452B2 (en) |
| CA (1) | CA1140267A (en) |
| DE (1) | DE2900219A1 (en) |
| FR (1) | FR2414268A1 (en) |
| GB (1) | GB2012135B (en) |
| NL (1) | NL7900095A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0082736A2 (en) * | 1981-12-22 | 1983-06-29 | Sony Corporation | Analogue to digital converter |
| WO1991004609A1 (en) * | 1989-09-18 | 1991-04-04 | Analog Devices, Inc. | Parallel analog-to-digital converter using 2(n-1) comparators |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5886846U (en) * | 1981-12-09 | 1983-06-13 | 酒井 友治 | heating tatami |
| JPS6334353Y2 (en) * | 1986-08-08 | 1988-09-12 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL84059C (en) * | 1948-02-26 | |||
| DE1232200B (en) * | 1965-01-08 | 1967-01-12 | Siemens Ag | Circuit arrangement for converting amplitude values into a binary code |
| DE1268196B (en) * | 1966-07-26 | 1968-05-16 | Siemens Ag | Analog-to-digital converter |
| US3495233A (en) * | 1966-12-28 | 1970-02-10 | Bell Telephone Labor Inc | Last stage of a stage by stage encoder |
| US3573798A (en) * | 1967-12-18 | 1971-04-06 | Bell Telephone Labor Inc | Analog-to-digital converter |
| FR2306575A1 (en) * | 1975-04-02 | 1976-10-29 | Nadler Morton | METHOD AND DEVICE FOR CONVERTING ANALOGUE ELECTRIC SIGNAL INTO BINARY CODE |
-
1979
- 1979-01-04 DE DE19792900219 patent/DE2900219A1/en not_active Ceased
- 1979-01-05 FR FR7900256A patent/FR2414268A1/en not_active Withdrawn
- 1979-01-05 NL NL7900095A patent/NL7900095A/en not_active Application Discontinuation
- 1979-01-05 GB GB79440A patent/GB2012135B/en not_active Expired
- 1979-01-05 CA CA000319183A patent/CA1140267A/en not_active Expired
- 1979-01-05 JP JP54000928A patent/JPS6028452B2/en not_active Expired
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0082736A2 (en) * | 1981-12-22 | 1983-06-29 | Sony Corporation | Analogue to digital converter |
| EP0082736A3 (en) * | 1981-12-22 | 1986-03-26 | Sony Corporation | Analogue to digital converter |
| WO1991004609A1 (en) * | 1989-09-18 | 1991-04-04 | Analog Devices, Inc. | Parallel analog-to-digital converter using 2(n-1) comparators |
Also Published As
| Publication number | Publication date |
|---|---|
| NL7900095A (en) | 1979-07-09 |
| JPS54106159A (en) | 1979-08-20 |
| FR2414268A1 (en) | 1979-08-03 |
| DE2900219A1 (en) | 1979-07-12 |
| JPS6028452B2 (en) | 1985-07-04 |
| GB2012135B (en) | 1982-06-23 |
| CA1140267A (en) | 1983-01-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |