GB1604308A - Process for the production of semiconductor bodies - Google Patents

Process for the production of semiconductor bodies Download PDF

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Publication number
GB1604308A
GB1604308A GB23885/78A GB2388578A GB1604308A GB 1604308 A GB1604308 A GB 1604308A GB 23885/78 A GB23885/78 A GB 23885/78A GB 2388578 A GB2388578 A GB 2388578A GB 1604308 A GB1604308 A GB 1604308A
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disc
recesses
process according
bodies
semiconductor
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GB23885/78A
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Semikron GmbH and Co KG
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Semikron GmbH and Co KG
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Die Bonding (AREA)
  • Dicing (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

In a method of producing semiconductor bodies by dividing up a large-area semiconductor starting wafer (1) containing at least one p-n junction (S1) and having a contact metal coating (12,14; 22,23,24) on each side of the starting wafer, in order to utilise the area of the starting wafer as well as possible and to ensure a uniform edge chamfering of the semiconductor body trench-like depressions (5) are provided on one side of the starting wafer, which are closed upon themselves and are determined in each case by the shape of the semiconductor body and which extend through the p-n junction of the starting wafer and expose the junctions. The depressions (5), which form a pattern, are filled with an insulating and stabilising substance (7) at least in the region of the emergence of the p-n junction (S1) at the surface. For the further processing of the semiconductor bodies envisaged, the starting wafer is provided with at least one metallic coating (12,14; 22,23,24) in each case on both sides in accordance with the predetermined area segments and then the starting wafer is separated, starting from the side not provided with depressions, in accordance with the existing pattern between adjacent depressions. <IMAGE>

Description

(54) PROCESS FOR THE PRODUCTION OF SEMICONDUCTOR BODIES (71) We, SEMIKRON, Gesellschaft fur Gleichrichterbau und Elektronik m.bh, a company existing uner the laws of the Federal Republic of Germany, of Sigmundstrasse 200, 8500 Nurnberg, Federal Replublic of Germany, do hereby declare the invention for which we pray that a Patent may be granted to us and the method by which it is to be performed to be particularly described in and by the following statement: This invention concerns a process for the production of semiconductor bodies.
In a known process a pre-formed disc of semiconducting material, having a layer sequence with at least one pnjunction, is provided with metallic coatings to serve as electrical contacts and then is divided into a plurality of individual semiconductor bodies, or chips, of smaller area which are then further processed separately as necessary to complete the construction of the operational semiconductor chips. For example, a carrier plate, for example of molybdenum or tungsten, may be alloyed to one side of the chip; the edge zone of the chip may be bevelled or faceted, for example by means of grinding and/or etching; and the semiconductor surface within the region of such bevelled edge zone may be subjected to a passivation or protection treatment; all of such further processes being carried out on the separated, individual chips.
This known process has a number of disadvantages. Alloying carrier plates individually to such chips is an expensive process. Bevelling or faceting the semiconductor chips results in an undesirably high loss of active surface. The truncated form of the semiconductor chips produced further adds to the loss of active surface area. When chips already provided with metallic contact coatings are subjected to etching, residues are deposited as impurities on the semiconductor surface and impair the electrical characteristics. Also grinding cannot always achieve a uniform shaping of the edge bevelling along the whole circumference of the chip. At least, if the faceting is effected by means of grinding, only semiconductor bodies with round surface form may be produced, as grinding of the faceting for semiconductor bodies with polygonal surface forms is not feasable in the desired manner. Thus, the originally formed semiconductor disc is not utilised optimally.
It is an object of the invention to provide a process for the production of semiconductor bodies in which the available surface of the original semiconductor disc can be most efficiently divided into the most favourable surface forms for the semiconductor bodies to be produced.
According to the invention we provide a process for the production of a plurality of individual semiconductor bodies from a preformed larger area disc of semiconducting material including a main zone of one conductivity type which extends completely across the entire disc and other zones of different conductivity type thereby affording a layer sequence with one or more pn-junctions, comprising the steps of forming on only one side of the pre-formed disc a plurality of separate, closed or endless recesses each of which defines the boundary of an area of a shape and size corresponding to the active area of one of the bodies to be produced with spaces outside each boundary between said recesses, the depth of each recess being sufficient for it to extend through at least one of said pn-junctions so as to expose it in said recess but without extending completely through the thickness of the disc, covering said exposed pn-junctions in said recesses by an insulating and stabilising substance, forming on opposite sides of the pre-formed disc metallic contact coatings as appropriate for each of the bodies to be produced, and after the above steps then dividing the pre-formed disc into individual semiconductor bodies by removing material from the disc along lines in said spaces between said recesses starting from the side opposed to that at which the recesses are formed.
The process in accordance with the invention will now be described by way of example with reference to the accompanying drawings where in:- Figure 1 shows in plan view a pre-formed semiconductor disc and the manner in which it is to be divided into a number of individual bodies or chips; Figure 2 shows a fragmentary cross-section on the line A-A of Figure 1 of such pre-formed disc after processing in accordance with the invention; and Figure 3 shows a similar fragmentary crosssection of a different disc affording two layer sequences of different structure, also after processing.
A large area disc 1 of semiconductor material with a main zone of one conductivity type (n in Figures 1 and 2) and other zones of different conductivity type, which define at least one pnjunction, is produced by the use of known techniques. This disc 1 is processed in accordance with the invention to produce a number of smaller area individual bodies, or chips, which may be of varying shape and size as shown for example by the division pattern indicated in Figure 1.
In accordance with the invention, on one side, herein called the upper side, the preformed disc 1 is firstly treated to form a plurality of recesses 5 in the form of closed or endless grooves which follow the intended outline of each individual body or chip to be produced, each recess 5 enclosing an area of the disc which is to correspond to the active area of one of the bodies to be produced. Each recess 5 achieves the desired superficial shaping for the respective body or chip being produced. The recesses 5 are shaped as appropriate in section, for example V-shape or truncated V-shape, and they extend not through the entire thickness of the disc but at least through the outermost conductivity zone and through the adjacent pnjunction surface S, so that at least one such pnjunction is interrupted and exposed within every recess 5, and may be masked with an insulating and stabilising coating. The extension of the spacecharge region within the region of the exit of the junction at the surface within the recess, and thus the blocking capability of the device produced, increases with the inclination of that side of the recess 5 nearest the centre of the enclosed surface by the effect of a reverse voltage, and the formation of the recesses serves the same purpose as bevelling the edges of individual chips in the previously known process.
The recesses 5 are so arranged that they each, being of endless or closed form, encompass completely the desired size active surface of one of the semiconductor bodies to be formed, whilst there remains a separation space between adjacent recesses where the disc 1 can subsequently be divided. It will be observed that in Figure 1 the shapes of the individual bodies are represented, not the recesses themselves.
The number and course of the recesses 5 therefore are determined by the intended division of the preformed disc 1 into semiconductor bodies of desired surface shape and surface area. The recesses each may have a round and/or a polygonal course. Their production may be effected by masking and etching, by ultrasonic drilling and postetching or by laser techniques. In the case of mechanical abrasion or grinding process, or in the case of the use of laser techniques, a post-etching process is necessary for the removal of impurities and/or lattice/dislocations.
In a following process step, the recesses 5 are filled, at least to an extent sufficient to mask the exposed pn-junction, with an insulating and stabilising substance 7. For that purpose known glass-forming substances, or known protective varnishes may be used. The former may be flow-melted at temperatures of approximately 700"C to 8000 C, and the latter may be applied preferably in liquid condition and cured generally by means of a suitable heat treatment.
It is to be noted that all the semiconductor bodies which are to be produced from the one pre-formed disc are still united at this stage and the provision of a protecting surface coat in all the recesses 5 of the disc 1 simultaneously under the same procedure conditions is particularly economical, especially as further procedure steps will not have a detrimental influence on the surface condition, and hence on the operational characteristics of the semiconductor bodies produced.
Glass passivation of the semiconductor surface of the semiconductor bodies furthermore makes it possible to carry out alloying processes on the surface of the pre-formed disc 1 for securing carrier plates and/or providing metallic contact coatings on the semiconductor bodies, without the preceding steps becoming inefficient and/or the electrical characteristics of the semiconductor material or other materials being unfavourably influenced.
Where such carrier plates are to be provided, for example of molybdenum, tungsten, tantalum, or of an iron-nickelcobalt- alloy, the plates may be secured on both sides of the pre-formed disc 1 by means of alloying over an intermediate layer, for example of aluminium. In this connection, for example the upper side may be provided with carrier plates each of an area and shape corresponding to the active surface of a respective one of the semiconductor bodies to be produced, and the underside of the disc 1 may be provided with a continuous carrier plate.
The materials and procedure temperatures for the alloy development are so chosen that the glass filling 7 in the recesses 5 is not impaired.
The glass-forming coat is for example formed at about 800 C, and the alloy process for securing carrier plates of molybdenum is effected over a silver coat up to about 700"C. However, individual carrier plates corresponding in number, shape and size to those on the upper surface may alternatively be secured on the underside of the disc 1 in register with those on the upper side, instead of a single continuous carrier plate 14 as shown in Figure 2.
Instead of, or additionally to, carrier plates the pre-formed disc may be provided with metallic coatings to serve as electrical contacts, for example with laminated coats of aluminium and silver, of nickel, chromium and nickel, of chromium and aluminium, of chromium, aluminium and nickel, of aluminium, chromium and nickel, of nickel and chromium, and of silver and chromium. These layer sequences are produced in known manner by means of deposition or vapour deposition and are, if necessary connected to a special firmly adhering contact coat with the semiconductor material, also in a subsequent alloying process. Insofar as such coats are not of etch-resistant materials, the disc must be provided with an etch-resistant coating if the disc is to be divided into individual semiconductor bodies by an etching process, such coating having the appropriate division pattern formed therein.
For example, an etch-resistant contact coat of gold may be arranged over an intermediate coat of nickel, an alloy process not being possible in this case because of the well known high diffusion rate of gold in silicon at high temperatures.
After the carrier plates and/or contact coatings are secured on the pre-formed disc 1, the latter is divided into the individual semiconductor bodies or chips of smaller and desired shape and area by removing material from the disc along lines in the spaces between the recesses starting from the side opposed to that at which the recesses are formed. For this various processes are possible. In the case of simple shapes, for example rectangular with uniform surface area, the disc may for example be divided by means of sawing through the spaces intentionally left between adjacent recesses 5.
By the use of laser techniques, the disc 1 may be divided, with the assistance of special control units for the laser beam guidance, also in more complicated separation patterns (such as shown in Figure 1) into bodies with different shapes and areas. If in this connection excessively high energy would be required for the laser beam to cut through the disc, in the first instance a partial sub division of the disc may be effected by means of a laser beam and then the division of the disc could be completed by means of an etching treatment for example. In this case, a masking process would be necessary to protect any surface of the disc not coated with an etch-resistant contact metal.
The division of the disc may also be effected by means of etching alone, and again in this case a preparatory procedure step would be required to deposit a corresponding etching pattern my means of masking. Etching techniques currently available make it possible to achieve relatively narrow etched slots 6 in separating the individual bodies from the discs.
In the example shown in Figure 2, are formed large area discs (only part of which is shown) has a layer sequence with two exterior, highly doped zones 2 and 4 of opposite conductivity type and one middle, low doped zone 3 of the conductivity type of the upper exterior zone 2. A continuous junction S is defined at the interface between the zones 3 and 4.
Recesses 5 are fromed at the upper side of the disc 1 according to a predetermined surface pattern, and such recesses 5 each enclose a predetermined area of the surface of a size and shape corresponding to the intended active area of the respective individual semiconductor bodies or chips to be formed from the disc. The recesses may for example in section have the form of an approximately isosceles tiangle, and be of such a depth that in this example the exterior zone 2 and the middle zone 3 are both completely penetrated so that the junction S is also piereced. The recesses 5 are so arranged that between the adjacent recesses of adjoining semiconductor bodies there remains a region of sufficient width for the subsequent development of a separation notch 6 by anyone of the processes referred to above.
After the development of the recesses 5, they are filled in with an insulating and stabilising substance 7. On the area of the surface which is enclosed by each recess 5, a metallic contact coating 12 is provided and on the underside of the disc 1 there is also provided a metallic contact coating 14 which may either be continuous or consist of discrete areas of coating in register with the coatings 12 on the upper surface. Typically the coating 14 may be formed in two or more layers 14a and 14b of different metals.
Finally, separation notches 6 according to the presecribed separation pattern are developed from the side of the disc opposite to the recess 5 so as to extend through the disc 1 completely in the zones defined between the adjacent recesses 5.
In the example shown in Figure 3, the preformed disc (only part of which is shown), has areas in which various different layer sequences have been produced by means of known masking and diffusion processes. In the illustrated example, one layer seqence I is formed with a single junction Sl and is intended for the production of a rectifier element, and an adjoining layer sequence II is formed with two pn-junctions Sl and S2 and is intended for the production of a transistor.
In accordance with the invention, the recesses 5 are formed in the disc on the side thereof which affords a continuous exterior zone of, for example, p-conductive material 4, the recesses as before each enclosing an area corresponding to a respective one of the semiconductor bodies to be produced. The recesses 5 penetrate fully through the exterior zone 4 of the disc and puncture the pnjunction S1.
Then the surface treatment in the recesses 5 is effected to form the protective coatings 7 and metallic contact coatings are produced on corresponding surface sections, for example to form contact electrodes 12 and 14 in the region of layer sequence I and contact electrodes 22, 23 and 24 respectively for emitter, base and collector, in the region of layer sequence II.
Now, where it is intended to produce semiconductor bodies with only one layer sequence in each, separation notches are developed where indicated at 6 and 61 in Figure 3. On the other hand, for making bodies incorporating for example two structures in an integrated arrangement of rectifier element and transistor, the separation notches are developed only where indicated at 6 in Figure 3.
Accordingly, the procedure of the invention allows in a surprisingly simple manner the production of semiconductor bodies or chips with arbitrary numbers and arrangements of layer sequences for the production of single elements or of spatially integrated elements if need he electrically isolated from one another.
The division pattern shown in Figure 1 indicates a typical combination of polygonal surfaces of different size and shape together with circular shapes of varying size as may be provided for the sub-division of disc 1 into a plurality of bodies of smaller surface area in such a manner as to maximise utilisation of the area of the disc 1. By carrying out all the procedure steps for the production of the semiconductor bodies of high reverse capability whilst they are still physically united in the preformed disc 1, there may be achieved, as may be seen in Figure 2, in a surprisingly simple manner semiconductor bodies of different areas and shapes so as to optimise the utilisation of the area of the pre-formed disc 1.
Amongst the advantages of the procedure according to the invention are the following; the surface treatment and the subsequent formation of metallic contact coatings are effected whilst the individual bodies are still united in the pre-formed disc in an economical manner under the same procedure conditions; The pre-formed semiconductor disc may be divided into individual semiconductor bodies with the desired surface shapes and areas designed for optimum utilisation of the surface of the disc; and semiconductor bodies may be produced with each have a structure for a semiconductor element or for serveral similar or different semiconductor elements.
The procedure as described above has the advantage that the loss of active surface can be minimised for each semiconductor body produced, furthermore the bevelling achieved by the inclined faces of the notches can be made uniform at all points, and it is possible to carry out on the preformed semiconductor body before it is divided at least some of those procedures which previously had to be carried separately on the individual bodies in accordance with the previously known methods of production.
WHAT WE CLAIM IS: 1. A process for the production of a plurality of individual semiconductor bodies from a pre-formed larger area disc of semiconducting material including a main zone of one conductivity type which extends completely across the entire disc and other zones of different conductivity type thereby affording a layer sequence with one or more pn-junctions, comprising the steps of forming on only one side of the preformed disc a plurality of separate, closed or endless recesses each of which defines the boundary of an area of a shape and size corresponding to the active area of one of the bodies to be produced with spaces outside each boundary between said recesses, the depth of each recess being sufficient for it to extend through at least one of said pn.junctions so as to expose it in said recess but without extending completely through the thickness of the disc, covering said exposed pn-junctions in said recesses by an insulating and stabilising substance, forming on opposite sides of the pre-formed disc metallic contact coatings as appropriate for each of the bodies to be produced, and after the above steps then dividing the pre-formed disc into individual semiconductor bodies by removing material from the disc along lines in said spaces between said recesses starting from the side opposed to that at wlich the recesses are formed.
2. A process according to Claim 1 wherein the contact coatings on one side of the disc are all formed simultaneously under the same procedure conditions.
3. A process according to Claim 1 or Claim 2 wherein on the side of the disc at which the recesses are formed, the contact coatings are formed only within the areas bounded by the respective recesses.
4. A process according to any of the preceding claims wherein on the other side of the disc a single continuous contact coating is formed.
5. A process according to any one of Claims 1 to 3 wherein on the other side of the disc separate contact coatings are formed in areas in register with the areas in register with the areas bounded by the recesses.
6. A process according to any one of the preceding claims wherein the layer sequence of the disc is different in different areas of the disc so that bodies are produced having different electrical functions.
7. A process according to any one of the preceding claims wherein at least some of the recesses are shaped to enclose round surfaces.
8. A process according to any one of the preceding claims wherein at least some of the recesses are shaped to enclose polygonally shaped surfaces.
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (23)

**WARNING** start of CLMS field may overlap end of DESC **. the disc and puncture the pnjunction S1. Then the surface treatment in the recesses 5 is effected to form the protective coatings 7 and metallic contact coatings are produced on corresponding surface sections, for example to form contact electrodes 12 and 14 in the region of layer sequence I and contact electrodes 22, 23 and 24 respectively for emitter, base and collector, in the region of layer sequence II. Now, where it is intended to produce semiconductor bodies with only one layer sequence in each, separation notches are developed where indicated at 6 and 61 in Figure 3. On the other hand, for making bodies incorporating for example two structures in an integrated arrangement of rectifier element and transistor, the separation notches are developed only where indicated at 6 in Figure 3. Accordingly, the procedure of the invention allows in a surprisingly simple manner the production of semiconductor bodies or chips with arbitrary numbers and arrangements of layer sequences for the production of single elements or of spatially integrated elements if need he electrically isolated from one another. The division pattern shown in Figure 1 indicates a typical combination of polygonal surfaces of different size and shape together with circular shapes of varying size as may be provided for the sub-division of disc 1 into a plurality of bodies of smaller surface area in such a manner as to maximise utilisation of the area of the disc 1. By carrying out all the procedure steps for the production of the semiconductor bodies of high reverse capability whilst they are still physically united in the preformed disc 1, there may be achieved, as may be seen in Figure 2, in a surprisingly simple manner semiconductor bodies of different areas and shapes so as to optimise the utilisation of the area of the pre-formed disc 1. Amongst the advantages of the procedure according to the invention are the following; the surface treatment and the subsequent formation of metallic contact coatings are effected whilst the individual bodies are still united in the pre-formed disc in an economical manner under the same procedure conditions; The pre-formed semiconductor disc may be divided into individual semiconductor bodies with the desired surface shapes and areas designed for optimum utilisation of the surface of the disc; and semiconductor bodies may be produced with each have a structure for a semiconductor element or for serveral similar or different semiconductor elements. The procedure as described above has the advantage that the loss of active surface can be minimised for each semiconductor body produced, furthermore the bevelling achieved by the inclined faces of the notches can be made uniform at all points, and it is possible to carry out on the preformed semiconductor body before it is divided at least some of those procedures which previously had to be carried separately on the individual bodies in accordance with the previously known methods of production. WHAT WE CLAIM IS:
1. A process for the production of a plurality of individual semiconductor bodies from a pre-formed larger area disc of semiconducting material including a main zone of one conductivity type which extends completely across the entire disc and other zones of different conductivity type thereby affording a layer sequence with one or more pn-junctions, comprising the steps of forming on only one side of the preformed disc a plurality of separate, closed or endless recesses each of which defines the boundary of an area of a shape and size corresponding to the active area of one of the bodies to be produced with spaces outside each boundary between said recesses, the depth of each recess being sufficient for it to extend through at least one of said pn.junctions so as to expose it in said recess but without extending completely through the thickness of the disc, covering said exposed pn-junctions in said recesses by an insulating and stabilising substance, forming on opposite sides of the pre-formed disc metallic contact coatings as appropriate for each of the bodies to be produced, and after the above steps then dividing the pre-formed disc into individual semiconductor bodies by removing material from the disc along lines in said spaces between said recesses starting from the side opposed to that at wlich the recesses are formed.
2. A process according to Claim 1 wherein the contact coatings on one side of the disc are all formed simultaneously under the same procedure conditions.
3. A process according to Claim 1 or Claim 2 wherein on the side of the disc at which the recesses are formed, the contact coatings are formed only within the areas bounded by the respective recesses.
4. A process according to any of the preceding claims wherein on the other side of the disc a single continuous contact coating is formed.
5. A process according to any one of Claims 1 to 3 wherein on the other side of the disc separate contact coatings are formed in areas in register with the areas in register with the areas bounded by the recesses.
6. A process according to any one of the preceding claims wherein the layer sequence of the disc is different in different areas of the disc so that bodies are produced having different electrical functions.
7. A process according to any one of the preceding claims wherein at least some of the recesses are shaped to enclose round surfaces.
8. A process according to any one of the preceding claims wherein at least some of the recesses are shaped to enclose polygonally shaped surfaces.
9. A process according to any one of the
preceding claims wherein the recesses are arranged to define a combination of shapes and sizes of surface areas which is appropriate for the optimum utilisation of the surface area of the preformed disc.
10. A process according to any one of the preceding claims wherein the recesses are formed at least partly by ultrasonic drilling.
11. A process according to any one of Claims 1 to 9 wherein the recesses are formed by means of etching and the disc is provided with an etch-resistant mask defining the layout of such recesses.
12. A process according to any one of Claims 1 to 11 wherein the recesses are filled with a protective varnish.
13. A process according to any one of Claims 1 to 11 wherein the recesses are filled with glass-forming substance.
14. A process according to any one of Claims 1 to 13 wherein the metallic contact coatings are formed by means of alloying and consist of sub-layers comprising an intermediate coat and a supporting plate of molybdenum, tungsten, tantalum or of a known ironnickel-cobalt alloy.
15. A process according to any one Claims 1 to 13 wherein the metallic contact coatings are formed by means of alloying and consist of sub-layers with the layer sequences aluminiumsilver, nickel-chromium-nickel, chromiumaluminium, chromium-aluminium ickel, aluminium-chromium-nickel, nickel-chromium or silver-chromium.
16. A process according to Claim 14 or Claim 15 wherein the sub-layers are formed'by means of deposition.
17. A process according to Claim 14 or Claim 15 wherein the sub-layers are formed by means of vapour-deposition.
18. A process according to any one of Claims 1 to 13 wherein the metallic contact coatings are formed of gold arranged if necessary over an intermediate coat which is firmly contact with the semiconductor material.
19. A process according to any one of the preceding claims wherein the pre-formed disc is divided into the individual bodies by means of laser beams.
20. A process according to any one of Claims 1 to 18 wherein the pre-formed disc is divided into the individual bodies by means of etching and the disc is provided with an etchresistant mask defining the division pattern.
21. A process as claimed in Claim 1 substantially as hereinbefore described.
22. A semiconductor body produced by the process according to any one of the preceding claims.
23. A semiconductor body according to Claim 22 substantially as herein before described with reference to and as shown in Figure 2 and 3 of the accompanying drawings.
GB23885/78A 1977-07-11 1978-05-30 Process for the production of semiconductor bodies Expired GB1604308A (en)

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DE19772731221 DE2731221A1 (en) 1977-07-11 1977-07-11 METHOD FOR MANUFACTURING SEMICONDUCTOR BODIES

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GB1604308A true GB1604308A (en) 1981-12-09

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JP (1) JPS5419358A (en)
BR (1) BR7804249A (en)
CH (1) CH629336A5 (en)
DE (1) DE2731221A1 (en)
FR (1) FR2397717A1 (en)
GB (1) GB1604308A (en)
IT (1) IT1098670B (en)

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Publication number Priority date Publication date Assignee Title
JPS57184597U (en) * 1981-05-20 1982-11-24
DE3211391A1 (en) * 1982-03-27 1983-09-29 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Method of producing a semiconductor device
DE3435138A1 (en) * 1984-09-25 1986-04-03 Siemens AG, 1000 Berlin und 8000 München Improvement to a method for separating semiconductor components which are obtained by breaking semiconductor wafers
DE3524301A1 (en) * 1985-07-06 1987-01-15 Semikron Gleichrichterbau METHOD FOR PRODUCING SEMICONDUCTOR ELEMENTS
JPS63108706A (en) * 1986-10-27 1988-05-13 Toshiba Corp Manufacture of semiconductor device
JP5903287B2 (en) * 2012-01-31 2016-04-13 新電元工業株式会社 Manufacturing method of semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4860871A (en) * 1971-11-30 1973-08-25
JPS4976469A (en) * 1972-11-27 1974-07-23
US3972113A (en) * 1973-05-14 1976-08-03 Mitsubishi Denki Kabushiki Kaisha Process of producing semiconductor devices

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JPS5419358A (en) 1979-02-14
IT1098670B (en) 1985-09-07
BR7804249A (en) 1979-04-10
FR2397717A1 (en) 1979-02-09
IT7825515A0 (en) 1978-07-10
DE2731221A1 (en) 1979-02-01
CH629336A5 (en) 1982-04-15

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