JP5903287B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor element.

  Some conventional semiconductor elements are configured by forming electrodes on a semiconductor substrate. As a method of forming a metal layer for an electrode on a semiconductor substrate, there is a plating method used in the method for manufacturing a semiconductor device of Patent Document 1.

In Patent Document 1, an N + type semiconductor layer is formed on one main surface of a semiconductor substrate, and a P type semiconductor layer is formed on the other main surface. A mesa groove is formed in the semiconductor substrate by etching from the N + type semiconductor layer side to a portion deeper than the PN junction surface. Thereafter, an anode electrode and a cathode electrode are respectively formed on the upper and lower main surfaces of the semiconductor substrate by plating.
By the way, when an electrode is formed on a semiconductor substrate, an alloy layer of a material for forming the semiconductor substrate and a material for forming the electrodes is provided at a connection portion between the semiconductor substrate and the electrodes. This alloy layer is formed by annealing a semiconductor substrate on which electrodes are formed by a plating method.

JP-A-6-204232

However, the plating method uses a large amount of chemical solution for pretreatment. For this reason, there exists a possibility that processing of a chemical | medical solution may cost, or a semiconductor substrate may be contaminated with a chemical | medical solution.
The present invention has been made in view of such problems, and an object of the present invention is to provide a method for manufacturing a semiconductor element that can form an alloy layer on a semiconductor substrate without using a plating method.

In order to solve the above problems, the present invention proposes the following means.
Production method of the present onset bright semi conductor elements, the sheet placement step of placing the metal sheet on one principal surface of the semiconductor substrate, by annealing the semiconductor substrate and the metal sheet, the metal sheet and the semiconductor substrate e Bei the annealing step to form an alloy layer, to the junction of the, in the sheet disposing step, is characterized in that for stacking said semiconductor substrate and said metal sheet alternately.
According to this invention, the alloy layer is formed by disposing a pre-formed metal sheet on one main surface of the semiconductor substrate and annealing. For this reason, an alloy layer can be formed on a semiconductor substrate without using a conventional plating method. Further, by using the metal sheet, the thickness of the metal covering one main surface of the semiconductor substrate becomes equal, and the thickness of the alloy layer can be easily made uniform.
Moreover, since an alloy layer is simultaneously formed on a plurality of semiconductor substrates, the manufacturing efficiency of the semiconductor element can be increased. In addition, a plurality of semiconductor elements can be manufactured in a compact manner.

In the method for manufacturing a semiconductor element, it is more preferable that the annealing process is performed while the metal sheet is in close contact with the semiconductor substrate.
According to the present invention, the gap between the semiconductor substrate and the metal sheet is reduced, so that the alloy layer can be formed more stably.

In the method of manufacturing a semiconductor element, a passivation film is formed in a mesa groove formed on one main surface of the semiconductor substrate, and the thickness of the metal sheet protrudes from the one main surface. More preferably, it is thicker than the height dimension of the membrane.
According to the present invention, the metal sheet disposed on the passivation film can be prevented from being damaged and broken by the passivation film, and the alloy layer can be more reliably formed.

In the method for manufacturing a semiconductor element, the metal sheet preferably contains 50 wt% or more and 100 wt% or less of nickel.
According to the present invention, it is possible to increase the purity of nickel in the alloy layer and reliably connect the outside through the alloy layer.

Further, in the semiconductor device manufacturing method, after the annealing step, a portion of the metal sheet that does not become the alloy layer is removed to expose the alloy layer, and on the alloy layer It is more preferable to include a metal layer forming step of forming a nickel layer.
According to the present invention, the connection strength between the solder and the like formed on the nickel layer and the alloy layer can be increased through the nickel layer.

  According to the method for manufacturing a semiconductor element of the present invention, an alloy layer can be formed on a semiconductor substrate without using a plating method.

It is a schematic sectional drawing which shows the semiconductor element manufactured by the manufacturing method which concerns on one Embodiment of this invention. It is a schematic sectional drawing which shows the state after a diffusion process in the manufacturing method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing which shows the state which apply | coated the resist at the oxide film formation process in the manufacturing method of the same semiconductor element. In the manufacturing method of the same semiconductor device, it is a schematic sectional view showing the state where the silicon oxide film pattern was formed in the oxide film forming step. In the manufacturing method of the same semiconductor device, it is a schematic sectional view showing the state after a mesa groove formation process. It is a schematic sectional drawing which shows the state after a surface treatment process in the manufacturing method of the same semiconductor element. It is a schematic sectional drawing which shows the state after a sheet | seat arrangement | positioning process in the manufacturing method of the same semiconductor element. It is a schematic sectional drawing which shows the state after an annealing process in the manufacturing method of the same semiconductor element. It is a schematic sectional drawing which shows the state after a metal layer formation process in the manufacturing method of the same semiconductor element. FIG. 6 is a schematic cross sectional view showing a state after a solder layer forming step in the method for manufacturing a semiconductor element. It is a schematic sectional drawing which shows the state after a cutting process in the manufacturing method of the same semiconductor element.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS. Hereinafter, a case where the semiconductor element is a mesa diode will be described as an example.
As shown in FIG. 1, a mesa diode 1 according to this embodiment includes a semiconductor substrate 2, nickel layers 3 and 4 formed on both main surfaces 2 a and 2 b of the semiconductor substrate 2, and solder layers 5 and 5. 6 and is generally configured.
The semiconductor substrate 2 has a second conductivity type (for example, p-type) p-type semiconductor layer 22 opposite to the first conductivity type on one surface of a first conductivity type (for example, n-type) n-type semiconductor layer 21. A nickel silicide layer (alloy layer) 23 is sequentially stacked, and a first conductivity type high-concentration n-type semiconductor layer 24 having a higher impurity concentration than the n-type semiconductor layer 21 is formed on the other surface of the n-type semiconductor layer 21. A silicide layer (alloy layer) 25 is laminated in order.
A p-type semiconductor layer 22 is disposed on the outer periphery of the nickel silicide layer 23, and a high-concentration n-type semiconductor layer 24 is disposed on the outer periphery of the nickel / silicide layer 25.

The impurity concentration of the n-type semiconductor layer 21 is, for example, 2 × 10 ¹⁴ atoms / cm ³ , and the impurity concentration of the p-type semiconductor layer 22 is, for example, 1 × 10 ¹⁹ atoms / cm ³ . Further, the high-concentration n-type semiconductor layer 24 is higher than the n-type semiconductor layer 21 and is, for example, 1 × 10 ¹⁹ atoms / cm ³ .
The semiconductor substrate 2 is formed, for example, in a rectangular shape in plan view, and a mesa groove 7 is formed on the outer peripheral edge of one main surface 2a thereof. The surface (inner surface) of the mesa groove 7 is curved and inclined in a concave shape from one main surface 2a of the semiconductor substrate 2 toward the side surface 2c. The junction interface (PN junction interface) between the n-type semiconductor layer 21 and the p-type semiconductor layer 22 is exposed on the surface of the mesa groove 7. In other words, the mesa groove 7 is formed deeper than the PN junction interface.

The surface of the mesa groove 7 is covered with a passivation film 8 made of glass or resin. The thickness of the passivation film 8 is substantially uniform. In the present embodiment, the passivation film 8 extends to the one main surface 2a of the semiconductor substrate 2 and covers the outer peripheral edge region of the one main surface 2a. In other words, the nickel layer 3 and the solder layer 5 formed so as to overlap one main surface 2 a of the semiconductor substrate 2 are surrounded by the passivation film 8.
Further, a silicon oxide film 9 is formed in the outer peripheral edge region of the other main surface 2 b of the semiconductor substrate 2. Therefore, the nickel layer 4 and the solder layer 6 formed to overlap the other main surface 2 b of the semiconductor substrate 2 are surrounded by the silicon oxide film 9.

The nickel layers 3 and 4 are layers containing nickel in an amount of 50 wt (wt) or more.
The total thickness of the nickel layer 3 and the solder layer 5 and the total thickness of the nickel layer 4 and the solder layer 6 are set larger than the thicknesses of the passivation film 8 and the silicon oxide film 9, respectively. It is preferable.

Next, an example of a method for manufacturing the mesa diode 1 having the above configuration (hereinafter referred to as a manufacturing method) will be described.
When manufacturing the mesa diode 1, first, as shown in FIG. 2, a first surface 2 a of a first conductivity type (for example, n type) semiconductor substrate 2 is opposite to the first conductivity type. A second conductivity type p-type semiconductor layer 22 is formed by diffusing two conductivity type (for example, p-type) impurities (diffusion process). Further, in the diffusion process of the present embodiment, the first conductivity type having a higher impurity concentration than the semiconductor substrate 2 is obtained by diffusing an impurity of the first conductivity type (n-type) into the other main surface 2 b of the semiconductor substrate 2. The high concentration n-type semiconductor layer 24 is formed.
The p-type semiconductor layer 22 is formed by disposing a sheet containing boron, aluminum, or the like on one main surface 2a of the semiconductor substrate 2 and baking it. On the other hand, the high concentration n-type semiconductor layer 24 is formed by disposing a sheet containing phosphorus or the like on the other main surface 2b of the semiconductor substrate 2 and baking it.
The semiconductor substrate 2 after the diffusion step forms the same n-type semiconductor layer 21 as the semiconductor substrate 2 before the step, the p-type semiconductor layer 22 that forms one main surface 2a of the semiconductor substrate 2, and the other main surface 2b. The high-concentration n-type semiconductor layer 24 is sandwiched.

After the diffusion step, silicon oxide film patterns are respectively formed on both main surfaces 2a and 2b of the semiconductor substrate 2 by using a photolithography method (oxide film forming step).
In this step, first, as shown in FIG. 3, silicon oxide films 11 and 12 are formed on the entire main surfaces 2a and 2b of the semiconductor substrate 2, respectively. The silicon oxide films 11 and 12 are formed, for example, by heating and oxidizing the semiconductor substrate 2.
Next, resists 13 and 14 made of a photosensitive resin are applied on the silicon oxide films 11 and 12, respectively. Thereafter, as shown in FIG. 4, a predetermined pattern is formed on each of the resists 13 and 14 by exposure and development to form resist patterns 13A and 14A. The pattern formed on each resist pattern 13A, 14A is the same as the pattern to be formed on each silicon oxide film 11, 12. Then, using the resist patterns 13A and 14A as a mask, the silicon oxide films 11 and 12 are etched to form a predetermined pattern to form silicon oxide film patterns 11A and 12A. The etching may be any etching such as dry etching or wet etching.

  The silicon oxide film patterns 11A and 12A formed as described above will be described in detail. A silicon oxide film pattern 11A formed on one main surface 2a of the semiconductor substrate 2 is a pattern (for forming mesa grooves) for forming a mesa groove 7 (see FIG. 5) on one main surface 2a of the semiconductor substrate 2. Pattern). That is, the silicon oxide film pattern 11A is formed so as to expose only a region where the mesa groove 7 is to be formed in one main surface 2a.

  On the other hand, the silicon oxide film pattern 12A formed on the other main surface 2b of the semiconductor substrate 2 is used for cutting when the semiconductor substrate 2 is cut and divided into element units (see FIG. 1) in a cutting process described later. It is a pattern (pattern for cutting guides) for functioning as a guideline. More specifically, the silicon oxide film pattern 12 </ b> A is formed at a position overlapping the region where the mesa groove 7 is to be formed in the other main surface 2 b of the semiconductor substrate 2 in the thickness direction of the semiconductor substrate 2. The other main surface 2b of the substrate 2 is partitioned into a plurality of regions. The silicon oxide film pattern 12A becomes the silicon oxide film 9 in the mesa diode 1 shown in FIG.

After the oxide film forming step, as shown in FIG. 5, a plurality of mesa grooves 7 are formed on one main surface 2a of the semiconductor substrate 2 at intervals, and one main surface 2a is formed by the plurality of mesa grooves 7. Is divided into a plurality of regions (mesa groove forming step).
In this step, the semiconductor substrate 2 is subjected to an arbitrary etching method such as dry etching or wet etching using the silicon oxide film pattern 11A and the resist pattern 13A laminated on one main surface 2a of the semiconductor substrate 2 as a mask. A plurality of mesa grooves 7 are formed on one main surface 2a.

In this step, the mesa groove 7 is formed to be recessed from one main surface 2a of the semiconductor substrate 2, and is deeper than the junction interface (PN junction interface) between the n-type semiconductor layer 21 and the p-type semiconductor layer 22. Formed to be. That is, in the state after the above process, the PN junction interface is exposed on the inner surface of the mesa groove 7.
The mesa groove 7 formed as described above forms an outer peripheral edge of one main surface 2a of the semiconductor substrate 2 (see FIG. 1) divided into element units. That is, the mesa groove 7 is formed to overlap the silicon oxide film pattern 12A on the other main surface 2b of the semiconductor substrate 2 in the thickness direction of the semiconductor substrate 2.
In the present embodiment, the resist patterns 13A and 14A are removed after the mesa groove forming step as shown in FIG. 6, but may be removed, for example, before the mesa groove forming step or after the surface stabilization processing step described later.

Thereafter, as shown in FIG. 6, a passivation film 8 made of glass, resin, or the like is deposited on the inner surface of the mesa groove 7 (surface treatment step). In this step, the passivation film 8 is formed on the inner surface of the mesa groove 7 so that the thickness thereof is substantially uniform. Therefore, the hollow shape of the mesa groove 7 is maintained even after the surface treatment process. In the illustrated example, the passivation film 8 is formed not only on the entire inner surface of the mesa groove 7 but also on the peripheral edge of the opening of the mesa groove 7 in one main surface 2 a of the semiconductor substrate 2. What is necessary is just to form so that the PN junction interface exposed to an inner surface may be covered.
Then, after this surface treatment step, the silicon oxide film pattern 11A is removed by sandblasting or the like.

Thereafter, as shown in FIG. 7, the semiconductor substrate 2 and the metal sheet 31 are alternately stacked to form a stacked body 30 (sheet placement step). That is, the stacked body 30 is configured such that the metal sheet 31 is disposed on any main surface 2a, 2b of the semiconductor substrate 2.
The stacked body 30 is preferably configured by stacking a plurality of semiconductor substrates 2.
The metal sheet 31 is formed in advance before performing the sheet arranging step, and one containing nickel of 50 wt% or more and 100 wt% or less is used.
Among the metal sheets 31, the thickness T1 of the metal sheet 31a disposed on the outer surface of the stacked body 30 and disposed only on one main surface 2a of the semiconductor substrate 2 is a passivation film protruding from the one main surface 2a. It is set to be thicker than the height dimension H1 of 8. Among the metal sheets 31, the thickness T2 of the metal sheet 31b disposed on the outer surface of the stacked body 30 and disposed only on the other main surface 2b of the semiconductor substrate 2 is greater than the thickness H2 of the silicon oxide film pattern 12A. It is set thick. Among the metal sheets 31, the thickness T3 of the metal sheet 31c sandwiched between the semiconductor substrates 2 is set to be thicker than the sum of the height dimension H1 of the passivation film 8 and the thickness H2 of the silicon oxide film pattern 12A.
Forming the stacked body 30 in this manner can be suitably used when manufacturing a semiconductor element having metal layers such as electrodes on both main surfaces.

After the sheet placement step, as shown in FIG. 8, the semiconductor substrate 2 and the metal sheet 31 constituting the stacked body 30 are annealed, so that the p-type semiconductor layer 22 and the high-concentration n-type semiconductor layer 24 of the semiconductor substrate 2 Then, nickel silicide layers 23 and 25 are formed at the junction with the metal sheet 31 (annealing step).
In this step, it is preferable to arrange the stacked body 30 so that the thickness direction of the semiconductor substrate 2 is substantially parallel to the vertical direction. By disposing the stacked body 30 in this way, the metal sheet 31 can be brought into close contact with the main surfaces 2a and 2b of the semiconductor substrate 2 by utilizing gravity acting on the semiconductor substrate 2.
The annealing conditions can be set as appropriate. For example, the laminate 30 is placed in a furnace at 600 ° C. for 30 minutes and then air-cooled.

Following the annealing step, portions of the metal sheet 31 that have not become the nickel silicide layers 23 and 25 are removed to expose the nickel silicide layers 23 and 25 (sheet removal step). For removal of the metal sheet 31, a nitric acid boil treatment or the like can be used.
Thereafter, as shown in FIG. 9, nickel layers 3 and 4 are formed on the nickel silicide layers 23 and 25 (metal layer forming step). The nickel layers 3 and 4 can be formed by an electroless plating method or the like.

After this metal layer forming step, solder layers 5 and 6 are formed on the nickel layers 3 and 4, respectively, as shown in FIG. 10 (solder layer forming step).
The solder layers 5 and 6 can be formed by a method such as screen printing.

Subsequent to the solder layer forming step, as shown in FIG. 11, the semiconductor substrate 2 is cut so as to pass through the bottom of the mesa groove 7 and the insulating film pattern 12A, and the semiconductor substrate 2 is divided into element units. Thus, the mesa diode 1 is obtained.
In this cutting step, for example, using the insulating film pattern 12A formed on the other main surface 2b of the semiconductor substrate 2 as a guideline, the laser is directed from the other main surface 2b side of the semiconductor substrate 2 toward the bottom of the mesa groove 7. Cut (laser scribe), dicing, or the like may be performed.
In the cutting process, only laser cutting or dicing may be performed, but for example, after cutting a groove that does not reach the bottom of the mesa groove 7 on the other main surface 2b side by laser cutting or dicing, braking is performed. You may implement.
The mesa diode 1 is manufactured by the steps described so far.

As described above, according to the manufacturing method of the present embodiment, in the sheet arranging process, the metal sheet 31 formed in advance is arranged on both main surfaces 2a and 2b of the semiconductor substrate 2 and annealed to thereby obtain nickel silicide. Layers 23 and 25 are formed. For this reason, the nickel silicide layers 23 and 25 can be formed on the semiconductor substrate 2 without using a conventional plating method using a large amount of chemical solution.
Further, by using the metal sheet 31, the thickness of the metal covering the main surfaces 2a, 2b of the semiconductor substrate 2 becomes equal, and the thicknesses of the nickel silicide layers 23, 25 can be easily made uniform.

By annealing the metal sheet 31 in close contact with the semiconductor substrate 2 in the annealing process, the gap between the semiconductor substrate 2 and the metal sheet 31 is reduced, and the nickel silicide layers 23 and 25 can be formed more stably. .
Since the thickness T1 of the metal sheet 31a is thicker than the height dimension H1 of the passivation film 8, the metal sheet 31a disposed on the passivation film 8 in the sheet placement process is damaged by the passivation film 8 and is torn. Therefore, the nickel silicide layer 23 can be more reliably formed.
By setting the thickness T2 of the metal sheet 31b and the thickness T3 of the metal sheet 31c as described above, the metal sheet 31b is prevented from being damaged by the silicon oxide film pattern 12A, and the metal sheet 31c is protected from the passivation film 8. In addition, the silicon oxide film pattern 12A can be prevented from being damaged.

In the sheet arranging step, the semiconductor substrate 2 and the metal sheet 31 are alternately stacked to form the stacked body 30, so that the nickel silicide layers 23 and 25 are simultaneously formed on the plurality of semiconductor substrates 2. The manufacturing efficiency of the diode 1 can be increased. In addition, the plurality of mesa diodes 1 can be manufactured more compactly than in the case where the nickel silicide layers 23 and 25 are formed on the semiconductor substrate 2 separated one by one.
Since the metal sheet 31 contains 50 wt% or more and 100 wt% or less of nickel, it is possible to increase the purity of nickel in the nickel silicide layers 23 and 25 and to be surely electrically connected to the outside through the nickel silicide layers 23 and 25. it can. Therefore, the electrical characteristics of the mesa diode 1 can be improved.
By forming the nickel layers 3 and 4 by the sheet removing step and the metal layer forming step, the connection strength between the solder layer 5 and the nickel silicide layer 23 formed on the nickel layer 3 and the nickel layer 4 are formed. The connection strength between the solder layer 6 and the nickel / silicide layer 25 can be increased.

As mentioned above, although one Embodiment of this invention was explained in full detail with reference to drawings, the concrete structure is not restricted to this Embodiment, The change of the structure of the range which does not deviate from the summary of this invention is included. .
For example, in the above-described embodiment, in the annealing step, the outer surface of the stacked body 30 may be annealed while being pressed in the thickness direction of the semiconductor substrate 2 with a gripping device or the like. By doing in this way, the adhesiveness of main surface 2a, 2b of the semiconductor substrate 2 and the metal sheet 31 can further be improved.

In the sheet arranging step, the metal sheet 31 may be brought into close contact with the main surfaces 2a and 2b of the single semiconductor substrate 2, and the semiconductor substrate 2 and the metal sheet 31 may be annealed in the subsequent annealing step.
Although the metal sheet contains 50 wt% or more of nickel, it may contain 50 wt% or more of chromium, silver, or the like.
Although the semiconductor element is a mesa diode, the present invention is not limited to this, and the present invention can be applied to a thyristor or a planar semiconductor element.

1 Mesa diode (semiconductor element)
2 Semiconductor substrate 2a One main surface 3, 4 Nickel layer 7 Mesa groove 8 Passivation film 23, 25 Nickel silicide layer (alloy layer)
31 Metal sheet H1 Height dimension T1 Thickness

Claims (5)

A sheet placement step of placing a metal sheet on one main surface of the semiconductor substrate;
Annealing step of annealing the semiconductor substrate and the metal sheet to form an alloy layer at the joint between the semiconductor substrate and the metal sheet;
Bei to give a,
In the sheet arranging step, the semiconductor substrate and the metal sheet are alternately laminated .   The method of manufacturing a semiconductor element according to claim 1, wherein in the annealing step, annealing is performed while the metal sheet is in close contact with the semiconductor substrate. A passivation film is formed in a mesa groove formed on one main surface of the semiconductor substrate;
3. The method of manufacturing a semiconductor element according to claim 1, wherein a thickness of the metal sheet is thicker than a height dimension of the passivation film protruding from the one main surface. The said metal sheet contains nickel 50wt% or more and 100wt% or less, The manufacturing method of the semiconductor element as described in any one of Claim 1 to 3 characterized by the above-mentioned. After the annealing step, a sheet removing step of exposing the alloy layer by removing a portion that did not become the alloy layer in the metal sheet;
A metal layer forming step of forming a nickel layer on the alloy layer;
The method of manufacturing a semiconductor device according to claim 4 , comprising:

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