JP5933280B2 - Method for manufacturing mesa type semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a mesa semiconductor device.

Conventionally, in a mesa type semiconductor element such as a diode, a bipolar transistor, or a thyristor, an electrode layer is formed on both main surfaces of a semiconductor substrate as in Patent Document 1, for example, and the outer periphery of one main surface of the semiconductor substrate is further formed. Some have mesa grooves.
When manufacturing such a mesa type semiconductor element, one main surface is partitioned into a plurality of regions by forming a plurality of mesa grooves on one main surface of a semiconductor substrate (semiconductor wafer), An electrode layer is formed on a plurality of regions of the main surface and on the other main surface. Thereafter, a solder layer is formed on each electrode layer, and finally, the semiconductor substrate is cut at the bottom of the mesa groove, whereby a plurality of mesa semiconductor elements can be obtained simultaneously.
Conventionally, in the step of forming a solder layer, a solder paste is applied to the entire main surfaces of the semiconductor substrate by screen printing, and then a reflow process is performed. In particular, on one main surface of the semiconductor substrate, the solder paste is collectively applied to the plurality of electrode layers formed in the plurality of regions.

JP-A-6-204232

However, when solder paste is applied to one main surface of a semiconductor substrate by screen printing, the thickness of the solder paste on the electrode layer becomes non-uniform due to the large unevenness of one main surface due to the mesa groove. As a result, the thickness of the solder layer obtained after reflow may be non-uniform.
Further, when the solder paste is printed on the main surface of the semiconductor substrate by screen printing, the semiconductor substrate is pressed by a squeegee or the like, and local stress is generated in the semiconductor substrate. For this reason, the semiconductor substrate is likely to be cracked or chipped, resulting in a decrease in the yield of products (mesa type semiconductor elements). Note that cracks and chips in the semiconductor substrate that occur during printing of the solder paste are mainly due to the formation of mesa grooves and the thinness of the semiconductor substrate.

  The present invention has been made in view of the above-described circumstances, and can easily make the thickness of the solder layer uniform in the mesa type semiconductor element and also improve the yield of the mesa type semiconductor element to be manufactured. An object of the present invention is to provide a method for manufacturing a mesa type semiconductor device capable of performing the above.

In order to solve this problem, a method for manufacturing a mesa semiconductor device according to the present invention includes forming a plurality of mesa grooves at intervals on one main surface of a semiconductor substrate, and the plurality of mesa grooves form the one mesa groove. A mesa groove forming step for dividing the main surface into a plurality of regions, an electrode layer forming step for forming a first electrode layer in each of the plurality of regions on the one main surface, and a plurality of the electrode layers after the electrode layer forming step A solder layer forming step of forming a solder layer on the first electrode layer, and in the solder layer forming step, a solder sheet is formed on the one main surface so as to cover the plurality of first electrode layers at once. After the mounting, the reflow process is performed to melt the solder sheet to form the solder layers on the plurality of first electrode layers, respectively , and among the other main surfaces of the semiconductor substrate, A plurality of mesa grooves and the semiconductor substrate Forming a silicon oxide film at a position overlapping in the thickness direction and partitioning the other main surface into a plurality of regions, and in the electrode layer forming step, the plurality of the main surfaces on the other main surface A second electrode layer is formed in each region, and in the solder layer forming step, a reflow process is performed after placing a solder sheet on the other main surface so as to collectively cover the plurality of second electrode layers. And the solder sheet is melted to form the solder layers on the plurality of second electrode layers, respectively .

According to this manufacturing method, even if a large unevenness is generated on one main surface or the other main surface of the semiconductor substrate by the mesa groove or the silicon oxide film, the entire thickness is uniform in the solder layer forming step. Since the solder sheet can be attached to a plurality of electrode layers, the thickness of the solder layer obtained after the reflow process can be easily made uniform.
In addition, since the solder sheet is placed in the solder layer forming step, the stress applied to the semiconductor substrate can be reduced as compared with the case where the solder paste is applied by screen printing as in the prior art. Therefore, it is possible to suppress the occurrence of cracks and chips in the semiconductor substrate and improve the yield of the mesa type semiconductor element to be manufactured.

Furthermore, in the solder layer forming step, it is only necessary to place a solder sheet having a predetermined thickness, so that the thickness of the solder layer obtained after the reflow process can be easily adjusted only by changing the thickness of the solder sheet. It becomes possible.
Also, in the solder layer forming step, the solder layer can be obtained simply by performing a reflow process after covering all the electrode layers formed on both main surfaces of the semiconductor substrate with a solder sheet. Compared with the case where the solder paste is sequentially applied to both main surfaces by screen printing, it is possible to improve the manufacturing efficiency of the mesa type semiconductor element.

  According to the present invention, the thickness of the solder layer in the mesa semiconductor element after manufacture can be easily made uniform, and the yield of the mesa semiconductor element to be manufactured can be improved. In addition, it is possible to easily adjust the thickness of the solder layer obtained after the reflow process simply by changing the thickness of the solder sheet.

It is a schematic sectional drawing which shows the semiconductor element manufactured by the manufacturing method which concerns on one Embodiment of this invention. It is a schematic sectional drawing which shows the state after a diffusion process in the manufacturing method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing which shows an oxide film formation process in the manufacturing method of the semiconductor element which concerns on one Embodiment of this invention. In the manufacturing method of the semiconductor device concerning one embodiment of the present invention, it is a schematic sectional view showing the state after a mesa groove formation process. It is a schematic sectional drawing which shows the state after a surface treatment process in the manufacturing method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing which shows the state after an electrode layer formation process in the manufacturing method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing which shows a solder layer formation process in the manufacturing method of the semiconductor element which concerns on one Embodiment of this invention. It is a schematic sectional drawing which shows the state after a cutting process in the manufacturing method of the semiconductor element which concerns on one Embodiment of this invention.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
As shown in FIG. 1, the mesa semiconductor device 1 according to this embodiment is a mesa diode, and includes a semiconductor substrate 2 and electrode layers 3 and 4 formed on both main surfaces 2 a and 2 b of the semiconductor substrate 2. And solder layers 5 and 6.
The semiconductor substrate 2 has a first conductivity type (for example, n-type) semiconductor layer 21 (hereinafter referred to as an n-type semiconductor layer 21) opposite to the first conductivity type that forms one main surface 2 a of the semiconductor substrate 2. A second conductive type (for example, p-type) semiconductor layer 22 (hereinafter referred to as p-type semiconductor layer 22) and the other main surface 2b, and having a higher impurity concentration than the n-type semiconductor layer 21. It is configured so as to be sandwiched by a type semiconductor layer 23 (hereinafter referred to as a high concentration n-type semiconductor layer 23).

The impurity concentration of the n-type semiconductor layer 21 is, for example, 2 × 10 ¹⁴ atoms / cm ³ , and the impurity concentration of the p-type semiconductor layer 22 is, for example, 1 × 10 ¹⁹ atoms / cm ³ . Further, the high-concentration n-type semiconductor layer 23 is higher than the n-type semiconductor layer 21 and is, for example, 1 × 10 ¹⁹ atoms / cm ³ .
The semiconductor substrate 2 is formed, for example, in a rectangular shape in plan view, and a mesa groove 7 is formed on the outer peripheral edge of one main surface 2a thereof. The surface (inner surface) of the mesa groove 7 is curved and inclined in a concave shape from one main surface 2a of the semiconductor substrate 2 toward the side surface 2c. The junction interface (PN junction interface) between the n-type semiconductor layer 21 and the p-type semiconductor layer 22 is exposed on the surface of the mesa groove 7. In other words, the mesa groove 7 is formed deeper than the PN junction interface.

The surface of the mesa groove 7 is covered with a passivation film 8 made of glass or resin. The thickness of the passivation film 8 is substantially uniform. In the present embodiment, the passivation film 8 extends to the one main surface 2a of the semiconductor substrate 2 and covers the outer peripheral edge region of the one main surface 2a. In other words, the first electrode layer 3 and the solder layer 5 formed so as to overlap one main surface 2 a of the semiconductor substrate 2 are surrounded by the passivation film 8.
Further, a silicon oxide film 9 is formed in the outer peripheral edge region of the other main surface 2 b of the semiconductor substrate 2. Therefore, the second electrode layer 4 and the solder layer 6 formed to overlap the other main surface 2 b of the semiconductor substrate 2 are surrounded by the silicon oxide film 9.

Each electrode layer 3, 4 is configured by, for example, sequentially laminating a nickel silicide film (Ni—Si film) and a nickel plating layer on each main surface 2 a, 2 b of the semiconductor substrate 2.
In the illustrated example, the thicknesses of the electrode layers 3 and 4 are set to be larger than the thicknesses of the passivation film 8 and the silicon oxide film 9 on the main surfaces 2a and 2b of the semiconductor substrate 2, but for example, the passivation film 8 Alternatively, it may be set equal to or smaller than the silicon oxide film 9. However, the total thickness of the electrode layers 3 and 4 and the solder layers 5 and 6 is preferably set larger than the thickness of the passivation film 8 and the silicon oxide film 9.

Next, an example of a method for manufacturing the mesa semiconductor element 1 having the above configuration will be described.
When the mesa semiconductor element 1 is manufactured, first, as shown in FIG. 2, one main surface 2a of the first conductive type (for example, n type) semiconductor substrate 2 is opposite to the first conductive type. A second conductivity type semiconductor layer 22 (p-type semiconductor layer 22) is formed by diffusing impurities of the second conductivity type (for example, p-type) (diffusion process). Further, in the diffusion process of the present embodiment, the first conductivity type having a higher impurity concentration than the semiconductor substrate 2 is obtained by diffusing an impurity of the first conductivity type (n-type) into the other main surface 2 b of the semiconductor substrate 2. Semiconductor layer 23 (high-concentration n-type semiconductor layer 23) is formed.
Therefore, the semiconductor substrate 2 after the diffusion process includes the same n-type semiconductor layer 21 as the semiconductor substrate 2 before the process, the p-type semiconductor layer 22 that forms one main surface 2a of the semiconductor substrate 2, and the other main surface 2b. The high-concentration n-type semiconductor layer 23 is configured so as to be sandwiched between them.

After the diffusion step, as shown in FIG. 3, patterned silicon oxide films 11 and 12 are formed on both main surfaces 2a and 2b of the semiconductor substrate 2 by using a photolithography method (oxide film forming step). .
In this step, first, as shown in FIG. 3A, silicon oxide films 11 and 12 are respectively formed on both main surfaces 2a and 2b of the semiconductor substrate 2, and then on the silicon oxide films 11 and 12, respectively. Then, resists 13 and 14 made of photosensitive resin are applied. Thereafter, as shown in FIG. 3B, predetermined patterns are formed on the resists 13 and 14 by exposure and development. The pattern formed on each resist 13 and 14 is the same as the pattern to be formed on each silicon oxide film 11 and 12. Then, by using the patterned resists 13 and 14 as a mask, the silicon oxide films 11 and 12 are etched to form a predetermined pattern on the silicon oxide films 11 and 12. The etching may be any etching such as dry etching or wet etching.

  The patterns of the silicon oxide films 11 and 12 formed as described above will be described in detail. The pattern of the first silicon oxide film 11 formed on one main surface 2a of the semiconductor substrate 2 is a pattern (mesa groove) for forming a mesa groove 7 (see FIG. 4) on one main surface 2a of the semiconductor substrate 2. Forming pattern). That is, the first silicon oxide film 11 is formed so as to expose only a region where the mesa groove 7 is to be formed in one main surface 2a.

  On the other hand, when the pattern of the second silicon oxide film 12 formed on the other main surface 2b of the semiconductor substrate 2 is divided into element units (see FIG. 1) by cutting the semiconductor substrate 2 in a cutting process described later. It is a pattern (pattern for cutting guides) for functioning as a guideline for cutting. More specifically, the second silicon oxide film 12 is formed on the other main surface 2b of the semiconductor substrate 2 at a position overlapping with a region where the mesa groove 7 is to be formed in the thickness direction of the semiconductor substrate 2, The other main surface 2b of the semiconductor substrate 2 is partitioned into a plurality of regions. The second silicon oxide film 12 becomes the silicon oxide film 9 in the mesa semiconductor element 1 shown in FIG.

After the oxide film forming step, a plurality of mesa grooves 7 are formed on one main surface 2a of the semiconductor substrate 2 at intervals, and the one main surface 2a is partitioned into a plurality of regions by the plurality of mesa grooves 7. (Mesa groove forming step).
In this step, by using the first silicon oxide film 11 and the resist 13 laminated on one main surface 2a of the semiconductor substrate 2 as a mask, an arbitrary etching method such as dry etching or wet etching is performed, whereby the semiconductor substrate 2 A plurality of mesa grooves 7 are formed on one main surface 2a.

In this step, the mesa groove 7 is formed to be recessed from one main surface 2a of the semiconductor substrate 2, and is deeper than the junction interface (PN junction interface) between the n-type semiconductor layer 21 and the p-type semiconductor layer 22. Formed to be. That is, in the state after the above process, the PN junction interface is exposed on the inner surface of the mesa groove 7.
The mesa groove 7 formed as described above forms an outer peripheral edge of one main surface 2a of the semiconductor substrate 2 (see FIG. 1) divided into element units. That is, the mesa groove 7 is formed so as to overlap the second silicon oxide film 12 on the other main surface 2 b of the semiconductor substrate 2 in the thickness direction of the semiconductor substrate 2.
In the present embodiment, the resists 13 and 14 are removed after the mesa groove forming step as shown in FIG. 5, but may be removed before the mesa groove forming step or after a surface stabilization treatment step described later.

Thereafter, as shown in FIG. 5, a passivation film 8 made of glass, resin, or the like is deposited on the inner surface of the mesa groove 7 (surface treatment step). In this step, the passivation film 8 is formed on the inner surface of the mesa groove 7 so that the thickness thereof is substantially uniform. Therefore, the hollow shape of the mesa groove 7 is maintained even after the surface treatment process. In the illustrated example, the passivation film 8 is formed not only on the entire inner surface of the mesa groove 7 but also on the peripheral edge of the opening of the mesa groove 7 in one main surface 2 a of the semiconductor substrate 2. What is necessary is just to form so that the PN junction interface exposed to an inner surface may be covered.
Then, after the surface treatment process, the first silicon oxide film 11 is removed.

  Thereafter, as shown in FIG. 6, the first electrode layer 3 is formed in each of the plurality of regions of the one main surface 2 a of the semiconductor substrate 2 defined by the mesa groove 7, and is partitioned by the second silicon oxide film 12. The second electrode layer 4 is formed in each of the plurality of regions of the other main surface 2b (electrode layer forming step). These electrode layers 3 and 4 can be formed by performing various plating methods, annealing treatments, sintering treatments, and the like.

For example, when each of the electrode layers 3 and 4 is composed of a nickel silicide film and a nickel plating layer as described above, in the electrode layer forming step, first, both main surfaces 2a, 2a, A primary nickel plating layer is formed on 2b. Next, by performing an annealing process, the semiconductor substrate 2 and the primary nickel plating layer react to form a nickel silicide film in an interface region between the semiconductor substrate 2 and the primary nickel plating layer. In addition, after completion | finish of annealing, a nitric acid boil process etc. are implemented and an unnecessary primary nickel plating layer is removed.
Then, the formation of the electrode layers 3 and 4 is completed by forming a secondary nickel plating layer on each nickel silicide film by plating. The secondary nickel plating layer described above corresponds to the nickel plating layer in each of the electrode layers 3 and 4.

After this electrode layer forming step, as shown in FIG. 7, solder layers 5 and 6 are formed on the plurality of first electrode layers 3 and second electrode layers 4, respectively (solder layer forming step).
In this step, first, as shown in FIG. 7A, a semiconductor is formed so as to cover a plurality of first electrode layers 3 in a lump and to cover a plurality of second electrode layers 4 in a lump. Solder sheets 15 and 16 are placed on the entire main surfaces 2a and 2b of the substrate 2, respectively. Specific examples of the solder sheets 15 and 16 used here include, for example, a solder paste formed in a sheet shape having a predetermined thickness, or a solder paste coated with a predetermined thickness on a release film. When the solder sheets 15 and 16 are provided with a release film, the solder sheets 15 and 16 are arranged on the main surfaces 2a of the semiconductor substrate 2 so that the solder paste faces the main surfaces 2a and 2b of the semiconductor substrate 2. , 2b. Further, after the solder sheets 15 and 16 are placed, the release film may be peeled off from the solder paste.

Then, after the solder sheets 15 and 16 are placed, a reflow process is performed to melt the solder sheets 15 and 16, so that the solder layers 5 and 6 have a plurality of first electrodes as shown in FIG. 7B. It will be formed on the layer 3 and the second electrode layer 4, respectively.
In the state before the reflow process, the solder sheets 15 and 16 also cover the passivation film 8 and the second silicon oxide film 12, but the passivation film 8 and the second silicon oxide film 12 are soldered more than the electrode layers 3 and 4. Since the wettability is low, molten solder is not formed on the passivation film 8 or the second silicon oxide film 12 during the reflow process. In other words, the electrode layers 3 and 4 adjacent to each other on the same main surface 2a and 2b are not connected by the solder layers 5 and 6.

Finally, as shown in FIG. 8, the semiconductor substrate 2 is cut so as to pass through the bottom of the mesa groove 7 and the second silicon oxide film 12, and the semiconductor substrate 2 is divided into element units. A mesa semiconductor device 1 is obtained.
In this cutting step, for example, the second silicon oxide film 12 formed on the other main surface 2b of the semiconductor substrate 2 is used as a guideline from the other main surface 2b side of the semiconductor substrate 2 toward the bottom of the mesa groove 7. Laser cutting (laser scribing), dicing, or the like may be performed.
In the cutting process, only laser cutting or dicing may be performed, but for example, after cutting a groove that does not reach the bottom of the mesa groove 7 on the other main surface 2b side by laser cutting or dicing, braking is performed. You may implement.

According to the manufacturing method of the present embodiment, even if large irregularities are formed on both the main surfaces 2a and 2b of the semiconductor substrate 2 by the mesa groove 7 and the second silicon oxide film 12, the entire thickness is reduced in the solder layer forming step. Can be attached to the plurality of electrode layers 3, 4, so that the thickness of the solder layers 5, 6 obtained after the reflow process can be easily made uniform. Become.
In addition, since the solder sheets 15 and 16 are placed in the solder layer forming step, the stress applied to the semiconductor substrate 2 can be reduced as compared with the case where the solder paste is applied by screen printing as in the prior art. Therefore, the yield of the mesa semiconductor device 1 to be manufactured can be improved by suppressing the occurrence of cracks and chips in the semiconductor substrate 2.

Furthermore, in the solder layer forming step, it is only necessary to place the solder sheets 15 and 16 having predetermined thicknesses. Therefore, the solder layers 5 and 6 obtained after the reflow process can be simply changed by changing the thickness of the solder sheets 15 and 16. It is also possible to easily adjust the thickness.
Further, in the solder layer forming step, all the electrode layers 3 and 4 formed on the two main surfaces 2a and 2b of the semiconductor substrate 2 are collectively covered with the solder sheets 15 and 16, and then the solder layer is simply applied by reflow treatment. 5 and 6 are obtained, it is possible to improve the manufacturing efficiency of the mesa semiconductor element 1 as compared with the case where the solder paste is sequentially applied to both the main surfaces 2a and 2b by screen printing as in the prior art. It is.

Although the details of the present invention have been described above by the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.
For example, in the diffusion step, the impurities are not limited to be diffused into both the main surfaces 2a and 2b of the semiconductor substrate 2, but at least one of the main surfaces 2a and 2b of the first conductivity type semiconductor substrate 2 is It is sufficient that the second conductivity type impurity is diffused. In other words, the semiconductor substrate 2 after the diffusion step only needs to be configured by laminating at least a first conductivity type semiconductor layer and a second conductivity type semiconductor layer so that the mesa semiconductor element 1 can be manufactured. .

In the oxide film forming step, the second silicon oxide film 12 patterned for the cutting guide is formed on the other main surface 2b of the semiconductor substrate 2, but at least one main surface of the semiconductor substrate 2 is formed. The first silicon oxide film 11 patterned for forming the mesa groove may be formed on the surface 2a. In the case where the second silicon oxide film 12 is not formed, for example, in the electrode forming step, the second electrode layer 4 is formed all over the other main surface 2b of the semiconductor substrate 2 and then as in the above embodiment. In addition, the second electrode layer 4 is patterned by the same photolithography method as in the above embodiment so that the second electrode layer 4 remains only in a plurality of partitioned areas of the other main surface 2b of the semiconductor substrate 2. do it. If the second electrode layer 4 is formed in this way, it is possible to perform the same solder layer forming step as in the above embodiment.
The manufacturing method of the present invention is not limited to the order of steps as in the above-described embodiment, and at least the mesa groove forming step, the electrode layer forming step, and the solder layer forming step may be performed in order. Presence / absence and order may be arbitrary.

DESCRIPTION OF SYMBOLS 1 Mesa type semiconductor element 2 Semiconductor substrate 2a One main surface 2b The other main surface 3 First electrode layer 4 Second electrode layers 5 and 6 Solder layer 7 Mesa groove 9 Silicon oxide film 12 Second silicon oxide films 15 and 16 Solder Sheet

Claims (1)

Forming a plurality of mesa grooves spaced apart from each other on one main surface of the semiconductor substrate, and dividing the one main surface into a plurality of regions by the plurality of mesa grooves; and
An electrode layer forming step of forming a first electrode layer in each of the plurality of regions on the one main surface;
A solder layer forming step of forming a solder layer on the plurality of first electrode layers after the electrode layer forming step,
In the solder layer forming step, a solder sheet is placed on the one main surface so as to collectively cover the plurality of first electrode layers, and then a reflow process is performed to melt the solder sheet. And forming each of the solder layers on the plurality of first electrode layers ,
further,
Forming an oxide film that forms a silicon oxide film at a position overlapping with the plurality of mesa grooves in the thickness direction of the semiconductor substrate in the other main surface of the semiconductor substrate, and divides the other main surface into a plurality of regions With a process,
In the electrode layer forming step, a second electrode layer is formed in each of the plurality of regions on the other main surface,
In the solder layer forming step, a solder sheet is placed on the other main surface so as to collectively cover the plurality of second electrode layers, and then a reflow process is performed to melt the solder sheet. The method for manufacturing a mesa semiconductor element , wherein the solder layer is formed on each of the plurality of second electrode layers .

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