GB1588183A - Arrangements for use in addressing mos stores - Google Patents

Arrangements for use in addressing mos stores Download PDF

Info

Publication number
GB1588183A
GB1588183A GB3806177A GB3806177A GB1588183A GB 1588183 A GB1588183 A GB 1588183A GB 3806177 A GB3806177 A GB 3806177A GB 3806177 A GB3806177 A GB 3806177A GB 1588183 A GB1588183 A GB 1588183A
Authority
GB
United Kingdom
Prior art keywords
transistors
decoder circuit
stage
decoder
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3806177A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Publication of GB1588183A publication Critical patent/GB1588183A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
GB3806177A 1976-09-15 1977-09-13 Arrangements for use in addressing mos stores Expired GB1588183A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2641524A DE2641524B1 (de) 1976-09-15 1976-09-15 Anordnung zur Adressierung eines MOS-Speichers

Publications (1)

Publication Number Publication Date
GB1588183A true GB1588183A (en) 1981-04-15

Family

ID=5987981

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3806177A Expired GB1588183A (en) 1976-09-15 1977-09-13 Arrangements for use in addressing mos stores

Country Status (4)

Country Link
JP (1) JPS6032279B2 (enrdf_load_stackoverflow)
DE (1) DE2641524B1 (enrdf_load_stackoverflow)
FR (1) FR2365179A1 (enrdf_load_stackoverflow)
GB (1) GB1588183A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2308703A (en) * 1995-12-29 1997-07-02 Hyundai Electronics Ind Word line driver in semiconductor memory device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6413289A (en) * 1988-05-06 1989-01-18 Nec Corp Decoder circuit
KR101412460B1 (ko) * 2012-05-21 2014-07-01 주식회사 뉴핫맥스 발열 코일의 처짐 방지 구조를 갖는 히터

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3902082A (en) * 1974-02-11 1975-08-26 Mostek Corp Dynamic data input latch and decoder

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2308703A (en) * 1995-12-29 1997-07-02 Hyundai Electronics Ind Word line driver in semiconductor memory device
GB2308703B (en) * 1995-12-29 2000-07-26 Hyundai Electronics Ind Word line driver in semiconductor memory device

Also Published As

Publication number Publication date
FR2365179A1 (fr) 1978-04-14
JPS6032279B2 (ja) 1985-07-26
DE2641524C2 (enrdf_load_stackoverflow) 1978-07-13
FR2365179B1 (enrdf_load_stackoverflow) 1983-05-13
JPS5336147A (en) 1978-04-04
DE2641524B1 (de) 1977-11-17

Similar Documents

Publication Publication Date Title
US4104735A (en) Arrangement for addressing a MOS store
EP0083482B1 (en) Improvements in logic circuit operation speed
US5751657A (en) Semiconductor memory device
US4849935A (en) Semiconductor memory including transparent latch circuits
KR100261558B1 (ko) 씨모스 디지탈 레벨 시프트 회로
JPS61113188A (ja) 改良されたアドレス・カウンタを有する半導体メモリ装置
EP0493092B1 (en) Level conversion circuit
US4514829A (en) Word line decoder and driver circuits for high density semiconductor memory
US4441171A (en) Monolithically integrated semiconductor memory
US4145622A (en) Decoder circuit arrangement with MOS transistors
US4063224A (en) Circuit for the production of read-out pulses
EP0262995B1 (en) Semiconductor memory device having an address transition detection circuit
US5097159A (en) Delay circuit for delaying an output signal relative to an input signal for a specified time interval
US4893281A (en) Semiconductor memory system with programmable address decoder
US4122547A (en) Complementary FET drivers for programmable memories
US4447892A (en) Pre-charge for the bit lines of a random access memory
EP0136229B1 (en) Sense amplifier
US4775990A (en) Serial-to-parallel converter
GB1588183A (en) Arrangements for use in addressing mos stores
US5218572A (en) Semiconductor memory device
US4592021A (en) Data readout circuit for an MOS transistor array
US5905452A (en) Current source cell apparatus for digital/analog converter
US4114192A (en) Semiconductor memory device to reduce parasitic output capacitance
GB2159359A (en) Semiconductor static memory device
US5557226A (en) Address transition detector circuit and method of driving same

Legal Events

Date Code Title Description
PS Patent sealed
PE20 Patent expired after termination of 20 years

Effective date: 19970912