GB1588183A - Arrangements for use in addressing mos stores - Google Patents
Arrangements for use in addressing mos stores Download PDFInfo
- Publication number
- GB1588183A GB1588183A GB3806177A GB3806177A GB1588183A GB 1588183 A GB1588183 A GB 1588183A GB 3806177 A GB3806177 A GB 3806177A GB 3806177 A GB3806177 A GB 3806177A GB 1588183 A GB1588183 A GB 1588183A
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- Prior art keywords
- transistors
- decoder circuit
- stage
- decoder
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- Expired
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4082—Address Buffers; level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
- H03K5/023—Shaping pulses by amplifying using field effect transistors
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Nonlinear Science (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
Description
(54) IMPROVEMENTS IN OR RELATING TO ARRANGEMENTS FOR
USE IN ADDRESSING MOS STORES
(71) We, SIEMENS AKTIENGESELL
SHAFT, a German Company, of Berlin and
Munich, Federal Republic of Germany, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to an arrangement for use in addressing an MOS store consisting of MOS transistor storage cells.
Arrangements for use in the addressing of
MOS stores consisting of MOS transistor storage cells are known. Usually the storage cells are arranged in the form of a matrix having word and bit lines, and a storage cell or a series of storage cells is addressed by selecting a word and a bit line by address signals which are fed to an addressing arrangement. The addressing arrangement contains buffer circuits which amplify, invert, and intermediately store in inverted and non-inverted form the incoming address signals. Outputs of the buffer circuits are connected to inputs of a decoder circuit, which in dependence upon the prevailing address signal combination selects one of the drive lines, i.e. a bit or word line, leading to the storage cells.
According to this invention there is provided an arrangement for use in addressing an MOS store consisting of MOS transistor storage cells, with the aid of n address signals, the arrangement comprising n buffer circuits, to each of which in use a respective one of the n address signals is supplied and each of which serves to produce at outputs thereof the respective address signal in inverted and non-inverted form, a first decoder circuit comprising y stages each of which has inputs connected to the outputs of a respective plurality of m of the buffer circuits and has 2m outputs and is arranged to produce a predetermined signal individually at each of its outputs in dependence upon the respective combination of the m address signals supplied in use to the m buffer circuits to which the stage is connected, n, m, and y being positive integers such that n > m and y is the quotient n/m, taken to the nearest integer below, and a second decoder circuit having 2n outputs, for connection each to a respective drive line of the store, and inputs connected to the outputs of the first decoder circuit and to any remaining buffer circuit outputs not connected to the inputs of the first decoder circuit, the second decoder circuit being arranged to produce a predetermined signal individually at each of its outputs in dependence upon the respective combination of signals supplied Vo its inputs and wherein each stage of the first decoder circuit comprises of 2m NAND gates, each of which comprises m charging transistors whose controlled paths are connected in parallel with one another and m discharge transistors whose controlled paths are connected in series with one another and in series with the controlled paths of the m charging transistors, the junction point between the parallel-connected and the series connected controlled paths constituting a respective output of the stage, and each stage of the first decoder circuit further comprises a control transistor whose controlled path is connected in series with the parallel-connected controlled paths of the charging transistors of all the NAND gates for controlling the supply of a fixed potential thereto, the control electrodes of the charging transistors of each NAND gate being connected in a respective combination each to an input of the stage which is connected to an output of a respective buffer circuit and the control electrodes of the discharge transistors of the same NAND gate being connected to the complementary signal inputs of the stage. Preferably, each stage of the first decoder circuit further comprises 2m coupling capacitors each connected between the connection point between the controlled paths of the control transistor and the charging transistors and a respective input of the stage. Expediently n = m.y.
Preferably the second decoder circuit comprises, in respect of each of its outputs, y + n -nLy logic elements each of which comprises a transistor having a control electrode connected to an input of the second decoder circuit, which inputs are connected to outputs of respective stages of the first decoder circuit or buffer circuits, and a controlled path connected between the respective output of the second decoder circuit and a point of fixed potential. Thus in the case in which n = m.y the second decoder circuit comprises y decoder transistors for each of the 2n outputs. The decoder transistors can be connected in known manner to an output stage which switches through a selector signal to a drive line when none of the decoder transistors is conductive.
The invention will be further understood frown the following description by way of example of an embodiment thereof with reference to the accompanying drawings, in which:
Fig. 1 schematically illustrates in the form of a block diagram an arrangement, for use in addressing an MOS store, comprising buffer circuits, a first decoder circuit having a plurality of stages, and a second decoder circuit;
Fig. 2 schematically illustrates a buffer buffer circuit;
Fig. 3 illustrates a pulse plan associated with the buffer circuit;
Fig. 4 schematically illustrates a stage of the first decoder circuit;
Fig. 5 schematically illustrates a stage of the first decoder circuit incorporating coupling capacitors;
Fig. 6 schematically illustrates the form of the second decoder circuit; and
Fig. 7 schematically illustrates an element employed in the second decoder circuit.
Fig. 1 illustrates an addressing arrangement which is responsive to n address signals AO to An supplied thereto to select any one of 2 drive lines XO to Xr (r = 2n - 1).
The arrangement consists of n buffer circuits
AVT, a first decoder circuit VD having y = nlm stages VDS1 to VDSy, and a second decoder circuit ND. Here n, m and y are positive whole numbers.
The address signals AO to An are supplied each to a respective one of the buffer circuits
AVT which inverts the address signal and intermediately stores the inverted and noninverted address signals and feeds these to one of the stages VDS of the first decoder circuit VD. As illustrated in Fig. 1, m = 2 address signals are each offered to each stage VDS in inverted and nori-inverted form, for example the stage VDS1 is supplied with the address signals AO, AO, A1, and Al. Each stage VDS has 2m output lines; thus in Fig. 1 where m = 2 each stage has 4 output lines, the stages VDS1 to
VDSy having respectively the output lines
ZOO to Z03, Z10 to Z13, and Zy0 to Zy3.
The output lines of each stage VDS of the first decoder circuit VD are connected to inputs of the second decoder circuit ND, in which these output lines are linked to the drive lines X0 to Xr, which lead to the storage cells of an MOS store to be addressed, in such manner that for each specific combination of address signals a respective drive line is selected.
Each buffer circuit AVT is for example as shown in Fig. 2 and consists of transistors M1 to M6. The controlled paths of the transistors M1, M3, and MS are connected in series with one another, and the controlled paths of the transistors M2, M4, and M6 are connected in series with one another, between fixed potentials VDD and VSS. The relevant address signal A is supplied to the gate of the transistor MS, and the gate of the transistor M6 is connected to the junction between the controlled paths of the transistors M3 and MS. The gates of the transistors M3 and M4 are connected together and are supplied with a transfer timing signal S, and the gates of the transistors M1 and M2 are connected together and are supplied with a pre-charging timing signal
SV. The output for the inverted address signal Av is connected to the junction between the controlled paths of the transistors M1 and M3, and the output for the non-inverted address signal Av is connected to the junction between the controlled paths of the transistors M2 and M4.
The operation of the buffer circuit illustrated in Fig. 2 is explained below with additional reference to Fig. 3. Initially the pre-charging timing signal SV is applied, so that the transistors M1 and M2 are conductive and the outputs Av and Av are charged to a voltage of approximately VDD-UT, and the transfer timing signal S is not present so that the transistors M3 and M4 are blocked. The pre-charging timing signal
SV is now terminated and the transfer timing signal S is applied, so that the transistors
M3 and M4 are rendered conductive and the transistors M1 and M2 are blocked. Accordingly one of the outputs Av and Av discharges, and the other does not discharge, in accordance with the address signal A supplied to the transistor MS. If, for example, the address signal A is such that the transistor MS is rendered conductive, the transistor M6 is blocked and only the output Av can discharge, via the transistors
M3 and MS. Following a transition period, stable conditions occur at the outputs Av and Av, at which the amplified address signal A appears in inverted and noninverted form, and the transfer timing signal
S is terminated. Expediently the outputs
Av and Av are connected to an output stage in which these address signals are intermediately stored. A circuit of this type is disclosed for example, inGerman Specification No. 2443 428.
The remainder of the description is based upon the assumption that the number of address signals A is n = 6, so that 28 = 64, and that m = 2 so that there are y = n/in = 3 stages VDS in the first decoder circuit VD each of which stages has 2m = 4 output lines.
Fig. 4 illustrates the form of the stage
VDS1 of the first decoder circuit VD, the other stages being the same but being supplied with different address signals. The stage VDS1 comprises four NAND gates
NG1 to NG4, having the outputs Z00 to Z03 respectively, each of which comprises two transistors, referred to hereinafter as discharge transistors, whose controlled paths are connected in series with one another and, in series therewith, a further two transistors, referred to hereinafter as charging transistors, whose controlled paths are connected in parallel with one another.
Thus the gate NGl consists of discharge transistors M17 and M21 and charging transistors M7 and M11, the gate NG2 consists of discharge transistors M15 and M22 and charging transistors M9 and M12, the gate NG3 consists of discharge transistors
M18 and M19 and charging transistors M8 and M13, and the gate MG4 consists of discharge transistors M16 and M20 and charging transistors M10 and M14. In each gate the connection point between the series and parallel-connected transistors forms the relevant output Z. The other ends of the series-connected discharge transistors are commonly supplied with the potential VSS, and the other ends of the parallel-connected charging transistors are commonly connected via the controlled path of a further transistor
M23, whose gate is supplied with the transfer timing signal S, to the potential VDD.
The gates of the discharge and charging transistors are supplied with the amplified address signals in inverted and non-inverted form, each NAND gate being supplied with a respective, combination of the address
signals. Thus in each NAND gate one of the charging transistors is supplied with the .address signal A0' or A0 and the other is supplied with the address signal Al or Al, -and the discharge transistors are supplied ;with the complementary address signals, i.e.
A0 or AO and Al or Al respectively. Thus for example in the NAND gate NG1 the charging transistors M7 and M11 are supplied with the address signals A0 and Al respectively, and the discharge transistors
M17 and M21 are supplied with the address signals A0 and Al respectively.
The operation of the stage VDS1 is as follows: Initially, before the signal S is present, as will be seen from Figs. 2 and 3 a high potential is present at the outputs Av and Av of each buffer circuit and hence at all the inputs of the stage VDS1. Consequently all of the discharge and charging transistors are rendered conductive, and as the transistor M23 is blocked the outputs
ZOO to Z03 all adopt approximately the potential VSS. When the transfer timing signal S is applied, the outputs of the buffer circuits and hence the inputs of the stage
VDS1 are set to potentials according to the relevant address signals AO and Al, and the transistor M23 is rendered conductive so that approximately the potential VDD is applied to the NAND gates NG1 to NG4.
The result of this is that, in dependence upon the prevailing address signal combination, three of the outputs ZOO to Z03 assume a high potential and the remaining one of these outputs remains at a low potential (approximately VSS).
For example in the presence of the address signals AO and Al the charging transistors M7 and M11 of the NAND gate
NG1, M12 of the NAND gate NG2, and
M8 of the NAND gate NG3 are conductive, whereas both the charging transistors M10 and M14 of the NAND gate NG4 are blocked, and the discharge transistors M17 and M21 of the NAND gate NG1, M22 of the NAND gate NG2, and M18 of the
NAND gate NG3 are blocked, whereas both the discharge transistors M16 and M20 of the NAND gate NG4 are conductive. Thus a high potential appears at the outputs Z00,
Z01 and Z02 and a low potential remains at the output Z03.
Fig. 4 illustrates the stage VDS1 for the
case m = 2 charging transistors and
m = 2 discharge transistors in respect
of each NAND gate. If m exceeds 2, the
number of charging transistors and the
number of discharge transistors in each
NAND gate is again m.
Fig. 5 shows a modification of the stage
illustrated in Fig. 5, in which coupling
capacitors CI( are provided each connected -between the point of connection of the
charging transistors to the transistor M23 and a respective one of the inputs. Thus the potential prevailing at the gates of the charging transistors is raised whenever the transfer -timing signal S is present. Fig. 9 also illus trates that the transistors M19 and M20, and likewise the transistors M21 and M22, can be constituted by a single transistor.
Otherwise the construction of the stage corresponds to that shown in Fig. 4.
Fig. 6 schematically illustrates one possible form of the second decoder circuit ND, but for simplicity, in addition to the output lines Z00 to Z03, Z10 to Z13, and Z20 to Z23 from the stages VDS1, VDS2, and VDS3 respectively of the first decoder circuit VD, only some of the drive lines XO to X63 which lead to the storage cells of the store to be addressed, and parts of the second decoder circuit associated with these drive lines, have been shown. Where a logic link is effected between an output line Z and a drive line X, a node K has been entered in Fig. 6. At this point there is arranged a logic element which is operated by a signal on the relevant output line Z to select the relevant drive line X accordingly. For example at each such node K there can be a logic element of the form shown in Fig. 7, this element comprising a decoder transistor
Dk whose gate is connected to the relevant output line Zik and whose controlled path is connected between the potential VSS and the relevant drive line Xl.
In Fig. 6, in accordance with the previously assumed figures, there are 3 groups each of four output lines Z which are linked to 64 drive lines X in such manner that each drive line X can be selected by means of the logic elements with a respective combination of signals on the output lines. In this case there are 43 possible combinations of signals on the output lines corresponding to the 64 drive lines X.
Thus each drive line X is linked via three logic elements (decoder transistors Dk) to three output lines, each of which output lines leads from a respective one of the three stages VDS1 to VDS3. The decoder transistors Dk as shown in Fig. 7 are connected in parallel in respect of each drive line X. The parallel arrangement of the decoder transistors Dk can also comprise an output stage which switches through a store selector signal in known manner to the drive line X. This will be the case when all the decoder transistors remain blocked during the operation by the address signals. Such an output stage is described in, for example,
German Specification No. 2,443 490.
It can be seen from Fig. 6 that the second decoder circuit ND requires only three decoder transistors Dk in respect of each drive line X.
Naturally it is also possible for n and m to have other values than those assumed in the above example, in which case different numbers of output lines from each stage of the first decoder circuit and stages of the first decoder circuit and a different linking of the output lines Z to the drive lines X will prevail.
If the selection of n and m is such that n cannot be divided by m without a remainder, the address signals corresponding to this remainder are fed not to the first decoder circuit VD but instead directly to the second decoder circuit ND, in inverted and non-inverted form. These address signals serve to control decoder transistors Dk as shown in Fig. 7 which, with the other decoder transistors which are selected by the output lines Z from the stages VDS1 to
VDSy, serve to select the relevant drive line
X for each combination of address signals.
WHAT WE CLAIM IS:- 1. An arrangement for use in addressing an MOS store consisting of MOS transistor storage cells, with the aid of n address signals, the arrangement comprising n buffer circuits, to each of which in use a respective one of the n address signals is supplied and each of which serves to produce at outputs thereof the respective address signal in inverted and non-inverted form, a first decoder circuit comprising y stages each of which has inputs connected to the outputs of a respective plurality of m of the buffer circuits and has 2m outputs and is arranged to produce a predetermined signal individually at each of its outputs in dependence upon the respective combination of the m address signals supplied in use to the m buffer circuits to which the stage is connected, n, m, and y being positive integers such that n > m and y is the quotient n/m, taken to the nearest integer below, and a second decoder circuit having 28 outputs, for connection each to a respective drive line of the store, and inputs connected to the outputs of the first decoder circuit and to any remaining buffer circuit outputs not connected to the inputs of the first decoder circuit, the second decoder circuit being arranged to produce a predetermined signal individually at each of its outputs in dependence upon the respective combination of signals supplied to its inputs, and wherein each stage of the first decoder circuit comprises 2m NAND gates, each of which comprises m charging transistors whose controlled paths are connected in parallel with one another and m discharge transistors whose controlled paths are connected in series with one another and in series with the controlled paths of the m charging transistors, the junction point between the parallel-connected and the series-connected controlled paths constituting a respective output of the stage, and each stage of the first decoder circuit further comprises a control transistor whose controlled path is connected in series with the parallel-connected controlled paths of the charging transistors
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (5)
1. An arrangement for use in addressing an MOS store consisting of MOS transistor storage cells, with the aid of n address signals, the arrangement comprising n buffer circuits, to each of which in use a respective one of the n address signals is supplied and each of which serves to produce at outputs thereof the respective address signal in inverted and non-inverted form, a first decoder circuit comprising y stages each of which has inputs connected to the outputs of a respective plurality of m of the buffer circuits and has 2m outputs and is arranged to produce a predetermined signal individually at each of its outputs in dependence upon the respective combination of the m address signals supplied in use to the m buffer circuits to which the stage is connected, n, m, and y being positive integers such that n > m and y is the quotient n/m, taken to the nearest integer below, and a second decoder circuit having 28 outputs, for connection each to a respective drive line of the store, and inputs connected to the outputs of the first decoder circuit and to any remaining buffer circuit outputs not connected to the inputs of the first decoder circuit, the second decoder circuit being arranged to produce a predetermined signal individually at each of its outputs in dependence upon the respective combination of signals supplied to its inputs, and wherein each stage of the first decoder circuit comprises 2m NAND gates, each of which comprises m charging transistors whose controlled paths are connected in parallel with one another and m discharge transistors whose controlled paths are connected in series with one another and in series with the controlled paths of the m charging transistors, the junction point between the parallel-connected and the series-connected controlled paths constituting a respective output of the stage, and each stage of the first decoder circuit further comprises a control transistor whose controlled path is connected in series with the parallel-connected controlled paths of the charging transistors
of all the NAND gates for controlling the supply of a fixed potential thereto, the control electrodes of the charging transistors of each NAND gate being connected in a respective combination each to an input of the stage which is connected to an output of a respective buffer circuit and the control electrodes of the discharge transistors of the same NAND gate being connected to the complementary signal inputs of the stage.
2. An arrangement as claimed in claim 1, wherein each stage of the first decoder circuit further comprises 2m coupling capacitors each connected between the connection point between the controlled paths of the control transistor and the charging transistors and a respective input of the stage.
3. An arrangement as claimed in claim 1 or 2 wherein n > m.y.
4. An arrangement as claimed in claim 1, 2 or 3 wherein the second decoder circuit comprises, in respect of each of its outputs, y + n-rn. y logic elements each of which comprises a transistor having a control electrode connected to an input of the second decoder circuit, which inputs are connected to outputs of respective stages of the first decoder circuit or buffer circuits, and a controlled path connected between the respective output of the second decoder circuit and a point of fixed potential.
5. An arrangement for use in addressing an MOS store substantially as herein described with reference to the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2641524A DE2641524B1 (en) | 1976-09-15 | 1976-09-15 | Arrangement for addressing a MOS memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1588183A true GB1588183A (en) | 1981-04-15 |
Family
ID=5987981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB3806177A Expired GB1588183A (en) | 1976-09-15 | 1977-09-13 | Arrangements for use in addressing mos stores |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS6032279B2 (en) |
| DE (1) | DE2641524B1 (en) |
| FR (1) | FR2365179A1 (en) |
| GB (1) | GB1588183A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2308703A (en) * | 1995-12-29 | 1997-07-02 | Hyundai Electronics Ind | Word line driver in semiconductor memory device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6413289A (en) * | 1988-05-06 | 1989-01-18 | Nec Corp | Decoder circuit |
| KR101412460B1 (en) * | 2012-05-21 | 2014-07-01 | 주식회사 뉴핫맥스 | Industrial oven heater |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3902082A (en) * | 1974-02-11 | 1975-08-26 | Mostek Corp | Dynamic data input latch and decoder |
-
1976
- 1976-09-15 DE DE2641524A patent/DE2641524B1/en active Granted
-
1977
- 1977-09-08 FR FR7727200A patent/FR2365179A1/en active Granted
- 1977-09-12 JP JP52109774A patent/JPS6032279B2/en not_active Expired
- 1977-09-13 GB GB3806177A patent/GB1588183A/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2308703A (en) * | 1995-12-29 | 1997-07-02 | Hyundai Electronics Ind | Word line driver in semiconductor memory device |
| GB2308703B (en) * | 1995-12-29 | 2000-07-26 | Hyundai Electronics Ind | Word line driver in semiconductor memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5336147A (en) | 1978-04-04 |
| FR2365179B1 (en) | 1983-05-13 |
| DE2641524C2 (en) | 1978-07-13 |
| JPS6032279B2 (en) | 1985-07-26 |
| DE2641524B1 (en) | 1977-11-17 |
| FR2365179A1 (en) | 1978-04-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| PE20 | Patent expired after termination of 20 years |
Effective date: 19970912 |