GB1505515A - Clock pulse compensation circuit - Google Patents
Clock pulse compensation circuitInfo
- Publication number
- GB1505515A GB1505515A GB22873/75A GB2287375A GB1505515A GB 1505515 A GB1505515 A GB 1505515A GB 22873/75 A GB22873/75 A GB 22873/75A GB 2287375 A GB2287375 A GB 2287375A GB 1505515 A GB1505515 A GB 1505515A
- Authority
- GB
- United Kingdom
- Prior art keywords
- signal
- pulses
- data
- signals
- oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005540 biological transmission Effects 0.000 abstract 1
- 230000003247 decreasing effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US05/514,982 US3950658A (en) | 1974-10-15 | 1974-10-15 | Data separator with compensation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1505515A true GB1505515A (en) | 1978-03-30 |
Family
ID=24049505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB22873/75A Expired GB1505515A (en) | 1974-10-15 | 1975-05-23 | Clock pulse compensation circuit |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US3950658A (enExample) |
| JP (1) | JPS5151275A (enExample) |
| DE (1) | DE2535424A1 (enExample) |
| FR (1) | FR2288420A1 (enExample) |
| GB (1) | GB1505515A (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4281259A (en) * | 1978-11-08 | 1981-07-28 | Sanyo Electric Co., Ltd. | Digital phase comparing apparatus |
| JPS5850827A (ja) * | 1981-09-08 | 1983-03-25 | Fujitsu Ltd | フェーズ・ロック・ループ回路 |
| US4633488A (en) * | 1984-11-13 | 1986-12-30 | Digital Equipment Corporation | Phase-locked loop for MFM data recording |
| US4872155A (en) * | 1987-03-13 | 1989-10-03 | Pioneer Electronic Corporation | Clock generator circuit and a synchronizing signal detection method in a sampled format system and a phase comparator circuit suited for generation of the clock |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3080487A (en) * | 1959-07-06 | 1963-03-05 | Thompson Ramo Wooldridge Inc | Timing signal generator |
| US3238462A (en) * | 1963-09-18 | 1966-03-01 | Telemetrics Inc | Synchronous clock pulse generator |
| US3333205A (en) * | 1964-10-02 | 1967-07-25 | Ibm | Timing signal generator with frequency keyed to input |
| US3506923A (en) * | 1967-01-12 | 1970-04-14 | Ibm | Binary data detection system |
| US3510786A (en) * | 1967-07-17 | 1970-05-05 | Ibm | Synchronizing circuit compensating for data bit shift |
| US3731208A (en) * | 1971-05-17 | 1973-05-01 | Storage Technology Corp | Apparatus for and method of integration detection |
-
1974
- 1974-10-15 US US05/514,982 patent/US3950658A/en not_active Expired - Lifetime
-
1975
- 1975-05-23 GB GB22873/75A patent/GB1505515A/en not_active Expired
- 1975-08-08 DE DE19752535424 patent/DE2535424A1/de not_active Withdrawn
- 1975-08-11 FR FR7525825A patent/FR2288420A1/fr active Granted
- 1975-08-27 JP JP50103112A patent/JPS5151275A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| DE2535424A1 (de) | 1976-04-29 |
| US3950658A (en) | 1976-04-13 |
| FR2288420A1 (fr) | 1976-05-14 |
| JPS5151275A (enExample) | 1976-05-06 |
| FR2288420B1 (enExample) | 1978-04-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed [section 19, patents act 1949] | ||
| PCNP | Patent ceased through non-payment of renewal fee |