GB1488830A - Circuit arrangement for processing a chrominance signal - Google Patents

Abstract

1488830 Colour television INDESIT INDUSTRIA ELETTRODOMESTICI ITALIANA SpA 9 Oct 1974 [22 Oct 1973 12 June 1974] 43709/74 Heading H4F A half-line-frequency switching signal generator 14 in a PAL colour television receiver has its phase controlled in dependence on the output of a threshold detector 20 connected to the output of R-Y demodulator 15 receiving one input from subtractor 4 connected to a one (or three or five) line delay 5 and the circuit input, and receiving a reference signal input from PAL- switch 13. A burst gate 2 is controlled by a pulse shaper 7 receiving the switching signal from generator 14 and line synchronizing pulses 7 and transmits every second colour synchronizing burst to subcarrier oscillator 9; if the phase of generator 14 is correct oscillator 9 provides an output of B-Y phase and demodulators 10, 15 provide B-Y and R-Y outputs respectively, gates 16, 17 being blocked during line flyback intervals. If the phase of generator 14 is incorrect oscillator 9 provides an output at 90 degrees to the B-Y phase and demodulator 15 provides, due to delay 5 and subtractor 4, substantially no output; threshold detector 20 then blocks a gate 8 to block gates 16, 17 and to block generator 14 until it is in the correct phase. A second threshold detector may be connected to the output of the B-Y demodulator 10, which receives an input from adder 3, the outputs of the two threshold detectors being fed via an OR gate to gate 8. In an alternative embodiment the output of the B-Y demodulator is fed to a second threshold detector (57, Fig. 3, not shown), the outputs of the threshold detectors 20, (57) being supplied via an OR gate (56) to one input of a differential circuit (55), the output of which controls gate 8. Third and fourth demodulators are also included, the third demodulator (50) receiving inputs from adder 3 and 90 degrees phase shifter 11, and the fourth demodulator (51) receiving inputs from subtractor 4 and subcarrier oscillator 9; the third and fourth demodulators thus produce substantially no outputs for correct phase of generator 14, but outputs for incorrect phase of generator 14. The outputs of the third and fourth demodulators are fed via respective threshold detectors (52, 53) and a second OR gate (54) to the second input of the differential circuit (55).