GB1426271A - Decoding systems for colour television receivers - Google Patents

Abstract

1426271 Colour television SONY CORP 11 April 1973 [13 April 1972] 17313/73 Heading H4F A PAL colour television receiver uses at least one one-line delay line and at least one switch operated at the end of each line period to produce a first chrominance signal formed of each second received line repeated twice and a second chrominance signal which is equivalent to the signal which would be produced by delaying the first chrominance signal by one line period. The first and second chrominance signals are added together to produce a modified chrominance signal which is fed to demodulators, and the first and second chrominance signals are subtracted from each other to derive a signal for controlling the phase of operation of the switch. In one embodiment, Fig. 9, the received chrominance signal is supplied to switch 3, operated by flip-flop 8, switch 3 co-operating with one-line delay line 4 to produce the first chrominance signal at the output of switch 3 and the second chrominance signal at the output of amplifier 5, which signals are fed to adder 9 and subtractor 17. The output of adder 9 is passed to demodulators 11, 12 and via a burst gate 13 to an oscillator 14 which provides reference signals to the demodulators 11, 12 via 45 degree phase shifter 15 and 90 degree phase shifter 16. The output of subtractor 17 is fed to a gain-controlled amplifier 18 which also acts as a burst gate, the output of amplifier 18 containing, due to the action of subtracter 17, only the first subcarrier burst passed by switch 3 in each field. A gate 19 is controlled by circuit 20 to be conductive for one line period starting seven line periods after the rising edge of each vertical synchronizing pulse. If switch 3 is passing only bursts of +135 degrees phase relative to the (B-Y) axis the burst passed by amplifier 18 does not coincide with the line period during which gate 19 is conductive and the phase of operation of flip-flop 8 is unaltered. If, however, switch 3 is passing only bursts of -135 degrees phase, the burst passed by amplifier 18 in tha first and fourth field of each four-field cyclecoincides with the line period during which gate 19 is conductive, and detector 21 produces an output to reverse the phase of operation of flip-flop 8, and hence switch 3. In a second embodiment (Fig. 8, not shown) the output of amplifier 5 is not fed to switch 3, the delayed input to switch 3 being provided by a second one-line delay line and amplifier connected between amplifier 1 and switch 3. In a further embodiment (Fig. 3, not shown) a second switch operated at the end of each line period is provided, receiving inputs from amplifier 5 and amplifier 1, the first chrominance signal being produced at the output of this second switch, and the second chrominance signal being produced at the output of amplifier 5.