GB1473126A - - Google Patents

Info

Publication number
GB1473126A
GB1473126A GB3502774A GB3502774A GB1473126A GB 1473126 A GB1473126 A GB 1473126A GB 3502774 A GB3502774 A GB 3502774A GB 3502774 A GB3502774 A GB 3502774A GB 1473126 A GB1473126 A GB 1473126A
Authority
GB
United Kingdom
Prior art keywords
output
circuit
supplied
pal
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3502774A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of GB1473126A publication Critical patent/GB1473126A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00Details of colour television systems
    • H04N9/44Colour synchronisation
    • H04N9/465Synchronisation of the PAL-switch

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Processing Of Color Television Signals (AREA)
  • Color Television Systems (AREA)

Abstract

1473126 Colour television SONY CORP 8 Aug 1974 [10 Aug 1973] 35027/74 Heading H4F A known decoding system, Fig. 3, for a PAL chrominance signal is modified so that when a monochrome signal is received a PAL-switch 23 cannot be switched during active line periods in response to noise applied to a resonance circuit 34; such erroneous switching would produce noise on the reproduced monochrome picture. The PAL chrominance signal is supplied via band-pass amplifiers 12, 14 to a oneline delay circuit 17, an adder 15 and a subtractor 16. The output of adder 15 is supplied to a B-Y demodulator 21 and the output of subtractor 16 is supplied to an R-Y demodulator 26a via an inverter 24 and PAL-switch 23 operated, during reception of a colour signal, at the end of each line period. The output of band-pass amplifier 12 is fed to a burst gate 31 which supplies a colour killer circuit 39, a subcarrier oscillator 33 and a synchronous detector 32 which supplies a pulse signal to resonance circuit 34 the output of which is fed to a waveform shaping circuit 35 which controls the phase of a flip-flop 26 which also receives line synchronizing pulses at terminal 25 and controls PAL-switch 23. In one embodiment (Fig. 6, not shown) the line synchronizing pulses are supplied to the emitter of a transistor (44) included in shaping circuit 35, the base of the transistor receiving the output of the resonance circuit 34, so that this transistor is conductive, producing an output of circuit 35, only when a line synchronizing pulse coincides with the positive peak portion of the output of resonance circuit 34. In a second embodiment (Fig. 7, not shown) the colour killer signal from circuit 39 is also supplied to resonance circuit 34 to disable its operation during monochrome reception.
GB3502774A 1973-08-10 1974-08-08 Expired GB1473126A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9021573A JPS5524313B2 (en) 1973-08-10 1973-08-10

Publications (1)

Publication Number Publication Date
GB1473126A true GB1473126A (en) 1977-05-11

Family

ID=13992249

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3502774A Expired GB1473126A (en) 1973-08-10 1974-08-08

Country Status (6)

Country Link
JP (1) JPS5524313B2 (en)
DE (1) DE2438477A1 (en)
ES (1) ES429141A1 (en)
GB (1) GB1473126A (en)
IT (1) IT1019874B (en)
NL (1) NL7410709A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5224433A (en) * 1975-08-20 1977-02-23 Hitachi Ltd Tv color signal demodulator circuit of pal system
JPS5813045B2 (en) * 1976-01-30 1983-03-11 ソニー株式会社 Master-slave flip-flop circuit phase inversion circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5310808B2 (en) * 1972-01-20 1978-04-17

Also Published As

Publication number Publication date
DE2438477A1 (en) 1975-02-20
ES429141A1 (en) 1976-11-16
JPS5524313B2 (en) 1980-06-27
IT1019874B (en) 1977-11-30
JPS5039832A (en) 1975-04-12
NL7410709A (en) 1975-02-12

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee