DE2318491A1 - DECODING SYSTEM FOR COLOR TV RECEIVER - Google Patents

Description

It 2465 P / b

SONY CORPORATION, Tokyo, Japan Decoding system for color television receivers

The invention relates to a decoding system for a color television receiver, suitable for receiving a chrominance signal transmitted according to the PAL system, with a signal transformation circuit and a demodulation circuit for demodulating the chrominance signal transformed by the signal transformation circuit.

In the PAL system, a composite color television signal has two color signal components, commonly called color difference signals and which contain the chrominance information which has been simultaneously encoded by suppressed carrier wave quadrature amplitude modulation on a color subcarrier in the frame rate band, the phase of one modulation axis for one of the color components is reversed by 180 ° for each line period.

For decoding such a composite color television signal some systems are known, such as the so-called simple PAL system and standard PAL system. This conventional However, systems decode the PAL signals with the consequence of degradation the quality of the reproduced image, or they require a large increase in the complexity of the system.

In the patent application P 2 259 928.6 of December 7, 1972, a new system for decoding the PAL signals is that some of the known PAL decoding systems inherent

309843/0910

overcoming boundaries is proposed. The said proposed The new system can theoretically also be used to receive signals, either according to the PAIt system or according to the so-called NTSC system can be used, although the currently used color subcarrier frequencies are in both of these Television systems make it difficult to exploit this benefit.

The decoding system contained in the application includes an arrangement circuit and delay means connected to receive the incoming chrominance signal. The chrominance signal is first transmitted directly to demodulators for a line interval of time, and then the same information that with respect to time by a time interval by the delay means delayed, is again transmitted through the circuit to the demodulators for the next line interval. The one from the Chroma information transmitted to television station during the second line interval is not used by the receiver. That Signal transmitted during the third line interval is passed to the demodulators without delay and in a delayed manner Shape repeated during the fourth line interval with respect to time. As a result, a chrominance signal is obtained in which both modulation axes for two color signal components accordingly the fixed phases are held during the entire line intervals and is fed to the demodulators. In this case however, deterioration in the reproduced color image may be caused as a result of repeated use thereof Color information from any even or odd number of line intervals in consecutive two lines.

It is therefore the object of the invention that in the patent application mentioned P 2 259 928.6 to improve the proposed decoding system.

The system should have a special mixing circuit for chrominance signals for supplying a chrominance signal transformed by mixing to a demodulator.

309843/0910

This task is accomplished by a decoding system of the type described at the beginning Type solved, which is characterized according to the invention in that the signal transformation circuit has a first processing circuit for generating a first signal from segments of the incoming chrominance signal from essentially one Line interval and its afterimages, which are delayed by essentially one line interval and arranged alternately in succession are, and a second processing circuit for generating a second signal, which by delaying the first signal by substantially one line interval, and an addition circuit for adding the first and second signals have to each other for generating the transformed chrominance signal.

Further features and usefulnesses of the invention emerge from the description of exemplary embodiments on the basis of the figures. From the figures show:

Figs. 1 and 2 are vector diagrams for explaining a color television signal s according to the PAL system;

Fig. 3 is a circuit diagram for an embodiment

the invention;

FIGS. 4 and 5 are vector diagrams for explaining what is shown in FIG

decoding system shown;

6A, 6B, 6C, signal diagrams for explaining the decoding 7A, 7B, 7C _system;

Figures 8 and 9 are block diagrams of other embodiments of the

Decoding system;

10A and 10B are vector diagrams for explaining the advantages of the

-Decoding system; and

Figs. 11A, 11B, 11C are diagrams for explaining the advantages of the decoding system.

Before describing the actual invention, the PAL color television system described in connection with FIGS. 1 and 2.

309843/0910

The essence of the PAL color television system consists in the phase relationship between the two color difference signals / which are modulated on a common intermediate carrier to form a color diileaseaa signal. This phase relationship is shown in FIG. One of the chrominance components E «-E _v contains information relating to the blue components of the television picture. The other E _R -E _y contains information relating to the red components. Both chrominance components are modulated on the same carrier, or more correctly on the same subcarrier, but the modulation is separated and carried out in such a way that for a certain time interval corresponding to a line η of the color television picture the chrominance component E "-Ey with a modulation axis of phase Φ is modulated on the carrier. During the same time interval, the other chrominance component Sg-Ey is modulated on the carrier with a modulation axis of phase Φ _{ο y-.} For this

Basically, the chrominance component {Eg-Ey) _n , ^if ^ & ^@s *> ® "* represents the blue information in a correct time interval η, is represented by a horizontal arrow, and the red chrominance component ( ^E R ~ Ey) is η during the same line interval represented by a vertical arrow The vector addition of these two chrominance components gives a resulting signal F, which is a complex voltage represented by the expression (E ^ -Ey) + jt ^E R "" ^E y'n toeschxi
signal).

The phase relationship for the following line n + 1 is also shown in ± n Fig. 1. In this case, the chrominance component Ejj-Εγ is modulated with a modulation axis of phase φ _ο ^ r- on the carrier, and accordingly the chrominance component ^ B for the Line n + 1 is shown in the same direction as the component ί $ «- Ε _γ ) _η . According to the PAL system, however, the chrominance coroponent Ep-Ey is modulated with a modulation axis with a phase φ - *? (- $ LJ on the carrier, that is, with the phase opposite to the previous line n, and therefore the chrominance component (E _R - Ey) _{n + 1} for the line n + 1 opposite the component (E ^ -Ey) _{n shown} in the opposite direction, VisSaer can express the signal by the expression (Eg-Ey) ₊₁ - j (E _R -Ey) .. . (hereinafter referred to as the minus line signal).

3098 4 37 0910

The chrominance signal contains a subcarrier synchronization pulse (color synchronization signal), which is referred to below as a burst signal. The burst signal assumes different phases in the two signals F and F-. As shown in FIG. 2, the phase of the burst signal in the signal F _{n leads} counterclockwise by 45 ° with respect to the phase Φ _ο , as represented by B +, and the phase of the burst signal 'F ₊ - is "m unrzeigerpinn at 45 ° against d
is represented by B-.

Pointer spin by 45 ° against the phase 0 _o -fl; (- 0 _o ) delayed as it

_o -fl; (- 0 _o ) delay

The invention provides a decoding system for such a PAL color television signal, in which a predetermined demodulated color signal is forcibly generated and a reproduced image one has improved quality.

In the following, an embodiment of the invention is based on the Fig. 3 described.

A bandpass amplifier 1 separates a chrominance signal from a composite one Color television signal. The chrominance signal separated in this way becomes one of the input contact points of a switch circuit 2 and also to an input contact point of another circuit 3. The output of circuit 3 is fed to the other input contact point of the circuit 2 via a delay circuit 4, which is fed to it Signal delayed by a horizontal line interval, and further through an amplifier 5. The output signal of the amplifier 5 is also fed to the other input contact point of the circuit 3 via an intermediate circuit 6 (buffer). The circuits 2 and 3 are alternately with a switching signal in each line interval switched by a bistable flip-flop 8, which is actuated in reverse by a horizontal pulse 7 in each line interval will. If the circuit 2 is switched in the position shown, then the circuit 3 is also in the position shown

ο
switched. If the circuit is switched to the position that is opposite to the position shown in FIG. 3, then the circuit 3 is accordingly also switched to the position shown in FIG.

309843/0910

position shown reversed position switched. The output signal from the circuit 2 and the output of the amplifier 5 are added in the adder 9. The output signal of the Adder 9 is fed to first and second demodulators 11 and 12 via a bandpass amplifier 10. The output signal of the Bandpass amplifier 10 is also fed to a burst element 13, which then generates a burst signal. The burst signal is applied to an oscillator 14 and generates an output signal, which the first demodulator 11 as a reference signal after a delay of 45 ° with respect to the phase in a phase shifter 15 is supplied. The output signal of the phase shifter 15 is the second demodulator 12 as a reference signal after a Delay supplied by a phase shifter 16, which delays the signal applied to it with respect to the phase by 90 °.

In a subtraction stage 17, the output signal of the amplifier 5 is subtracted from that of circuit 2. The output signal of the subtracter 17 is gain-controlled Amplifier 18 is supplied, which can also serve as a burst element and generates a burst signal. The burst signal blanked out in this way becomes a member 19 is fed to which also the output signal of a key signal generator 20 is supplied, which is based on a vertical synchronization signal VD. The signal from the gate signal generator 20 can open the gate 19 or the gate 19 only from the time on make conductive during 1H (H represents a line interval) when the time periods 7H after the rising edge of the vertical tracking signal VD have passed. In this way, the gate 19 delivers only the burst signal that is at the output of the gain-controlled Amplifier 18 exists, during a predetermined 1H, to a detector 21 which determines the amplitude for the burst signal detected and the amplitude-detected signal of the bistable flip-flop 8 as a correction signal leads to § ».

In the circuit described with reference to FIG. 3, if the circuits 2 and 3 are in the positions shown when they hit of a plus signal and in the opposite position when a minus signal occurs, the circuit then generates 2 signals

■ 30984370910

nals of the type F _n , F _n ", F _{n + 2} , F ' _{n + 2} , F _{n + 4} , F« _{n + 4} -, .... consecutive, ie - those signals which consist of the original plus signals and of signals that alternatively arise by delaying the original plus signals by 1 line interval, while the amplifier 5 successively signals> of the type F ¹ * _o ,

F'ni ^F " _n # ^F ' _{n +} 2' ^F " n + 2 * ^F 'n + 4', ie those that

consist of signals obtained by delaying the original plus signals by one line interval and signals obtained alternatively by further delaying the previous one by one line interval. In other words, the above signals from the amplifier 5 are the same as those obtained by delaying those from the circuit 2 by one line interval. As a result, in the adder 9, the additions of F _{n +} P "- ^, P ' _{n +} F' _n , F _{n + 2} - * "V ^ρΙ _{η +} 2 ^{+ Ι} " η ₊ 2 'F ₊ 4 ~ ^F ".ο» ^F "+ 4 ~ ^F * +4» ···· carried out, That is, during a certain line interval for every other line interval the addition of an original line signal is carried out with that of two line intervals before, while signals delayed by one line interval are added during the next adjacent line interval Demodulators 11 and 12 are fed through the bandpass amplifier 10.

In the meantime, during a certain line interval in every second line interval of the original line signals in the line interval by two line intervals, previous line intervals are subtracted in the subtracter 17, such as F _n ^- * ¹¹ · _ ₂ ,

^F η ^F η ' ^F n + 2 ^F n' ^F n + 2 ^F n + 2 ' ^F n + 4 ^F n + 2 / ^F n + 4 ^F n + 4''

while line signals delayed by one line interval are added together during the next adjacent line interval.

In this case, the state of the burst signals in the signals obtained in the respective parts at the initial part of each field interval is the same as that shown in Fig. 4, and therefore the burst signal becomes B +, the same as the first burst -Signal H + in the signal from the bandpass amplifier 1 _; from the gain control amplifier 18 during the line inter-

3G9843 / 0910

vails H- received, within which the first burst signal B + exists. In the PAL signal, the start time of the field interval changes in the line interval H ^, within which the first burst signal B + is obtained from each field interval, i.e. the time period from the rising edge of the vertical syn-

, changes

chronisiersignals VD / with a period of four field intervals, as shown in Fig. 6A, and therefore the time period from the time becomes the rising edge of the vertical tracking signal VD to the line interval H- in which the first burst signal B + is obtained in this field interval, 6H in the first Field interval, 5.5H in the second field interval, 5H in the third field interval and 6.5H in the fourth field, interval. Correspondingly, as shown in Fig. 6C, a key signal G is supplied to the gate member 19 from the key signal generator 20, wherein the key signal G can open the member 19 during Time period 1H from the time that has elapsed since the rising edge of the vertical tracking signal VD by 7H in each field interval, so that in this case the element 19 does not pass any burst signal and therefore the detector 21 does not allow any display output signal generated with the result that the bistable multivibrator 8 maintains its reverse operation unchanged. That's why the circuits 2 and 3 kept unchanged in switching positions, as they have been described above, to the plus line signal continuously to the demodulators 11 and 12 in a state as described above.

Furthermore, it should be taken into account in this case that even in the interval in which the key signal G is obtained as it is through 4 and 6A, a noise component is added to the input of the gain control amplifier 18 is. However, since the gain-controlled amplifier 18 is designed in such a way that the gain of the Amplifier 18, which also works as a burst gate, is a maximum at the time when the burst signal is obtained, as indicated by the broken lines 22 in Fig. 6A, and thereafter can be abruptly decreased, the noise component can be greatly decreased. As a result, the detected output

309843/0910

signal is used as a correction signal for the flip-flop 8, and therefore it is avoided that the flip-flop 8 is switched.

In contrast, if the circuits 2 and 3 are switched to the positions opposite to those shown in FIG the line signals which are alternately delayed by one line signal from the former, such as ^F n + 1 ' ^F ' n + 1 ' ^F n + 3' ^F 'n + 3' ¹ W ^F 'n + 5' · "· ' ^{and the} amplifier 5 generates a signal from line signals obtained by delaying the original minus line signals by one line interval and those alternatively delayed by one line interval from the preceding ones, such as P ¹¹ _., F ^1. , F ". F ¹ ₃ , F ¹¹ ₃ , F ¹ ₅ , ..., ie the same as that delayed by the circuit 2 by one line interval. In this case, during one of the other line intervals, the original line signal in this line interval and the one two line intervals before are added in the adding stage 9, while signals delayed by one line interval are added during the next adjacent line interval, such as F _{n + 1} + ^F _n _-i /

P 'TP J-T?' 'TP' J. T? 'T? J-TT ''

^F n + 1 ' ^F n + 3 ^{+ F} n + 1' ^F n + 3 ^{+ F} n + 3 ' ^F n + 5 ^{+ F} n + 3

F ¹ , - + F ' _{n +} c t ···· · Correspondingly, the adder 9 only supplies the minus line signals via the amplifier 10 to the demodulators 11 and 12.

In the meantime, in this case, the line signals two line intervals before the original line signals in the interval are subtracted from the original line signals in the subtracting stage 17 during a certain of every other line interval, while the line signals delayed by one line interval are subtracted during the next adjacent line interval, such as F ₊₁ . - F ".,

T? '- T? 'T? _ T? · 'TP' - T? TP - TP ''

^F n + 1 ^F n + 1 ' ^F n + 3 ^F n + 1' ^F n + 3 ^F n + 3 ' ^F n + 5 ^F n + 3'

F - TP

n + 5 * n + 5 '

309843/0910

Accordingly, the state of the burst signals in the line signals, obtained from the respective parts, of the kind shown in Fig. 5 at the beginning part of each field interval, with the result that the burst signal B- is obtained from the gain controlled amplifier 18 during the line interval H- alone that follows the line interval H- in which the first burst signal B + is in the signal from the bandpass amplifier 1 exists. As shown in Fig. 6B, the time period from the rising edge of the vertical tracking signal is VD to the line interval H ~, within which the burst signal B-von the gain controlled amplifier 18, 7H in the first field, 6.5H in the second field, 6H in the third Field and 7.5H in the fourth field. Accordingly leaves in this case the gate 19, which is acted upon by the "blanking signal G mentioned above." becomes, the burst signal B- in the first field or the fourth field through. The burst signal B- is indicated by the detector 21 and is the correction signal. As a result, it switches the bistable multivibrator 8, which keeps its reverse operation in the manner shown in FIG. 7A, its operation with that in FIG. 7B correction signal shown in the manner shown in Fig. 7C, so that the circuits 2 and 3 in the positions shown can be switched when the plus line signal arrives, but in reverse when the minus line signal arrives of the first case. Therefore, the demodulators 11 and 12 become continuous with the plus line signal according to the above Condition applied.

With the structure described above, the demodulators 11 and 12 always successively applied with the plus line signals. As can be seen from Fig. 4, 'the burst signal, which is in The phase is with the burst signal B + and twice the amplitude of the burst signal B + is always obtained from the burst element 13. Accordingly, the oscillator 14 always generates an output signal which is in phase with the burst signal B +, and therefore the phase shifter 15 always supplies a reference signal to the demodulator 11 which is in phase with the R-Y axis, while the phase shifter 16 always enters the demodulator 12

309843/0910

Provides reference signal which is in phase with the B-Y axis, with the result that the demodulators 11 and 12 always generate demodulated color signals one after the other.

FIG. 8 shows another embodiment of the invention, in which the same reference numerals as in FIG. 3 have the same elements describe. In the embodiment in Fig. 8, there are two delay circuits 4A and 4B, which each delay the signal fed to them by one line interval, by one of the two circuits 2 and 3, the example shown in FIG have been used to omit, for example, the circuit. In the embodiment shown in Fig. 8, the chrominance signal from the bandpass amplifier 1, an input contact point of the Circuit 2 unchanged and the other input contact point of the same via the delay circuit 4A, which is fed to it Signal delayed by one line interval in the above-mentioned manner, and fed through an amplifier 5A. In this case the Circuit 2 is switched over in every line interval as in the former case. The output signal of the circuit 2 is via the Delay circuit 4B is supplied to an amplifier 5B. In the adder 9, the output signals from the circuit 2 and the amplifier 5B are added to each other, while in the subtracting stage 17 the output signal of the amplifier 5B, e.g. Output of the circuit 2 is subtracted. Furthermore For example, the circuit construction and operation of the circuit are substantially the same as in Fig. 3, so that for brevity of description can be dispensed with.

Fig. 9 shows a further embodiment of the invention, in which the same reference numerals as in Figs. 3 and 8 have the same components describe. In this embodiment, only one circuit, namely the circuit 3, and the delay circuit 4 used. In this exemplary embodiment, the chrominance signal supplied from the bandpass amplifier 1 to an input contact point of the circuit 3, and the output of the latter is the other input contact point of the circuit 3 via the delay circuit 4, the signal fed to it by a

309843/0910

Line interval delayed, fed to the amplifier 5 and the intermediate circuit 6. The circuit 3 is alternatively in each Line interval switched. In the adder 9 the output signals of the circuit 3 / aes amplifier 5 are added, while in the subtracter 17, the output signal of the amplifier 5 is subtracted, for example, from the output signal of the Circuit 3. The other circuit construction and operation are the same as in the previous embodiment, see above that their description is omitted for brevity.

It is apparent that the same operation as that in FIG The embodiment shown can be carried out with the embodiments shown in FIGS. 8 and 9. · ·

Various methods other than those mentioned above for obtaining the reference signal for demodulation can be considered. For example, it is possible for this purpose that the burst signals B + and B- in the chrominance signal from the bandpass amplifier 1 are fed to an oscillator for generating an output signal from the same, which can be in phase with the axis - (BY) just between the Burst signals B + and B-, and then to shift this output signal obtained in this way with respect to its phase. - -

With the circuits described above, the quality of the reproduced Image can be improved.

It can be used to achieve demodulation with the help of a reference signal be considered with a predetermined phase that the output of the circuit 2 which is the original chrominance signals contains, enterechenden signals and those caused by delay the former are obtained by one line interval in each line interval, which are alternatively derived, the demodulators 11 and 12 can be supplied without change, as shown in the above-mentioned application no. P 2 259 928.6 is described. at However, this method can, if a small error in the delay time caused by the delay circuit to generate a

309843 / 0.910

Phase shift of θ in delay of one line interval occurs when images have a vertical correlation, a phase error of θ between signals generated during an odd Number of line intervals to be demodulated, and the even number of line intervals to be generated, as shown in Figure 10A is shown. This can result in a deterioration in the quality of the reproduced images, what is called so-called Line flicker is called.

With this invention, during a certain line interval at every other line interval, the signal is modulated which is generated by adding the original line signal to the one by two line intervals before the former, such as ^F _n ^{+ F} '' _n _2 '

n + 2 n '* "* If the phase shift of θ is generated by delaying the signal by one line interval, and accordingly in the same case that the signal is further delayed by one line interval with the same delay circuit, then a phase shift of 2Θ is generated, where the phase shift of the signal to be demodulated during the above line interval becomes θ as shown in Fig. 10B. On the other hand, during the line interval besides the former, the signal formed by adding the line signals delayed by one line interval such as F ¹ + F ' , ^F ' _{n + 2} ^{+ F} ' _n + 2 '"' is ^de- modulated so that the phase shift of the signal to be demodulated becomes θ as shown in Fig. 10B. Therefore, even if the pictures have a vertical correlation, no phase shift occurs between the signals to be demodulated during the adjacent line intervals, and therefore the so-called line flicker is prevented by the invention.

In the case where the level of the line signal is changed by delaying one line interval, if that is the output signal of the circuit 2 signal corresponding to the demodulators 11 and 12 is supplied unchanged to achieve the demodulation the same in the manner described above, assuming that the level of the original line signal is 1 and that the signal a delayed by one line interval is the level difference

309843/0910

rence between the signals to be demodulated in adjacent two line intervals 1-a.

On the other hand, with the circuit according to the invention the level of the line signal a times the original when delayed by one line interval, and accordingly, if the signal is delayed by another line interval with the same delay circuit, the level of the delayed

2
Gerten signal a times as large as the original. In this way, during the line interval within which the original line signal was added to the previous two line intervals, the level of the line interval to be demodulated becomes

2
1 + a, while during the line period within which the signals delayed by one line interval have been added, the level of the signal to be demodulated becomes 2a. This results in the level difference between the above two cases (1 + a ² ) - 2a = (1-a) ² . If one takes into account that the value of the factor a is approximately 1. and therefore the relationship J 1-aJ ^ is satisfied, then the equation J1-aJ ^ (1-a) is also satisfied. For this reason it can be seen that the level difference to avoid line flicker can be greatly reduced with the circuit according to the invention.

Further, the content of the original chrominance signal changes successively between each line interval as shown in Fig. 11A and an inclined line indicated by a dashed line shown should disappear in a reproduced image when that is the output of the circuit corresponding signal unchanged to the demodulators 11 and 12 Demodulation of the same is supplied, then the dashed line flips Line in Fig. 11A does not appear but appears in steps as shown in Fig. 11B because the signals are in the same line interval to be repeated twice.

However, the content of the signals to be demodulated varies successively between each corresponding line interval, and the sloped line is reproduced with high accuracy, "

309843/0910

as shown in Fig. 11C.

As stated above, a predetermined demodulated color signal is inevitably always obtained with a simple structure.

Further, in the invention, there is a gain-controlled amplifier having a specific characteristic as mentioned above has been used to generate a burst signal to control the circuit, then stable operation can also can be obtained when the electric field of the transmitted signal is weak and contains a noise component.

The invention could also be used when two color signals Q and I signals would be.

309843/0910

Claims (9)

Claims Decoding system for a color television receiver, suitable for receiving a chrominance signal transmitted according to the PAL system, with a signal transformation circuit and a demodulation circuit for demodulating the from the signal transformation circuit transformed chrominance signal, characterized in that that the signal transformation circuit has a first processing circuit for generating a first signal from segments of the incoming chrominance signal of essentially one line interval and its afterimages by essentially one line interval delayed and successively arranged alternately, and a second processing circuit for generating a second Signal, which is formed by delaying the first signal by essentially one line interval, and an addition circuit for adding the first and second Have signals to each other for generating the transformed chrominance signal. 2. Decoding system according to claim 1, characterized in that the first processing circuit includes a delay device for delaying the incoming chrominance signal by substantially ' a line interval and a switching device for deriving the incoming chrominance signal and the delayed chrominance signal alternately in each line period and the second processing circuit further comprises a second delay device with a delay time of essentially one line interval, which corresponds to the output-side end of the switching device is connected. 3. Decoding system according to claim 2, characterized in that the adder is connected in parallel with the second delay device. 309843/0910 4 »Decoding system according to claim 1, characterized in that the first processing circuit includes a delay circuit for delaying the incoming chrominance signal by substantially one Line interval and a switching device for deriving the incoming chrominance signal and the delayed chrominance signal alternately in each line period and and the second processing circuit the delay circuit and feedback means for feeding the output signal from the delay circuit back to the delay circuit in each alternating line period. 5. Dekodiersystem.nach claim 4, characterized in that an additional switching device is provided in common with the first and second processing circuit means that the Switching device is connected to the input end of the delay device and the incoming chrominance signal and the delayed chrominance signal derived from the delay device alternately every line period to the delay device supplies. 6. Decoding system according to claim 4, characterized in that the switching device of the first processing circuit is common is used for part of the feedback link of the second processing circuit. 7. Decoding system according to claim 1, characterized in that the first and second processing circuits have a switch two input contact points and one output contact point, the input contact points alternating with each line period connected to the output contact point, a delay device with a delay time which is im is essentially equal to a line interval between one of the input contact points and the. Output contact point switched and a signal supply line for supplying the incoming chrominance signal to the other of the input contact points. 309843/0910 8. decoding system according to claim 7, characterized in that the adding circuit is connected in parallel with the delay device. 9. Decoding system according to claim 4 or 7, characterized in that a subtracting circuit in parallel with the adding circuit is intended to generate a signal as a result of the subtraction between the first and second signals for control the operation of the switching device in response to the result of the subtraction. 30 9843/0910 Blank page