GB1401678A - Decoding systems for colour television receivers - Google Patents

Abstract

1401678 Colour television SONY CORP 21 Aug 1972 [23 Aug 1971] 38837/72 Heading H4F A PAL colour television receiver uses a oneline delay line 3 and a switch 2 operated at half line-frequency to produce a chrominance signal having fixed modulation axes and bursts of constant phase, the switch 2 being operated by a flip-flop circuit 5 controlled so that switch 2 passes only signals having desired modulation axes to demodulators 6 and 7. In the embodiment shown the desired R-Y modulation axis is at + 90 degrees relative to the B-Y modulation axis; and the bursts in the signals passed by switch 2 are separated at 8 and control a reference oscillator 10 which feeds the demodulators 6 and 7 via 45 degree phase shifter 11 and 135 degree phase shifter 12 respectively. The output of phase shifter 12 is also passed to demodulators 13, 14 which receive the incoming chrominance signal from 1 and the delayed chrominance signal from 3 respectively. If switch 2 is operating as desired the output of phase shifter 11 has +(R-Y) phase, the output of phase shifter 12 has +(B-Y) phase and the outputs of demodulators 13 and 14 are equal, so that no signal is derived at the output of subtractor 15 and no signal is derived from control circuit 16. If, however, switch 2 is operating in antiphase to the desired operation, the output of phase shifter 11 has -(B-Y) phase, the output of phase shifter 12 has +(R-Y) phase, the outputs of demodulators 13 and 14 are antiphase and the alternating output of subtractor 15 causes control circuit 16 to change the state of switch 2 via flip-flop 5. Alternatively one demodulator (18, Fig. 6, not shown) may be used instead of demodulators 13, 14, the outputs of 1 and 3 being added before being supplied to the demodulator, and the control circuit producing an output signal in response to a zero output from the demodulator. In further embodiments (Figs. 8, 10, not shown) the outputs or inputs of the demodulators 13, 14 are added and subtracted, the resulting signals then being fed to a comparator circuit to derive a control signal to change the operation of switch 2 if necessary. In alternative embodiments (Figs. 11, 13, not shown) four demodulators are used in place of demodulators 13, 14, two (38, 40) being fed with the signal from 1 and two (39, 41) being fed with the delayed signal from 3, one demodulator of each pair (38, 39) receiving a reference signal from phase shifter 12 and the other demodulators (40, 41) receiving a reference signal from phase shifter 11, the resulting signals from the demodulators receiving the same reference signal being added or subtracted, the resulting two signals being passed to a comparator. In all the embodiments the signals fed to the demodulators such as 13, 14 may be the complete chrominance signals or only the bursts or the chrominance signals with the bursts removed. Signals in antiphase with those from phaseshifters, 11, 12 may be used as the reference signals.